Abstract: A method for fabricating a semiconductor structure is shown. A first gate of a first device and a second gate of a second device are formed over a semiconductor substrate. First LDD regions are formed in the substrate beside the first gate using the first gate as a mask. A conformal layer is formed covering the first gate, the second gate and the substrate, wherein the conformal layer has sidewall portions on sidewalls of the second gate. Second LDD regions are formed in the substrate beside the second gate using the second gate and the sidewall portions of the conformal layer as a mask.

Abstract: A method includes a patterned hard mask layer formed over a substrate. The substrate is etched using the patterned hard mask layer to form a trench therein but leaving at least one elongated portion of the substrate inside the trench. A first isolation layer is formed over the patterned hard mask layer. The first isolation layer fills the trench and covers the at least one elongated portion of the substrate. A portion of the first isolation layer is removed to expose the at least one elongated portion of the substrate. The at least one elongated portion of the substrate is thereafter removed to form a first opening. A second isolation layer is formed over the first opening, the patterned hard mask layer, and the first isolation layer, the second isolation layer sealing the first opening to form an air gap.

Abstract: Provided is a semiconductor device having favorable reliability.

Abstract: The present disclosure generally relates to a method for performing semiconductor device fabrication, and more particularly, to improvements in lithographic overlay techniques. The method for improved overlay includes depositing a material on a substrate, heating a substrate in a chamber using thermal energy, measuring a local stress pattern of each substrate, wherein measuring the local stress pattern measures an amount of change in a depth of the deposited material on the substrate, plotting a plurality of points on a k map to determine a local stress pattern of the substrate, adjusting the thermal energy applied to the points on the k map, determining a sensitivity value for each of the points on the k map, and applying a correction factor to the applied thermal energy to adjust the local stress pattern.

Abstract: A process for fabricating an integrated circuit is provided. The process includes providing a substrate, forming a hard mask upon the substrate by one of atomic-layer deposition and molecular-layer deposition, and exposing the hard mask to a charged particle from one or more charged particle beams to pattern a gap in the hard mask. In the alternative, the process includes exposing the hard mask to a charged particle from one or more charged-particle beams to pattern a structure on the hard mask.

Abstract: A technique is disclosed for causing the top surfaces of solder bumps on a chip to be in the same plane to ensure a more reliable bond between the chip and a substrate. The chip is provided with solder pads that may have different heights. A dielectric layer is formed between the solder pads. A relatively thick metal layer is plated over the solder pads. The metal layer is planarized to cause the top surfaces of the metal layer portions over the solder pads to be in the same plane and above the dielectric layer. A substantially uniformly thin layer of solder is deposited over the planarized metal layer portions so that the top surfaces of the solder bumps are substantially in the same plane. The chip is then positioned over a substrate having corresponding metal pads, and the solder is reflowed or ultrasonically bonded to the substrate pads.

Abstract: A semiconductor device includes a gate disposed over a substrate; a source region and a drain region on opposing sides of the gate; and a pair of trench contacts over and abutting an interfacial layer portion of at least one of the source region and the drain region; wherein the interfacial layer includes boron in an amount in a range from about 5×1021 to about 5×1022 atoms/cm2.

Abstract: A method for fabricating a touch display device is provided. The method includes: forming a sensor on a substrate, and forming a sensing signal line electrically connected to the sensor. The method of forming the sensor includes: forming a semiconductor layer including a semiconductor pattern of the sensor on the substrate, forming a gate insulation layer on the semiconductor layer, forming a first conductor layer on the gate insulation layer, forming an interlayered insulation layer on the gate insulation layer, performing an annealing process, removing the interlayered insulation layer on a gate predetermined region after the annealing process is performed, removing the first conductor layer on the gate predetermined region, forming a gate in the gate predetermined region, and forming a second conductor layer including a source and a drain of the sensor respectively electrically connected to the semiconductor pattern of the sensor.

Abstract: In various embodiments, an optoelectronic component is provided. The optoelectronic component includes a metal substrate having a surface, an electrically conductive planarization layer on the surface of the metal substrate, wherein the planarization layer comprises a surface, an organically functional layer structure on or above the surface of the planarization layer, and an electrode layer formed in a transparent fashion on or above the organically functional layer structure. The roughness of the surface of the planarization layer is lower than the roughness of the surface of the metal substrate. The surface of at least one of the metal substrate or the planarization layer is formed in a light-scattering fashion.

Abstract: A semiconductor device includes active pillars protruding from a semiconductor substrate and spaced apart from each other in a first direction and a second direction that is perpendicular to the first direction, a word line extending in the first direction between the active pillars, a drain region disposed in an upper portion of each of the active pillars, and a separation pattern provided between the word line and the drain region. A bottom surface of the separation pattern is disposed at a lower level than a bottom surface of the drain region.

Abstract: A FinFET includes a substrate, a fin structure on the substrate, a source in the fin structure, a drain in the fin structure, a channel in the fin structure between the source and the drain, a gate dielectric layer over the channel, and a gate over the gate dielectric layer. At least one of the source and the drain includes a bottom SiGe layer.

Abstract: Provided is a light-emitting device that can display an image with a wide color gamut or a novel light-emitting element. The light-emitting device includes a plurality of light-emitting elements each of which includes an EL layer between a pair of electrodes. Light obtained from a first light-emitting element through a first color filter has, on chromaticity coordinates (x, y), a chromaticity x of greater than 0.680 and less than or equal to 0.720 and a chromaticity y of greater than or equal to 0.260 and less than or equal to 0.320. Light obtained from a second light-emitting element through a second color filter has, on chromaticity coordinates (x, y), a chromaticity x of greater than or equal to 0.130 and less than or equal to 0.250 and a chromaticity y of greater than 0.710 and less than or equal to 0.810. Light obtained from a third light-emitting element through a third color filter has, on chromaticity coordinates (x, y), a chromaticity x of greater than or equal to 0.120 and less than or equal to 0.

Abstract: Semiconductor devices having air gap spacers that are formed as part of BEOL or MOL layers of the semiconductor devices are provided, as well as methods for fabricating such air gap spacers. For example, a method comprises forming a first metallic structure and a second metallic structure on a substrate, wherein the first and second metallic structures are disposed adjacent to each other with insulating material disposed between the first and second metallic structures. The insulating material is etched to form a space between the first and second metallic structures. A layer of dielectric material is deposited over the first and second metallic structures using a pinch-off deposition process to form an air gap in the space between the first and second metallic structures, wherein a portion of the air gap extends above an upper surface of at least one of the first metallic structure and the second metallic structure.

Abstract: The present disclosure provides one embodiment of an etch system. The etch system includes a tank designed to hold an etch solution for etching; a silicon monitor configured to measure silicon concentration of the etch solution; a drain module coupled to the tank and being operable to drain the etch solution; and a supply module being operable to fill in the tank with a fresh etch solution.

Abstract: A method includes forming a first mandrel layer above a first process layer. A first implant region is formed in the first mandrel layer. The first mandrel layer is patterned to define a plurality of first mandrel elements. At least a first subset of the first mandrel elements is formed from the first mandrel layer outside the first implant region and a second subset of the first mandrel elements is formed from the first implant region. First spacers are formed on sidewalls of the plurality of first mandrel elements. The first subset of the first mandrel elements are selectively removed without removing the second subset of the first mandrel elements. The first process layer is patterned using the first spacers and the second subset of the first mandrel elements as an etch mask.

Abstract: A stack of MTJ layers is provided on a substrate comprising a bottom electrode, a pinned layer, a tunnel barrier layer, a free layer, and a top electrode. The MTJ stack is patterned to form a MTJ device wherein sidewall damage is formed on its sidewalls. A dielectric spacer is formed on the MTJ device. The dielectric spacer is etched away on horizontal surfaces wherein the dielectric spacer on the sidewalls is partially etched away. The remaining dielectric spacer covers the pinned layer and bottom electrode. The dielectric spacer is removed from the free layer or is thinner on the free layer than on the pinned layer and bottom electrode. Sidewall damage is thereafter removed from the free layer by applying a horizontal etching to the MTJ device wherein the pinned layer and bottom electrode are protected from etching by the dielectric spacer layer.

Abstract: An integrated circuit may be formed by forming an isolation recess in a single-crystal silicon-based substrate. Sidewall insulators are formed on sidewalls of the isolation recess. Thermal oxide is formed at a bottom surface of the isolation recess to provide a buried isolation layer, which does not extend up the sidewall insulators. A single-crystal silicon-based semiconductor layer is formed over the buried isolation layer and planarized to be substantially coplanar with the substrate adjacent to the isolation recess, thus forming an isolated semiconductor layer over the buried isolation layer. The isolated semiconductor layer is laterally separated from the substrate.

Abstract: A method is presented for forming a diffusion barrier in a field effect transistor with a source. A raised source is formed at least partially on the source with the raised source comprising III-V material. An interfacial layer is formed at least partially on the raised source with the interfacial layer comprising silicon or germanium. A metal layer is formed at least partially on the interfacial layer with the metal layer comprising transition metal. The diffusion barrier is formed at least partially on the raised source with the diffusion barrier layer comprising transition metal from the metal layer bonded to silicon or germanium from the interfacial layer. Similar processing forms a corresponding diffusion barrier on a raised drain.

Abstract: A semiconductor device includes a semiconductor region with a charge balance region on a junction blocking region, the junction blocking region having a lower doping concentration. The junction blocking region extends between a pair of trench structures in cross-sectional view. The trench structures are provided in the semiconductor region and include at least one insulated electrode. In some embodiments, the semiconductor device further includes a first doped region disposed between the pair of trench structures. The semiconductor device may further include one or more features configured to improve operating performance. The features include a localized doped region adjoining a lower surface of a first doped region and spaced apart from the trench structure, a notch disposed proximate to the lower surface of the first doped region, and/or the at least one insulated electrode configured to have a wide portion adjoining a narrow portion.

Abstract: A plating method can improve adhesivity with a substrate. The plating method of performing a plating process on the substrate includes forming a vacuum-deposited layer 2A on the substrate 2 by performing a vacuum deposition process on the substrate 2; forming an adhesion layer 21 and a catalyst adsorption layer 22 on the vacuum-deposited layer 2A of the substrate 2; and forming a plating layer stacked body 23 having a first plating layer 23a and a second plating layer 23b which function as a barrier film on the catalyst adsorption layer 22 of the substrate 2. By forming the vacuum-deposited layer 2A, a surface of the substrate 2 can be smoothened, so that the vacuum-deposited layer 2A serving as an underlying layer can improve the adhesivity.