Abstract: A Metal-Insulator-Metal (MIM) capacitor structure and method of fabricating the same in an integrated circuit improve capacitance density in a MIM capacitor structure by utilizing a sidewall spacer extending along a channel defined between a pair of legs that define portions of the MIM capacitor structure. Each of the legs includes top and bottom electrodes and an insulator layer interposed therebetween, as well as a sidewall that faces the channel. The sidewall spacer incorporates a conductive layer and an insulator layer interposed between the conductive layer and the sidewall of one of the legs, and the conductive layer of the sidewall spacer is physically separated from the top electrode of the MIM capacitor structure. In addition, the bottom electrode of a MIM capacitor structure may be ammonia plasma treated prior to deposition of an insulator layer thereover to reduce oxidation of the electrode.

Abstract: A field effect transistor of the present invention includes, on a semiconductor substrate, (i) a fin section formed in a fin shape protruding from the substrate, (ii) a gate dielectric for covering a channel region section of the fin section, (iii) a gate electrode that is insulated from the channel region section by the gate dielectric and is formed on the channel region section and (iv) an insulating layer for covering a surface of the semiconductor substrate. The fin section is formed so as to extend from the semiconductor substrate through the insulating layer and protrudes outward from a surface of the insulating layer. In this way, the channel region of the fin section is physically in contact with the substrate.

Abstract: Microelectronic imaging units and methods for manufacturing a plurality of imaging units at the wafer level are disclosed herein. In one embodiment, a method for manufacturing a plurality of imaging units includes providing an imager workpiece having a plurality of imaging dies including integrated circuits, external contacts electrically coupled to the integrated circuits, and image sensors operably coupled to the integrated circuits. The individual image sensors include at least one dark current pixel at a perimeter portion of the image sensor. The method includes depositing a cover layer onto the workpiece and over the image sensors. The method further includes patterning and selectively developing the cover layer to form discrete volumes of cover layer material over corresponding image sensors. The discrete volumes of cover layer material have sidewalls aligned with an inboard edge of the individual dark current pixels such that the dark current pixels are not covered by the discrete volumes.

Abstract: Methods for forming a semiconductor structure are described. In an embodiment, the technique includes providing a donor wafer having a first semiconductor layer and a second semiconductor layer on the first layer and having a free surface; coimplanting two different atomic species through the free surface of the second layer to form a zone of weakness zone in the first layer; bonding the free surface of the second layer to a host wafer; and supplying energy to detach at the zone of weakness a semiconductor structure comprising the host wafer, the second layer and a portion of the first layer.

Abstract: An electroluminescent device comprising: a first charge carrier injecting layer for injecting positive charge carriers; a second charge carrier injecting layer for injecting negative charge carriers; and a light-emissive layer located between the charge carrier injecting layers and comprising a mixture of: a first component for accepting positive charge carriers from the first charge carrier injecting layer; a second component for accepting negative charge carriers from the second charge carrier injecting layer; and a third, organic light-emissive component for generating light as a result of combination of charge carriers from the first and second components; at least one of the first, second and third components forming a type II semiconductor interface with another of the first, second and third components.

Abstract: The present invention includes a method for forming a memory array and the memory array produced therefrom. Specifically, the memory array includes at least one first-type memory device, each of the at least one first-type memory device comprising a first transistor and a first underlying capacitor that are in electrical contact to each other through a first buried strap, where the first buried strap positioned on a first collar region; and at least one second-type memory cell, where each of the at least are second-type memory device comprises a second transistor and a second underlying capacitor that are in electrical contact through an offset buried strap, where the offset buried strap is positioned on a second collar region, wherein the second collar region has a length equal to the first collar region.

Abstract: This invention is related to a thin film transistor (TFT) array and method of making same, for use in an active matrix liquid crystal display (AMLCD) having a high pixel aperture ratio. The TFT array and corresponding display are made by forming the TFTs and corresponding address lines on a substrate, coating the address lines and TFTs with a photo-imageable insulating layer which acts as a negative resist, exposing portions of the insulating layer with UV light which are to remain on the substrate, removing non-exposed areas of the insulating layer so as to form contact vias, and depositing pixel electrodes on the substrate over the insulating layer so that the pixel electrodes contact respective TFT source electrodes through the contact vias. The resulting display has an increased pixel aperture ratio because the pixel electrodes are formed over the insulating layer so as to overlap portions of the array address lines.

Abstract: An integrated circuit package is provided. The package includes a substrate having first and second surfaces and a plurality of conductive traces therebetween. The substrate further has a cavity therein and a heat slug is fixed to the substrate and spans the cavity. A semiconductor die is mounted to the heat slug such that at least a portion of the semiconductor die is disposed in the cavity. A plurality of wire bonds connect the semiconductor die to ones of the conductive traces of the substrate and an encapsulating material encapsulates the wire bonds and the semiconductor die. A ball grid array is disposed on the first surface of the substrate. Bumps of the ball grid array are in electrical connection with ones of the conductive traces.

Abstract: According to a resin encapsulation molding method for a semiconductor device, a resin-encapsulated substrate having a semiconductor device that is mounted on the substrate and that has a portion exposed is formed. With the method, a device-mounted substrate on which the semiconductor device is mounted is prepared and then the device-mounted substrate is set in one mold part. A release film is thereafter provided between the device-mounted substrate and the other mold part opposite to that one mold part. The one and other mold parts are then closed to press the release film against the portion of the semiconductor device. The device-mounted substrate has a projection enclosing the portion of the semiconductor device for preventing resin flash from being formed. When the mold parts are closed, the release film is pressed against the projection to allow the projection to dig into the release film.

Abstract: In one embodiment, a method for forming a silicon-based material on a substrate having dielectric materials and source/drain regions thereon within a process chamber is provided which includes exposing the substrate to a first process gas comprising silane, methylsilane, a first etchant, and hydrogen gas to deposit a first silicon-containing layer thereon. The first silicon-containing layer may be selectively deposited on the source/drain regions of the substrate while the first silicon-containing layer may be etched away on the surface of the dielectric materials of the substrate. Subsequently, the process further provides exposing the substrate to a second process gas comprising dichlorosilane and a second etchant to deposit a second silicon-containing layer selectively over the surface of the first silicon-containing layer on the substrate.

Abstract: A method for fabricating a semiconductor device that forms a capacitor and metal interconnection in the same level, simultaneously using a damascene process for forming a metal interconnection. A capacitor structure having the high capacitance needed for logic elements is obtained without increasing the number of layers for fabricating the capacitor by forming a three-dimensional capacitor in the damascene pattern while maintaining the conventional processes in a damascene interconnection process.

Abstract: Provided is a manufacturing method of a semiconductor device which has the following steps of forming a plurality of layered patterns obtained by stacking an insulating film, a conductor film for forming a floating gate electrode and another insulating film over a semiconductor substrate in the order of mention, forming sidewalls over the side surfaces of the plurality of layered patterns, removing a damage layer of the semiconductor substrate between any two adjacent layered patterns by dry etching, forming an insulating film over the semiconductor substrate between two adjacent layered patterns, and forming a plurality of assist gate electrodes over the insulating film between two adjacent layered patterns in self alignment therewith. According to the present invention, a semiconductor device having a flash memory has improved reliability.

Abstract: Complementary IGFETs (210W and 220W or 530 and 540) are fabricated so that the body dopant concentration in each IGFET decreases by at least 10 in moving from a subsurface location in the body material of that IGFET up to one of its source/drain zones. Semiconductor dopant, typically a fast-diffusing species such as aluminum, is introduced into starting semiconductor material to form a relatively uniformly doped region that serves as body material (108) for one of the IGFETs. A remaining part of the starting material serves as body material (268) for the other IGFET. Well dopant is introduced into the body material of each IGFET for establishing the requisite body dopant profile. Alternatively, a cavity is formed through an initial structure having body material (108) doped in the preceding way for one of the IGFETs. Semiconductor material is introduced into the cavity to form the body material (568) for the other IGFET.

Abstract: A method of forming a semiconductor structure, and the semiconductor structure so formed, wherein a transmission line, such as an inductor, is formed on a planar level above the surface of a last metal wiring level.

Abstract: A silicon film is crystallized in a predetermined direction by selectively adding a metal element having a catalytic action for crystallizing an amorphous silicon and annealing. In manufacturing TFT using the crystallized silicon film, TFT provided such that the crystallization direction is roughly parallel to a current-flow between a source and a drain, and TFT provided such that the crystallization direction is roughly vertical to a current-flow between a source and a drain are manufactured. Therefore, TFT capable of conducting a high speed operation and TFT having a low leak current are formed on the same substrate.

Abstract: A non-volatile semiconductor memory (30) comprising a semiconductor substrate (1) and a plurality of memory cells (19) and methods for manufacturing such a memory is provided. Each memory cell (19) comprises a charge-trapping element (5), a gate stack (20), nitride spacers (10) and electrically insulating elements (21). The charge-trapping element (5) is arranged on the semiconductor substrate (1) and comprises a nitride layer (3) sandwiched between a bottom oxide layer (2) and a top oxide layer (4), the charge-trapping element (5) having two lateral sidewalls (24) opposed to one another. The gate stack (20) is arranged on top of the charge-trapping element (5), the gate stack having two lateral sidewalls (25) opposing one another. The electrically insulating elements (21) are disposed at opposing sidewalls (24) of the charge-trapping element (5) and cover the sidewalls (24) of the charge-trapping element (5).

Abstract: A method for forming a single-crystal silicon film of high quality is provided. The method includes the operations of: growing single-crystal silicon to a predetermined thickness of a crystal growth plate; depositing a buffer layer on the single-crystal silicon layer; forming a partition layer at a predetermined depth in the single-crystal silicon layer by implanting hydrogen ions in the single-crystal silicon layer from an upper portion of an insulating layer; attaching a substrate onto the buffer layer; and cutting the partition layer of the single-crystal silicon layer by heating the partition layer from the crystal growth plate to obtain a single-crystal silicon layer of a predetermined thickness on the substrate.

Abstract: A gate dielectric is treated with a nitridation step and an anneal. After this, an additional nitridation step and anneal is performed. The second nitridation and anneal results in an improvement in the relationship between gate leakage current density and current drive of the transistors that are ultimately formed.

Abstract: In a method of manufacturing a bonded substrate stack by bonding the bonding surfaces of the first and second substrates, a bonding surface having a hydrophobic region and a hydrophilic region is formed by partially processing at least one of the bonding surfaces of the first and second substrates, and then the bonding surfaces of the first and second substrates are bonded to each other.

Abstract: An electroluminescent device comprising: a first charge carrier injecting layer for injecting positive charge carriers; a second charge carrier injecting layer for injecting negative charge carriers; and a light-emissive layer located between the charge carrier injecting layers and comprising a mixture of: a first component for accepting positive charge carriers from the first charge carrier injecting layer; a second component for accepting negative charge carriers from the second charge carrier injecting layer; and a third, organic light-emissive component for generating light as a result of combination of charge carriers from the first and second components; at least one of the first, second and third components forming a type II semiconductor interface with another of the first, second and third components.