Abstract: A method of manufacturing a semiconductor memory device comprises forming floating gates on active regions of a semiconductor substrate and forming a capping layer on the floating gates. An isolation layer located in the semiconductor substrate between the floating gates is anisotropically etched using the capping layer as an etch mask to form recessed regions. The recessed regions are formed to have a width smaller than a distance between the floating gates, and bottom surfaces positioned below bottom surfaces of the floating gates. Control gate electrodes are formed across the active regions over the floating gates and the control gate electrodes have control gate extensions formed within the recessed regions between the floating gates.

Abstract: A method for implementing a desired offset in device characteristics of an integrated circuit includes forming a first device of a first conductivity type on a first portion of a substrate having a first crystal lattice orientation, and forming a second device of the first conductivity type on a second portion of the substrate having a second crystal lattice orientation. The carrier mobility of the first device formed on the first crystal lattice orientation is greater than the carrier mobility of the second device formed on the second crystal lattice orientation.

Abstract: A first laser beam is emitted from a first laser oscillator in a pulsed manner at a high repetition frequency, and converged onto a substrate by a first intermediate optical system 2 so as to form a slit-like first beam spot. A second laser beam is emitted from a second laser beam oscillator in a pulsed manner to rise precedent to and fall subsequent to the first laser beam, and converged onto the substrate by a second intermediate optical system so as to form a second beam spot similar in configuration to the first beam spot and to contain the first beam spot. Crystallization of a semiconductor thin film on the substrate is carried out while the substrate or the first, second beam spots are moved. Thereby, the whole semiconductor thin film is formed into a crystal surface that has grown in one direction and free from ridges. Thus, the semiconductor thin film has an extremely flat surface, extremely few defects, large crystal grains and high throughput.

Abstract: Integrated circuit field effect transistor devices include a substrate having a surface and an active channel pattern on the surface. The active channel pattern includes channels that are stacked upon one another and are spaced apart from one another to define at least one tunnel between adjacent channels. A gate electrode surrounds the channels and extends through the at least one tunnel. A pair of source/drain regions also is provided. Integrated circuit field effect transistors are manufactured, by forming a pre-active pattern on a surface of a substrate. The pre-active pattern includes a series of interchannel layers and channel layers stacked alternately upon each other. Source/drain regions are formed on the substrate at opposite ends of the pre-active pattern. The interchannel layers are selectively removed to form tunnels. A gate electrode is formed in the tunnels and surrounding the channels.

Abstract: A method for fabricating a semiconductor device for a system on chip (SOC) for embodying a transistor for a logic device, an electrical erasable programmable read only memory (EEPROM) cell and a flash memory cell in one chip is provided. Floating gates of the EEPROM cell and the flash memory cell are formed by using a first polysilicon layer; and a gate electrode of the logic device and control gates of the EEPROM cell and the flash memory cell are formed by using a second polysilicon layer. Thus, it is possible to stably form the logic device, the EEPROM cell and the flash memory cell in one chip.

Abstract: A method for fabricating stacked non-volatile memory cells and non-volatile memory cell arrays are disclosed. A semiconductor wafer is provided having a charge-trapping layer and a conductive layer deposited on the surface of the semiconductor wafer. Using a mask layer on top of the conductive layer, contact holes are formed into which a contact fill material is deposited. A further conductive layer is deposited on the surface of the semiconductor wafer and is patterned so as to form word lines. The contact fill material is connected to a contact plug using the contact holes with the contact fill material as a landing pad.

Abstract: A method for fabricating a liquid crystal display includes providing a first substrate having a pixel part and a driving circuit part, forming a gate electrode in the pixel part of the first substrate, forming a first insulation film, a first amorphous silicon thin film and a second amorphous silicon thin film on the first substrate, forming a first conductive film on the first substrate, having the first insulation film, the first amorphous silicon thin film, and the second amorphous silicon thin film, selectively patterning the first conductive film, the second amorphous silicon thin film and the first amorphous silicon thin film to form an active pattern in each of the pixel part and the driving circuit part of the first substrate and source and drain electrodes, crystallizing the first amorphous silicon thin film constituting the active pattern of the driving circuit part, forming a second insulation film on the first substrate, forming a pixel electrode in the pixel part and a gate electrode in the drivi

Abstract: A system, method and apparatus for processing a semiconductor device including a processing chamber and a heating assembly positioned within the processing chamber. The heating assembly including at least a plate defining an internal cavity configured to receive gas. The gas enters the internal cavity through a first passage at a first temperature, and exits the internal cavity at a second temperature through a second passage.

Abstract: A semiconductor fabrication process includes forming a recess in a semiconductor substrate. A silicon germanium film is formed on a sidewall of the recess. A gate dielectric and gate electrode are formed adjacent the silicon germanium film. Source/drain regions are then formed wherein a first source/drain region is adjacent a first side of the gate electrode in an upper surface of the substrate and a second source/drain region adjacent a second side of the gate electrode is below a lower surface of the recess. Etching the exposed portion of the substrate may be done so as to form a rounded corner at the junction of the recess sidewall and the recess lower surface. The silicon germanium film formation is preferably epitaxial. An epitaxial silicon film may be formed adjacent the silicon germanium film.

Abstract: A self-aligned, thin-film, top-gate transistor and method of manufacturing same are disclosed. A first print-patterned mask is formed over a metal layer by digital lithography, for example by printing with a phase change material using a droplet ejector. The metal layer is then etched using the first print-patterned mask to form source and drain electrodes. A semiconductive layer and an insulative layer are formed thereover. A layer of photosensitive material is then deposited and exposed through the substrate, with the source and drain electrodes acting as masks for the exposure. Following development of the photosensitive material, a gate metal layer is deposited. A second print-patterned mask is then formed over the device, again by digital lithography. Etching and removal of the photosensitive material leaves the self-aligned top-gate electrode.

Abstract: Methods are provided for forming a semiconductor device from a substrate comprising a bottom gate layer, a channel layer overlying the bottom gate layer, and a top gate structure formed over the channel layer. First, a hardmask comprising a first material interposed between a second material and a third material is deposited over a portion of the top gate structure. Then, the hardmask and top gate structure are encapsulated with an insulating material to form a spacer. A channel structure is formed from the channel layer, and the channel structure is disposed under the spacer. A bottom gate structure is formed from the bottom gate layer, and the bottom gate structure is disposed under the channel structure. Then, a source/drain contact is formed around the bottom gate structure.

Abstract: The invention relates to the field of electronics, more particularly to the wire bonds incorporated into an integrated circuit package such as a quad flat pack, a ball grid array or hybrid style module. The present invention takes the normally undesirable wire bond inductance and uses it in an operational circuit where positive inductance is required. The circuit in which the wire bond inductance is used is located primarily in the integrated circuit die housed in the integrated circuit package, but may also include off-die components. In one example, a wire bond is used as the required series inductance in a discrete circuit impedance inverter which consists of two shunt-to-ground negative inductances and one series positive inductance. One of the negative inductances is located on-die, while the other is located off-die.

Abstract: The invention relates to a side-emitting LED package and a manufacturing method of the same. The invention provides a side-emitting LED package for emitting light from a light source sideward including a substrate with an electrode formed thereon. The package also includes a light source disposed on the substrate, a molded part that covers and protects the substrate with the light source thereon, and a reflective layer that covers an outer surface of the molded part. The molded part with the reflective layer forms a light transmitting surface in one side thereof. The invention allows easy manufacture of a reflecting surface in a desired shape, miniaturization regardless of the LED chip size, mass-production in an LED array, significantly improving productivity.

Abstract: An SOI FET comprising a silicon substrate having silicon layer on top of a buried oxide layer having doped regions and an undoped region is disclosed. The doped region has a dielectric constant different from the dielectric constant of the doped regions. A body also in the silicon layer separates the source/drains in the silicon layer. The source/drains are aligned over the doped regions and the body is aligned over the undoped region. A gate dielectric is on top of the body and a gate conductor is on top of the gate dielectric.

Abstract: The present invention describes a method including the steps of providing a single crystal semiconductor substrate, forming a layer of rare earth silicide on a surface of the semiconductor substrate, forming a first layer of insulating material on the layer of rare earth silicide, forming a layer of electrically conductive material on the first layer of insulating material, and forming a second layer of insulating material on the layer of electrically conductive material. In one embodiment the step of forming the layer of rare earth silicide includes depositing a layer of rare earth metal on a surface of the semiconductor substrate depositing a layer of insulating material on the layer of rare earth metal, and annealing the structure to form a layer of rare earth silicide in conjunction with the surface of the semiconductor substrate and a rare earth doped insulating layer in conjunction with the layer of insulating material.

Abstract: A memory cell having a bit line contact is provided. The memory cell may be a 6F2 memory cell. The bit line contact may have a contact hole bounded by insulating sidewalls, and the contact hole may be partially or completely filled with a doped polysilicon plug. The doped polysilicon plug may have an upper plug surface profile that is substantially free of concavities or substantially convex. Similarly, a storage node contact may comprise a doped polysilicon plug having an upper plug surface profile that is substantially free of concavities or that is substantially convex. Additionally, a semiconductor device having a conductive contact comprising a polysilicon plug may is provided. The plug may contact a capacitor structure.

Abstract: Provided are a vertical field-effect transistor, a method of manufacturing the same, and a display device having the same. The method is highly reproducible and can be used to manufacture a vertical organic field-effect transistor at a low cost. In addition, the method does not require photolithography and a shadow mask. In the vertical field-effect transistor, a source electrode is formed on a substrate, and an insulating layer and discontinuous gate electrodes are formed. Then, a charge carrier block layer, an organic semiconductor material, and a drain electrode are formed. The gate electrodes are formed using nanoparticles.

Abstract: The invention is directed to a thin-film capacitor device that is adapted to be mounted on a printed wiring board together with an LSI device. After forming a plurality of grooves in a core substrate, a first conductive film is formed, and a first conductor is filled into each groove. After forming a metal film on the first conductive film, a dielectric film is generated by selective anodic oxidation of the metal film. A second conductive film is formed on the dielectric film, and an electrode connected to the second conductive film is formed. After removing the back surface of the core substrate until the grooves are exposed therein, an electrode for connection to the first conductor in each groove is formed. A capacitor is formed by the first conductive film and second conductive film sandwiching the dielectric film therebetween.

Abstract: Disclosed are a multi-layer printed circuit board and a method for manufacturing the multi-layer printed circuit board. Circuit layers and insulating layers are alternately stacked so that via holes of the circuit layers provided with plated inner walls without application of additional plating and conductive paste-filling steps are connected to via holes of the insulating layers filled with a conductive paste.

Abstract: The invention includes methods of forming a substrate having a surface comprising at least one of Pt, Pd, Co and Au in at least one of elemental and alloy forms. In one implementation, a substrate is provided which has a first substrate surface comprising at least one of Pt, Pd, Co and Au in at least one of elemental and alloy forms. The first substrate surface has a first degree of roughness. Within a chamber, the first substrate surface is exposed to a PF3 comprising atmosphere under conditions effective to form a second substrate surface comprising at least one of Pt, Pd, Co and Au in at least one of elemental and alloy forms which has a second degree of roughness which is greater than the first degree of roughness. The substrate having the second substrate surface with the second degree of roughness is ultimately removed from the chamber.