Abstract: An organic light emitting device display may include transverse row and column lines. In a passively driven OLED display, a fuse may be positioned between the OLED material and the row electrode. When a short occurs, the single pixel may be separated from the circuit by the fuse, avoiding the possibility that an entire row of pixels may be adversely affected by the short associated with one single pixel along a row.

Abstract: There is provided a technique for obtaining improved maximum allowed value for the antenna ratio while inhibiting the damage on the gate insulating film of the MOSFET. A semiconductor device having a configuration that comprises a silicon substrate, a contact interlayer film, a first interconnect interlayer film, a first via interlayer film and a second interconnect interlayer film, all of which are sequentially formed in this order, comprises two protective diodes, which are coupled to a MOSFET via the second interconnect.

Abstract: A bi-directional read/program non-volatile memory cell and array is capable of achieving high density. Each memory cell has two spaced floating gates for storage of charges thereon. The cell has spaced apart source/drain regions with a channel therebetween, with the channel having three portions. One of the floating gate is over a first portion; another floating gate is over a second portion, and a gate electrode controls the conduction of the channel in the third portion between the first and second portions. An independently controllable control gate is insulated from each of the source/drain regions, and is also capacitively coupled to the floating gate. The cell programs by hot channel electron injection, and erases by Fowler-Nordheim tunneling of electrons from the floating gate to the gate electrode. Bi-directional read permits the cell to be programmed to store bits, with one bit in each floating gate.

Abstract: A method for fabricating improved integrated circuit devices. The method enables selective hardening of gate oxide layers and includes providing a semiconductor substrate having a gate oxide layer formed thereover. A resist is then formed over the gate oxide layer and patterned to expose one or more areas of the gate oxide layer which are to be hardened. The exposed portions of the gate oxide layer are then hardened using a true remote plasma nitridation (RPN) scheme or a high-density plasma (HDP) RPN scheme. Because the RPN scheme used in the method of the present invention runs at low temperature, the patterned resist remains stable through the RPN process, and those areas of gate oxide layer which are exposed by the patterned resist are selectively hardened by the RPN treatment, while those areas covered by the patterned resist remain unaffected.

Abstract: Chemical vapor deposition methods are used to deposit amorphous silicon-containing films over various substrates. Such methods are useful in semiconductor manufacturing to provide a variety of advantages, including uniform deposition over heterogeneous surfaces, high deposition rates, and higher manufacturing productivity. Preferably, the deposited amorphous silicon-containing film is annealed to produce crystalline regions over all or part of an underlying substrate.

Abstract: The current invention provides for encapsulated release structures, intermediates thereof and methods for their fabrication. The multi-layer structure has a capping layer, that preferably comprises silicon oxide and/or silicon nitride, and which is formed over an etch resistant substrate. A patterned device layer, preferably comprising silicon nitride, is embedded in a sacrificial material, preferably comprising polysilicon, and is disposed between the etch resistant substrate and the capping layer. Access trenches or holes are formed in to capping layer and the sacrificial material are selectively etched through the access trenches, such that portions of the device layer are release from sacrificial material. The etchant preferably comprises a noble gas fluoride NGF2x (wherein Ng=Xe, Kr or Ar: and where x=1, 2 or 3). After etching that sacrificial material, the access trenches are sealed to encapsulate released portions the device layer between the etch resistant substrate and the capping layer.

Abstract: A method of making an isolation-less, contact-less array of bi-directional read/program non-volatile memory cells is disclosed. Each memory cell has two stacked gate floating gate transistors, with a switch transistor there between. The source/drain lines of the cells and the control gate lines of the stacked gate floating gate transistors in the same column are connected together. The gate of the switch transistors in the same row are connected together. Spaced apart trenches are formed in a substrate in a first direction. Floating gates are formed in the trenches, along the side wall of the trenches. A buried source/bit line is formed at the bottom of each trench. A control gate common to both floating gates is also formed in each trench insulated from the floating gates, capacitively coupled thereto, and insulated from the buried source/bit line.

Abstract: The formation of gate spacers on the sides of a gate structure on a semiconductor substrate is provided. In one embodiment, a gate structure is formed on a gate insulator layer of the semiconductor substrate. A liner layer is formed over the exposed surfaces of the substrate, the gate insulator layer, and the gate structure. A layer of gate spacer material is formed over the liner layer. Thereafter, gate spacers are formed from the layer of gate spacer material. A protection layer is formed over portions of the liner layer, gate structure, and the gate spacers. The protection layer is etched back. A first wet etch procedure is performed to remove exposed portions of the liner layer. The protection layer is removed and a second wet etch procedure is performed to remove substantially a top portion and a bottom portion of the liner layer.

Abstract: A method for fabricating a variable capacitive device including providing a base silicon-bearing compound electrode which is vertically-inclined with respect to a substrate, depositing a sacrificial layer on the base electrode, depositing a silicon-bearing compound electrode on the sacrificial layer which is also vertically-inclined with respect to the substrate, and removing the sacrificial layer from between the base silicon-bearing compound electrode and the grown silicon-bearing compound electrode. A variable capacitive device having a fixed vertically-inclined silicon-bearing compound electrode and a movable vertically-inclined silicon-bearing compound electrode produced by arranging a sacrificial layer on a base silicon-bearing compound electrode, depositing a grown silicon-bearing compound electrode on the sacrificial layer, and etching the sacrificial layer. Between the fixed silicon-bearing compound and the movable silicon-bearing compound electrode is a nanogap, the nanogap having a uniform width.

Abstract: It is an object of the present invention to enhance a selection ratio in an etching process, and provide a method for manufacturing a semiconductor device that has favorable uniform characteristic with high yield. In a method for manufacturing a semiconductor device according to the present invention, a semiconductor layer is formed, a gate insulating film is formed on the semiconductor film, a first conductive layer is formed on the gate insulating film, a second conductive layer is formed on the first conductive layer, the first conductive layer and the second conductive layer are etched to form a first conductive-layer pattern, the second conductive layer in the first conductive-layer pattern is selectively etched with plasma of boron trichloride, chlorine, and oxygen to form a second conductive-layer pattern, and a first impurity region and a second impurity region are formed in the semiconductor layer.

Abstract: A semiconductor processing method of forming a conductive gate or gate line over a substrate includes, a) forming a conductive gate over a gate dielectric layer on a substrate, the gate having sidewalls and an interface with the gate dielectric layer; b) electrically insulating the gate sidewalls; and c) after electrically insulating the gate sidewalls, exposing the substrate to oxidizing conditions effective to oxidize at least a portion of the gate interface with the gate dielectric layer. According to one aspect of the invention, the step of exposing the substrate to oxidizing conditions is conducted after provision of a first insulating material and subsequent anisotropic etch thereof to insulate the gate sidewalls. According to another aspect of the invention, the step of exposing the substrate to oxidizing conditions is conducted after provision of first and second insulating materials and subsequent anisotropic etch thereof to insulate the gate sidewalls.

Abstract: A method for forming an oxide layer on a vertical, non-planar semiconductor surface provides a low stress oxide layer having a pristine interface characterized by a roughness of less than 3 angstroms. The oxide layer includes a portion that is substantially amorphous and notably dense. The oxide layer is a graded growth oxide layer including a composite of a first oxide portion formed at a relatively low temperature below the viscoelastic temperature of the oxide film and a second oxide portion formed at a relatively high temperature above the viscoelastic temperature of the oxide film. The process for forming the oxide layer includes thermally oxidizing at a first temperature below the viscoelastic temperature of the film, and slowly ramping up the temperature to a second temperature above the viscoelastic temperature of the film and heating at the second temperature.

Abstract: A process for producing a resin-sealed semiconductor device having high reliability which is produced more easily and efficiently without voids, the process comprising the steps of: (a) providing a semiconductor wafer having circuits on a surface; (b) applying a resin sheet composed of a support and an adhesive resin layer releasable from the support, on the circuit surface of the semiconductor wafer, and fixing an outer periphery of the resin sheet with a ring frame; (c) cutting the semiconductor wafer and the resin layer by each circuit to form chips; (d) picking up each chip together with the resin layer from the support; (e) mounting each chip on a predetermined position of a chip mounting substrate through the resin layer; and (f) firmly bonding the chip on the chip mounting substrate so as to achieve conduction between the chip and the chip mounting substrate.

Abstract: The invention generally teaches a method for depositing a silicon film or silicon germanium film on a substrate comprising placing the substrate within a process chamber and heating the substrate surface to a temperature in the range from about 600° C. to about 900° C. while maintaining a pressure in the range from about 0.1 Torr to about 200 Torr. A deposition gas is provided to the process chamber and includes SiH4, an optional germanium source gas, an etchant, a carrier gas and optionally at least one dopant gas. The silicon film or the silicon germanium film is selectively and epitaxially grown on the substrate. One embodiment teaches a method for depositing a silicon-containing film with an inert gas as the carrier gas. Methods may include the fabrication of electronic devices utilizing selective silicon germanium epitaxial films.

Abstract: The invention includes semiconductor devices. In one implementation, semiconductor device includes a first conductive material. A first layer of a dielectric material is over the first conductive material. A second layer of the dielectric material is on the first layer. A second conductive material is over the second layer of the dielectric material. A device in accordance with an implementation of the invention can include a pair of capacitor electrodes having capacitor dielectric material therebetween comprising a composite of two immediately juxtaposed and contacting, yet discrete, layers of the same capacitor dielectric material.

Abstract: A first area, a ring shape second area surrounding the first area, and a third area surrounding the second area are defined on the surface of a support substrate. A first wiring layer is disposed above the support substrate. A wiring is formed in the third area, dummy patterns being formed in the second area, and conductive patterns are not formed in the first area. A functional element is disposed above the first wiring layer and in the first area.

Abstract: A method for cleaning and forming an oxide film on a surface, particularly a silicon surface. The surface is initially cleaned and then exposed to ozone vapor, which forms the oxide film on the surface. The method is particularly useful for forming a pre-liner oxide film on trench surfaces in the fabrication of STI (shallow trench isolation) structures.

Abstract: A method of fabricating a non-volatile memory is provided. A plurality of columns of isolation structures are formed on a substrate. A plurality of rows of stacked gate structures crossing over the isolation structures are formed on the substrate. A plurality of doping regions are formed in the substrate between two neighboring stacked gate structures. A plurality of stripes of spacers are formed on the sidewalls of stacked gate structures. A plurality of first dielectric layers are formed on a portion of the isolation structures adjacent to two rows of stacked gate structures. Also, one isolation structure is disposed between two neighboring first dielectric layers in the same row, while two neighboring rows comprising the first dielectric layer and the isolation structure are arranged in an interlacing manner. A plurality of first conductive layers are formed between two neighboring first dielectric layers in the same row.

Abstract: Various methods are provided for forming metal interconnection layers of semiconductor devices.

Abstract: A flash EEPROM array having a double-diffused source junction that can be used for source side programming. The flash EEPROM array, when programmed from the source side exhibits fast programming rates. Additionally, source side programming of arrays having different physical characteristics (e.g. transistor cell channel length) exhibit tighter program rate distributions than for the same arrays in which drain side programming is used.