Abstract: Contaminants from surfaces of temperature sensitive substrates, such as glass substrates are removed by exposing the surfaces to a hydrogen Surface-mixed diffusion flame for a predetermined duration of time. The predetermined duration of time being insufficient to heat up the surfaces substantially thereby causing damage to the temperature sensitive substrates.

Abstract: The memory device includes a source region and a drain region in a substrate and spaced apart from each other; a memory cell formed on a surface of the substrate, wherein the memory cell connects the source region and the drain region and includes a plurality of nanocrystals; a control gate formed on the memory cell. The memory cell includes a first tunneling oxide layer formed on the substrate; a second tunneling oxide layer formed on the first tunneling oxide layer; and a control oxide layer formed on the second tunneling oxide layer. The control oxide layer includes the nanocrystals. The second tunneling oxide layer, having an aminosilane group the increases electrostatic attraction, may be hydrophilic, enabling the formation of a monolayer of the nanocrystals.

Abstract: The compound semiconductor device comprises an i-GaN buffer layer 12 formed on an SiC substrate 10; an n-AlGaN electron supplying layer 16 formed on the i-GaN buffer layer 12; an n-GaN cap layer 18 formed on the n-AlGaN electron supplying layer 16; a source electrode 20 and a drain electrode 22 formed on the n-GaN cap layer 18; a gate electrode 26 formed on the n-GaN cap layer 18 between the source electrode 20 and the drain electrode 22; a first protection layer 24 formed on the n-GaN cap layer 18 between the source electrode 20 and the drain electrode 22; and a second protection layer 30 buried in an opening 28 formed in the first protection layer 24 between the gate electrode 26 and the drain electrode 22 down to the n-GaN cap layer 18 and formed of an insulation film different from the first protection layer.

Abstract: The present invention provides a method for forming a wiring having a minute shape on a large substrate with a small number of steps, and further a wiring substrate formed by the method. Moreover, the present invention provides a semiconductor device in which cost reduction and throughput improvement are possible due to the small number of steps and reduction of materials and which has a semiconductor element with a minute structure, and further a manufacturing method thereof. According to the present invention, a composition including metal particles and organic resin is irradiated with laser light and a part of the metal particles is baked to form a conductive layer typified by a wiring, an electrode or the like over a substrate. Further, a semiconductor device having the baked conductive layer as a wiring or an electrode is formed.

Abstract: Disclosed herein is a method for forming a highly conductive metal pattern which comprises forming a metal pattern on a substrate by the use of a photocatalyst and a selective electroless or electroplating process, and transferring the metal pattern to a flexible plastic substrate. According to the method, a highly conductive metal pattern can be effectively formed on a flexible plastic substrate within a short time, compared to conventional formation methods. Further disclosed is an EMI filter comprising a metal pattern formed by the method. The EMI filter not only exhibits high performances, but also is advantageous in terms of low manufacturing costs and simple manufacturing process. Accordingly, the EMI filter can be applied to a variety of flat panel display devices, including PDPs and organic ELs.

Abstract: An optical device with an iridium oxide (IrOx) electrode neural interface, and a corresponding fabrication method are provided. The method provides a substrate and forms a first conductive electrode overlying the substrate. A photovoltaic device having a first electrical interface is connected to the first electrode. A second electrical interface of the photovoltaic device is connected to a second conductive electrode formed overlying the photovoltaic device. An array of neural interface single-crystal IrOx nanostructures are formed overlying the second electrode, where x?4. The IrOx nanostructures can be partially coated with an electrical insulator, such as SiO2, SiN, TiO2, or spin on glass (SOG), leaving the IrOx distal ends exposed. In one aspect, a buffer layer is formed overlying the second electrode surface, made from a material such as LiNbO3, LiTaO3, or SA, for the purpose of orienting the growth direction of the IrOx nanostructures.

Abstract: An integrated circuit (IC) includes a high voltage first-conductivity type field effect transistor (HV-first-conductivity FET) and a high voltage second-type field effect transistor (HV-second-conductivity FET). The HV first-conductivity FET has a second-conductivity-well and a field oxide formed over the second-conductivity-well to define an active area. A first-conductivity-well is formed in at least a portion of the active area, wherein the first-conductivity-well is formed to have the capability to operate as a first-conductivity-drift portion of the HV-first-conductivity FET. The HV second-conductivity FET has a first-conductivity-well and a field oxide formed over the first-conductivity-well to define an active area. A channel stop region is formed in at least a portion of the active area, wherein the channel stop region is formed to have the capability to operate as second-conductivity-drift portions of the HV-second-conductivity FET.

Abstract: A method of assembling large numbers of nanoscale structures in pre-determined ways using fluids or capillary lithography to control the patterning and arrangement of the individual nanoscale objects and nanostructures formed in accordance with the inventive method are provided. In summary, the current method uses the controlled dispersion and evaporation of fluids to form controlled patterns of nanoscale objects or features anchored on a substrate, such as nanoscale fibers like carbon nanotubes.

Abstract: A device of forming a film from an organic compound material at low cost is provided, using an organic compound material having high light emission efficiency. An organic compound film is formed on a substrate under an inert gas atmosphere by spraying of a colloid solution in which organic compound aggregates are dispersed (this solution is also referred to as a “sol”). Note that the organic compound may be one in which particles are composed of aggregates of several organic compounds within a liquid, and may be one in which a portion of the organic compound is dissolved within a liquid.

Abstract: A method of fabricating a TFT using dual or multiple gates, and a TFT having superior characteristics and uniformity by providing a method of fabricating a TFT using dual or multiple gates by calculating the probability including Nmax, the maximum number of crystal grain boundaries in active channel regions according to the length of the active channels, and adjusting a gap between the active channels capable of synchronizing the number of the crystal grain boundaries in each active channel region of the TFT using the dual or multiple gates in the case where Gs, the size of crystal grains of polycrystalline silicon forming a TFT substrate, ? angle in which “primary” crystal grain boundaries are inclined at a direction perpendicular to an active channel direction of the gates, the width of the active channels and the length of the active channels are determined.

Abstract: A semiconductor chip having an adhesive layer previously formed on an element forming surface thereof and having a bump exposed from the surface of the adhesive layer is wire-bonded to a printed circuit board. Another semiconductor chip is stacked on the above semiconductor chip with the adhesive layer disposed therebetween and is wire-bonded to the printed circuit board by wire bonding. Likewise, at least one semiconductor chip is sequentially stacked on the thus attained semiconductor structure to form a stack MCP.

Abstract: A method of forming cell bitline contact plugs is disclosed in the present invention. After providing a semiconductor substrate with a first region and a second region, cell bitline contacts are formed at the first region. After forming bitline pattern openings at the second region, poly spacers are formed on sidewalls of the cell bitline contacts and the bitline pattern openings. A substrate contact and a gate contact are then formed within the openings at the second region. After forming a trench around each of the substrate contact and the gate contact by performing an etching process, cell-bitline contact plugs, a substrate contact plug, and a gate contact plug are formed.

Abstract: A memory cell and method of forming the same is provided. To make contact between a bit line and a select transistor of a dynamic memory unit on a semiconductor wafer, a contact hole is filled with a metal or a metal alloy. A liner layer may be introduced between the semiconductor substrate and the metal filling. The semiconductor substrate has a doped region in the contact hole.

Abstract: The invention includes masking methods. In one implementation, a masking material which includes boron doped amorphous carbon is formed over a feature formed on a semiconductor substrate. The masking material includes at least about 0.5 atomic percent boron. The masking material is substantially anisotropically etched effective to form an anisotropically etched sidewall spacer which includes the boron doped amorphous carbon on a sidewall of the feature. The substrate is then processed proximate the spacer while using the boron doped amorphous carbon-including spacer as a mask. After processing the substrate proximate the spacer, the boron doped amorphous carbon-including spacer is etched from the substrate. Other implementations and aspects are contemplated.

Abstract: This invention relates to novel, transparent oxide semiconductor thin film transistors (TFT's) and a process for making them.

Abstract: A method of forming a metal wiring layer of a semiconductor device produces metal wiring that is free of defects. The method includes forming an insulating layer pattern defining a recess on a substrate, forming a conformal first barrier metal layer on the insulating layer pattern, and forming a second barrier metal layer on the first barrier metal layer in such a way that the second barrier metal layer will facilitate the growing of metal from the bottom of the recess such that the metal can fill a bottom part of the recess completely and thus, form damascene wiring. An etch stop layer pattern is formed after the damascene wiring is formed so as to fill the portion of the recess which is not occupied by the damascene wiring.

Abstract: A semiconductor memory includes memory cell transistors comprising a tunnel insulating film, a floating gate electrode, a first insulating film, a control gate electrode, and a first metal salicide film; low-voltage transistors comprising a first p-type source region and a first p-type drain region, a first gate insulating film, and a first gate electrode of an n conductivity type having the same dose of a first p-type impurity as with the first p-type source region; and high-voltage transistors comprising a second p-type source region and a second p-type drain region, a second gate insulating film thicker than the first gate insulating film, and a second gate electrode of an n conductivity type having the same dose of a second p-type impurity as with the second p-type source region.

Abstract: Salient electrodes on a semiconductor chip and leads on a film substrate are to be connected together with a high accuracy. A change in lead pitch which occurs at the time of connecting salient electrodes on a semiconductor chip and inner leads on a film substrate with each other is taken into account and a correction is made beforehand to the pitch of the inner leads. Likewise, a change in lead pitch which occurs at the time of connecting electrodes on a liquid crystal substrate and outer leads on the film substrate with each other is taken into account and a correction is made beforehand to the pitch of the outer leads.

Abstract: Provided is a method of forming a heterojunction of contiguous layers of organic semiconducting polymers. The method comprises firstly forming a layer of a first organic semiconducting polymer on a substrate. A solution of a film-forming material is then deposited on the layer of the first organic semiconducting polymer. The first organic semiconducting polymer is insoluble in this solution and so is not disturbed by its deposition. The deposited solution is then dried to form a temporary film having a thickness of less then 20 nm formed from the film-forming material. Next a solution of a second organic semiconducting polymer dissolved in an organic solvent is deposited on the temporary film and this solution dried. The solubility of the material forming the temporary film in the organic solvent and the thickness of the temporary film are such that the organic solvent permeates through the thickness of the temporary film during drying of the solution of the second organic semiconducting polymer.

Abstract: Methods are provided for fabricating an SOI component on a semiconductor layer/insulator/substrate structure including a diode region formed in the substrate. The method comprises, in accordance with one embodiment, forming a shallow trench isolation (STI) region extending through the semiconductor layer to the insulator. A layer of polycrystalline silicon is deposited overlying the STI and the semiconductor layer and is patterned to form a polycrystalline silicon mask comprising at least a first mask region and a second mask region. First and second openings are etched through the STI and the insulator using the mask as an etch mask. N- and P-type ions are implanted into the diode region through the openings to form the anode and cathode of the diode. The anode and cathode are closely spaced and precisely aligned to each other by the polycrystalline silicon mask. Electrical contacts are made to the anode and cathode.