Abstract: A method of forming a dual damascene opening comprising the following steps. A structure having an overlying exposed conductive layer formed thereover is provided. A dielectric layer is formed over the exposed conductive layer. An anti-reflective coating layer is formed over the dielectric layer. The anti-reflective layer and the dielectric layer are etched using a via opening process to form an initial via exposing a portion of the conductive layer. A protective film portion is formed over at least the exposed portion of the conductive layer. The anti-reflective coating layer and the dielectric layer are patterned to reduce the initial via to a reduced via and to form a trench opening substantially centered over the reduced via. The trench opening and the reduced via comprising the dual damascene opening.

Abstract: Consistent with example embodiments a semiconductor device and a method are disclosed for obtaining on a substrate a multilayer structure with a quantum well structure. The quantum well structure comprises a semiconductor layer sandwiched by insulating layers, wherein the material of the insulating layers has preferably a high dielectric constant. In a field effect transistor (FET) the quantum wells function as channels, allowing a higher drive current and a lower off current. Short channel effects are reduced. The multi-channel FET is suitable to operate even for sub-35 nm gate lengths. In the method the quantum wells are formed by epitaxial growth of the high dielectric constant material and the semiconductor material alternately on top of each other, preferably with molecular beam epitaxy (MBE).

Abstract: Methods are disclosed of fabricating a compound nitride semiconductor structure. A substrate is disposed over a susceptor in a processing chamber, with the susceptor in thermal communication with the substrate. A group-III precursor and a nitrogen precursor are flowed into the processing chamber. The susceptor is heated with a nonuniform temperature profile to heat the substrate. A nitride layer is deposited over the heated substrate with a thermal chemical vapor deposition process within the processing chamber using the group-III precursor and the nitrogen precursor.

Abstract: Compositions and methods are provided herein that include modifications to at least one surface of a silicon-based semiconductor material. Modifications occur in a liquid and comprise alterations of surface states, passivation, cleaning and/or etching of the surface, thereby providing an improved surface to the semiconductor material. Modifications of surface states include reduction or elimination of an electrically active state of the surface, wherein, at the atomic level, the surface binding characteristics are changed. Passivation includes the termination of dangling bonds on the surface of the semiconductor material.

Abstract: Methods of processing a semiconductor structure including a metal layer in the presence of organic material include flowing an aqueous mixture including an oxidizing agent over the semiconductor structure during processing of the semiconductor structure. Processing the semiconductor structure may include sawing the semiconductor structure and/or scrubbing the semiconductor structure with pressurized water. The oxidizing agent may include a peroxide, such as hydrogen peroxide, or another oxidizing agent.

Abstract: Organic FETs are produced having high mobilities in the accumulation mode and in the depletion mode. Significantly higher mobility is obtained from FETs in which RR-P3HT film is applied by dip-coating to a thickness of only about 20 ? to 1 ?m. It was found that the structural order of the semiconducting polymer at the interface between the semiconducting polymer and the SiO2 gate-insulator is important for achieving high carrier mobility. Heat-treatment under an inert atmosphere also was found to increase the on/off ratio of the FET.

Abstract: The present invention provides a semiconductor device having a coating film of a predetermined thickness provided along the circumference of a semiconductor light emitting element, and provide a method for easily manufacturing the semiconductor device. A semiconductor light emitting element 2 that emits blue light is mounted face down on the top face of a pedestal 1, and a coating film 3 containing a YAG fluorescent material 6 that emits yellow light is placed so as to cover the top face and side face of the semiconductor light emitting element 2 and the top face of the pedestal 1. With the semiconductor light emitting element 2 and other elements placed between a first film 8 and a second film 9, the films are laminated in vacuum, thereby to fasten the coating film 3 onto the semiconductor light emitting element 2.

Abstract: Phase-changeable memory devices include non-volatile memory cells. Each of these non-volatile memory cells may include a phase-changeable diode on a semiconductor substrate and a phase-changeable memory element having a first terminal electrically coupled to a terminal of the phase-changeable diode. This phase-changeable diode may include a lower electrode pattern on the semiconductor substrate, a first phase-changeable pattern on the lower electrode pattern and a gate switching layer pattern on the first phase-changeable pattern. The phase-changeable memory element includes a second phase-changeable pattern electrically coupled to the terminal of the phase-changeable diode and a memory switching layer pattern on the second phase-changeable pattern. The memory switching layer pattern may include a composite of a titanium layer pattern contacting the phase-changeable memory element and a titanium nitride layer pattern contacting the titanium layer pattern.

Abstract: A doped region in a semiconductor substrate is activated by irradiation of electromagnetic waves having a main spectrum peak at a wavelength of 1.1 ?m or less. The efficiency of electromagnetic wave absorption of the silicon substrate increases in use of such electromagnetic waves in comparison with heat treatment using conventional infrared light, such as a tungsten halogen lamp. Accordingly, only a desired very small area in the substrate can be locally heated with a region using a thermally unstable material maintained at a temperature of 400° C. or less. For example, activation can be performed after forming a metal or alloy layer or an insulating interlayer over the semiconductor substrate, or after bonding an adhesive coating film and a support substrate to the semiconductor substrate.

Abstract: One embodiment of the present invention is a method for fabricating a nanoscale shift register. In a described embodiment, a nanoimprinting-resist layer applied above a silicon-on-insulator substrate is nanoimprinted to form troughs and trough segments. The silicon layer exposed at the bottom of the troughs and trough segments is then etched, and a conductive material is deposited into the troughs to form nanowires and into the trough segments to form nanowire segments. The exposed surfaces of nanowires are coated with a protective coating, and the conductive material of the nanowire segments is then removed to produce trough segments etched through the nanoimprinting resist and the silicon layer.

Abstract: A method of forming a semiconductor device includes forming a first dielectric layer over a semiconductor substrate, forming a plurality of discrete storage elements over the first dielectric layer, thermally oxidizing the plurality of discrete storage elements to form a second dielectrics over the plurality of discrete storage elements, and forming a gate electrode over the second dielectric layer, wherein a significant portion of the gate electrode is between pairs of the plurality of discrete storage elements. In one embodiment, portions of the gate electrode is in the spaces between the discrete storage elements and extends to more than half of the depth of the spaces.

Abstract: A method of creating metal caps on copper lines within an inter-line dielectric (ILD) deposits a thin (e.g., 5 nm) metal blanket film (e.g., Ta/TaN) on top the copper lines and dielectric, after the wafer has been planarized. Further a thin dielectric cap is formed over the metal blanket film. A photoresist coating is deposited over the thin dielectric cap and a lithographic exposure process is performed, but without a lithographic mask. A mask is not needed in this situation, because due to the reflectivity difference between copper and the ILD lying under the two thin layers, a mask pattern is automatically formed for etching away the Ta/TaN metal cap between copper lines. Thus, this mask pattern is self-aligned above the copper lines.

Abstract: In a semiconductor device having a capacitor and a method of fabricating the same, the semiconductor device comprises a semiconductor substrate having a memory cell array region and a peripheral region, a plurality of capacitors in the memory cell array region each having a storage electrode, a dielectric layer on the storage electrode, and a plate electrode on the dielectric layer, wherein an extended portion of the plate electrode extends in a direction toward the peripheral region, a dummy pattern in the peripheral region at an elevation above the semiconductor substrate that is substantially the same as that of the extended portion of the plate electrode and spaced apart from the extended portion of the plate electrode, an insulating layer formed on the plurality of capacitors in the cell array region and formed on the dummy pattern in the peripheral region, a first metal contact through the insulating layer between the extended portion of the plate electrode and the dummy pattern.

Abstract: Metal interconnection lines of semiconductor devices and methods of forming the same are disclosed. Improved reliability is achieved in a disclosed metal line of a semiconductor device by preventing metal layers from eroding and preventing metal lines from being destroyed due to electro-migration (EM) and stress-migration (SM). An illustrated metal interconnection line includes: a semiconductor substrate; a metal pattern on the substrate; a glue pattern under the metal pattern; an anti-reflection pattern on the metal pattern; and dummy patterns surrounding side walls of the metal pattern.

Abstract: A light emitting diode structure has a silicon substrate, a conductive layer, and a light emitting diode. The top surface of the silicon substrate has a cup-structure like paraboloid, and the bottom of the cup-structure has a plurality of through-holes penetrating the silicon substrate. The conductive layer fills up the through-holes and protrudes out from the through-holes. The light emitting diode is disposed on the top of the conductive layer protruding out from the through-holes and is located at the focus of the cup-structure.

Abstract: A semiconductor device which includes a laterally extending stack of laterally adjacent conductive semiconductor regions formed over a support surface of a substrate, and a method for fabricating the device.

Abstract: In accordance with a specific embodiment, a method of processing a semiconductor substrate is disclosed whereby the substrate is thinned, and the dice formed on the substrate are singulated by a common process. Trench regions are formed on a backside of the substrate. An isotropic etch of the backside results in a thinning of the substrate while maintaining the depth of the trenches, thereby facilitating singulation of the die.

Abstract: A method of forming and a structure of an electronic device. The method including: forming a trench in a single-crystal semiconductor substrate; forming a dopant diffusion barrier layer on sidewalls and a bottom of the trench; and epitaxially growing a single-crystal semiconductor layer in the trench, the single-crystal semiconductor layer filling the trench, the dopant diffusion barrier layer a barrier to diffusion of semiconductor dopants. Also a power transistor formed by the same method.

Abstract: A growth plane of substrate 1 is processed to have a concavo-convex surface. The bottom of the concave part may be masked. When a crystal is grown by vapor phase growth using this substrate, an ingredient gas does not sufficiently reach the inside of a concave part 12, and therefore, a crystal growth occurs only from an upper part of a convex part 11. As shown in FIG. 1(b), therefore, a crystal unit 20 occurs when the crystal growth is started, and as the crystal growth proceeds, films grown in the lateral direction from the upper part of the convex part 11 as a starting point are connected to cover the concavo-convex surface of the substrate 1, leaving a cavity 13 in the concave part, as shown in FIG. 1(c), thereby giving a crystal layer 2, whereby the semiconductor base of the present invention is obtained. In this case, the part grown in the lateral direction, or the upper part of the concave part 12 has a low dislocation region and the crystal layer prepared has high quality.

Abstract: An electronic device including: a pair of electrodes; an organic semiconductor layer; and an organic film formed of organic compounds including nonconjugated organic compounds coupled to at least one of surfaces of the pair of electrodes.