Abstract: A light emitting device includes a silicon substrate (1), a silicon nitride film (2) formed on the surface of the silicon substrate (1), at least an n-type layer (3), (4) and a p-type layer (6), (7) which are formed on the silicon nitride film (2) and also which are made of a ZnO based compound semiconductor, and a semiconductor layer lamination (11) in which layers are laminated to form a light emitting layer. Preferably this silicon nitride film (2) is formed by thermal treatment conducted in an atmosphere containing nitrogen such as an ammonium gas. Also, in another embodiment, a light emitting device is formed by growing a ZnO based compound semiconductor layer on a main face of a sapphire substrate, the main face being perpendicular to the C-face thereof. As a result, it is possible to obtain a device using a ZnO based compound with high properties such as an LED very excellent in crystallinity and having a high light emitting efficiency.

Abstract: A method of manufacturing a semiconductor chip package includes mechanically and electrically connecting a semiconductor chip to a top surface of a main substrate, securely attaching the semiconductor chip to a recessed cavity on a bottom surface of an interconnection substrate, mechanically and electrically connecting the main substrate to the interconnection substrate, and cutting the main substrate to form a central substrate and a peripheral substrate wherein the semiconductor chip is disposed on the central substrate. The cutting step is conducted either (i) by forming a plurality of slots such that the central substrate and the peripheral substrate are partially conned to each other or (ii) by completely separating the central substrate and the peripheral substrate.

Abstract: A semiconductor device comprises a field-effect transistor arranged in a semiconductor substrate, which transistor has a gate electrode, source/drain impurity diffusion regions, and carbon layers surrounding the source/drain impurity diffusion regions. Each of the carbon layers is provided at an associated of the source/drain impurity diffusion regions and positioned so as to be offset from the front edge of a source/drain extension in direction away from the gate electrode and to surround as profile the associated source/drain impurity diffusion region.

Abstract: A transistor includes a semiconductor substrate that has a first surface of a {100} crystal plane, a second surface of the {100} crystal plane having a height lower than that of the first surface, and a third surface of a {111} crystal plane connecting the first surface to the second surface. First heavily doped impurity regions are formed under the second surface. A gate structure is formed on the first surface. An epitaxial layer is formed on the second surface and the third surface. Second heavily doped impurity regions are formed at both sides of the gate structure. The second heavily doped impurity regions have side faces of the {111} crystal plane so that a short channel effect generated between the impurity regions may be prevented.

Abstract: Programmable resistive RAM cells have a resistance that depends on the size of the programmable resistive elements. Manufacturing methods and integrated circuits for programmable resistive elements with uniform resistance are disclosed that have a cross-section of reduced size compared to the cross-section of the interlayer contacts.

Abstract: A process for fabricating a leadless plastic chip carrier. A first surface of a leadframe strip is selectively etched to thereby provide depressions in the first surface and metal contacts are deposited in the depressions in the first surface of the leadframe strip. At least one layer of metal is selectively plated on at least the metal contacts to provide a plurality of selectively plated contact pads and a die attach pad. A semiconductor die is mounted on the first surface of the die attach pad and the semiconductor die is wire bonded to ones of the contact pads. The wire bonds and the semiconductor die are encapsulated in a molding material such that the molding material covers the die attach pad and the contact pads. The leadframe strip is etched away thereby exposing the metal contacts in the form of an array and the leadless plastic chip carrier is singulated from other leadless plastic chip carriers.

Abstract: The invention provides a method for increasing the usable surface area of a semiconductor wafer having a substantially planar surface and a thickness dimension at right angles to said substantially planar surface, the method including the steps of selecting a strip thickness for division of the wafer into a plurality of strips, selecting a technique for cutting the wafer into the strips at an angle to the substantially planar surface, in which the combined strip thickness and width of wafer removed by the cutting is less than the thickness of the wafer, cutting the wafer into strips using the selected technique and separating the strips from each other.

Abstract: A method of forming a tungsten film on a surface of an object to be processed in a vessel capable of being vacuumized, includes the steps of forming a tungsten film by alternately repeating a reduction gas supplying process for supplying a reduction gas and a tungsten gas supplying process for supplying a tungsten-containing gas with an intervening purge process therebetween for supplying an inert gas while vacuumizing the vessel. A reduction gas supplying period of a reduction gas supplying process among the repeated reduction gas supplying processes is set to be longer than that of the remaining reduction gas supplying processes.

Abstract: The invention provides a laminating system in which one of second and third substrates for sealing a thin film integrated circuit is supplied to a first substrate having the plurality of thin film integrated circuit while being extruded in a heated and melted state, and further rollers are used for supplying the other substrate, receiving IC chips, separating, and sealing. Processes of separating the thin film integrated circuits provided over the first substrate, sealing the separated thin film integrated circuits, and receiving the sealed thin film integrated circuits can be continuously carried out by rotating the rollers. Thus, the production efficiency can be extremely improved.

Abstract: Improved methods for depositing low resistivity tungsten films are provided. The methods involve depositing a tungsten nucleation layer on a substrate and then depositing a tungsten bulk layer over the tungsten nucleation layer to form the tungsten film. The methods provide precise control of the nucleation layer thickness and improved step coverage. According to various embodiments, the methods involve controlling thickness and/or improving step coverage by exposing the substrate to pulse nucleation layer (PNL) cycles at low temperature. Also in some embodiments, the methods may improve resistivity by using a high temperature PNL cycle of a boron-containing species and a tungsten-containing precursor to finish forming the tungsten nucleation layer.

Abstract: In one embodiment, a reflowable layer 51 is deposited over a semiconductor device 10 and reflowed in an environment having a pressure approximately equal to that of atmosphere to form a seal layer 52. The seal layer 52 seals all openings 43 in the underlying layer of the semiconductor device 10. Since the reflow is performed at approximately atmospheric pressure a gap 50 which was coupled to the opening 43 is sealed at approximately atmospheric pressure, which is desirable for the semiconductor device 10 to avoid oscillation. The seal layer 52 is also desirable because it prevents particles from entering the gap 50. In another embodiment, the seal layer 52 is deposited in an environment having a pressure approximately equal to atmospheric pressure to seal the hole 43 without a reflow being performed.

Abstract: The present invention pertains to methods for removing unwanted material from a semiconductor wafer during wafer manufacturing. More specifically, the invention pertains to stripping photo-resist material and removing etch-related residues from a semiconductor wafer. Methods involve implementing a plasma operation using hydrogen and a weak oxidizing agent, such as carbon dioxide. The invention is effective at stripping photo-resist and removing residues from low-k dielectric material used in Damascene devices.

Abstract: A method of patterning a thin film. The method includes forming a mask on a film to be patterned. The film is then etched in alignment with the mask to form a patterned film having a pair of laterally opposite sidewalls. A protective layer is formed on the pair of laterally opposite sidewalls. Next, the mask is removed from above the patterned film. After removing the mask from the patterned film, the protective layer is removed from the sidewalls.

Abstract: Methods of forming low-k dielectric layers for use in the manufacture of semiconductor devices and fabricating semiconductor structures using the low-k dielectric material. The low-k dielectric material comprises carbon nanostructures, like carbon nanotubes or carbon buckyballs, that are characterized by an insulating electronic state. The carbon nanostructures may be converted to the insulating electronic state either before or after a layer containing the carbon nanostructures is formed on a substrate. One approach for converting the carbon nanostructures to the insulating electronic state is fluorination.

Abstract: A method for making a semiconductor device is provided, comprising (a) providing a semiconductor structure comprising a first gate electrode (210); (b) forming a first set of organic spacers (213) adjacent to said first electrode; (c) depositing a first photo mask (215) over the structure; and (d) simultaneously removing the first set of organic spacers and the first photo mask.

Abstract: A fabrication method of a semiconductor device is disclosed by which damage to another film or exfoliation of a film is prevented and an insulating film having a dielectric constant of 2.5 or less can be formed while a film strength is maintained without deteriorating a wiring line characteristic. According to an embodiment, an insulating film is formed on a substrate by a plasma process, which uses film-forming gas having a ring structure of Si—O bonds, such that it maintains the ring structure of the Si—O bonds. According to another embodiment, an insulating film is formed on a substrate by a plasma process, which uses film-forming gas which contains silane-containing gas and oxygen gas or film-forming gas which contains Si—O bond-containing gas, such that it has a ring structure of the Si—O bonds.

Abstract: A method for producing a compound semiconductor wafer used for production of HBT by vapor growth of a sub-collector layer, a collector layer, a base layer and an emitter layer in this turn on a compound semiconductor substrate using MOCVD method wherein the base layer is grown as a p-type compound semiconductor thin film layer containing at least one of Ga, Al and In as a Group III element and As as a Group V element under such growth conditions that the growth rate gives a growth determined by a Group V gas flow rate-feed.

Abstract: An organic light emitting diode display may have a power supply line that is coplanar with a first pixel electrode of an organic light emitting element. The power supply line, first source and drain electrodes of a first thin film transistor (TFT), second source and drain electrodes of a second TFT, a data line, and an upper electrode of a storage capacitor constitute source/drain wire lines. In addition to the power supply line, any one(s) of or all of the source/drain wire lines may be coplanar with the first pixel electrode.

Abstract: Copper diffusion barrier films having low dielectric constants are suitable for a variety of copper/inter-metal dielectric integration schemes. Copper diffusion barrier films in accordance with the invention are composed of one or more layers of silicon carbide, at least one of the silicon carbide layers having a composition of at least 40% carbon (C), for example, between about 45 and 60% carbon (C). The films' high carbon-content layer will have a composition wherein the ratio of C to Si is greater than 2:1; or >3:1; or >4:1; or >5.1. The high carbon-content copper diffusion barrier films have a reduced effective k relative to conventional barrier materials.

Abstract: In one example, a method of epitaxially forming a silicon-containing material on a substrate surface is presented which includes positioning a substrate into a process chamber. The substrate has a monocrystalline surface and at least a second surface, such as an amorphous surface and/or a polycrystalline surface. The substrate is exposed to a deposition gas to deposit an epitaxial layer on the monocrystalline surface and a polycrystalline layer on the second surface. The deposition gas preferably contains a silicon source and at least a second elemental source, such as a germanium source, a carbon source and/or combinations thereof. Thereafter, the method further provides exposing the substrate to an etchant gas to etch the polycrystalline layer and the epitaxial layer in a manner such that the polycrystalline layer is etched at a faster rate than the epitaxial layer.