Patents Examined by Midys Rojas
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Patent number: 10776203Abstract: A data storage service stores a dataset on a set of storage nodes in accordance with a first encoding. A set of shards constituting quorum, and one or more additional shards, are stored on the storage nodes. The data storage system determines to store the dataset according to a second encoding, in which the second encoding has fewer total shards. The data storage system reconfigures the storage of the dataset in accordance with the second encoding, such that the reconfigured storage comprises subsets of shards from the first encoding that were not re-encoded in forming the second encoding.Type: GrantFiled: June 27, 2018Date of Patent: September 15, 2020Assignee: Amazon Technologies, Inc.Inventors: Seth William Markle, Bryan James Donlan, Paul David Franklin, Colin Laird Lazier
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Patent number: 10776050Abstract: Systems and methods are provided that may be implemented to prevent unexpected and/or uncontrollable system reboots that occur due to write filter overlay and/or RAM disk depletion within system memory of an information handling system by monitoring time-based write filter memory overlay and/or RAM disk usage. This information may be used to predict when the write filter memory overlay and/or RAM disk will fill up with data, and/or to take actions to prevent write filter memory overlay and/or RAM disk usage from reaching a threshold percentage or fractional utilization value that will trigger a system reboot. Those applications and/or data files that are primarily responsible for filling the memory of a write filter overlay may also be identified and stopped or restarted to prevent automatic system reboot due to write filter memory overlay usage.Type: GrantFiled: February 8, 2019Date of Patent: September 15, 2020Assignee: Dell Products L.P.Inventors: Sumit K. Popli, Suruchi Dubey, Ryan G. Mason
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Patent number: 10768850Abstract: Generally described, one or more aspects of the present application correspond to a highly distributed replica of a volume stored in a networked computing environment. First and second replicas of the volume can be synchronously replicated, and some implementations of the tertiary replica can be asynchronously replicated. The highly distributed nature of the tertiary replica supports parallel data transfer of the data of the volume, resulting in faster creation of backups and new copies of the volume.Type: GrantFiled: April 30, 2018Date of Patent: September 8, 2020Assignee: Amazon Technologies, Inc.Inventors: Kiran-Kumar Muniswamy-Reddy, Christopher Magee Greenwood, Colin Williams, Wells Lin, Danny Wei, Igor A. Kostic
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Patent number: 10754576Abstract: A performance evaluation apparatus and a performance evaluation method are provided. The performance evaluation method includes: detecting multiple access commands of a memory controller for page miss so as to identify at least one page-missed command from the access commands; calculating an interval between the at least one page-missed command and a last conflict command to serve as a conflict command interval, wherein the last conflict command conflicts with the at least one page-missed command; and evaluating performance of the memory controller according to the conflict command interval.Type: GrantFiled: March 23, 2018Date of Patent: August 25, 2020Assignee: Shanghai Zhaoxin Semiconductor Co., Ltd.Inventors: Zufa Yu, Jie Jin
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Patent number: 10740003Abstract: A computer-implemented method includes receiving, at a memory controller, a new transaction request referencing a new transaction to be executed on a memory. The memory includes two or more memory groups embodying two or more memory technologies, and the memory controller includes two or more group request queues with a respective group request queue corresponding to each memory group of the two or more memory groups. A memory group is selected, by the memory controller, from among the two or more memory groups. The transaction request is placed, by the memory controller, on the respective group request queue corresponding to the selected memory group. The new transaction is executed on the selected memory group. A new response to the new transaction is received, by the memory controller, from the selected memory group. The new response is returned.Type: GrantFiled: March 23, 2018Date of Patent: August 11, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Philip G. Emma, Michael B. Healy, Tejas Karkhanis
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Patent number: 10725697Abstract: A round robin system with interleaved weighted and priority arbiters to serve on-demand bandwidth of a storage system are provided. In one embodiment, a host assigns a priority and weight to each of a plurality of memory commands. The memory commands are sent to the storage system in a priority round-robin manner, in which memory commands assigned to a relatively-higher priority level are sent to the storage system before memory commands assigned to a relatively-lower priority level. Further, memory commands assigned to a given priority level are sent to the storage system in a weighted round-robin manner in accordance with their assigned weight. Other embodiments are provided.Type: GrantFiled: May 9, 2018Date of Patent: July 28, 2020Assignee: Western Digital Technologies, Inc.Inventors: Sivaraj Velusamy, Chandra Sekhara Rao Lakkimsetty, Eyal Hakoun, Manikandan Sakthivel, Amar Nath Alamuri, Arpit Mishra, Himanshu Kumar Patel
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Patent number: 10719438Abstract: A memory controller is for controlling operations of a nonvolatile memory including a first memory block group for storing a first type of data and a second memory block group for storing a second type of data. The memory controller includes a garbage collection management unit configured to execute a garbage collection policy in which a first garbage collection criteria is applied to the first memory block group, and a second garbage collection criteria is applied to the second memory block group, where first garbage collection criteria is different than the second garbage collection criteria.Type: GrantFiled: June 28, 2016Date of Patent: July 21, 2020Assignee: Samsung Electronics Co., Ltd.Inventor: In-Hwan Choi
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Patent number: 10713163Abstract: A method of managing a solid state drive (SSD), comprising: storing a first set of data in a first plurality of non-volatile memory dies, the first plurality of non-volatile memory dies communicatively arranged in one or more first communication channels; storing a second set of data in a second plurality of non-volatile memory dies, the second plurality of non-volatile memory dies communicatively arranged in one or more second communication channels; generating a first set of system data corresponding only to the first set of data; generating a second set of system data corresponding only to the second set of data; and managing the first set of system data corresponding to the first set of data independently of the second set of system data corresponding to the second set of data, wherein the one or more first communication channel and the one or more second communication channel are communicatively coupled to one or more channel controllers, the one or more channel controls are communicatively coupled to aType: GrantFiled: September 11, 2018Date of Patent: July 14, 2020Assignee: Toshiba Memory CorporationInventors: Girish Desai, Narasimhulu DharaniKumar Kotte
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Patent number: 10712974Abstract: A virtual disk processing method and apparatus belong to the field of storage technologies, where the method includes receiving delete information from a client system of a first virtual machine, determining, according to the delete information, at least one data cluster in a first virtual disk corresponding to a designated file, where the first virtual disk is a virtual disk corresponding to the first virtual machine, setting the at least one data cluster to be available, determining, according to a storage mapping table, a target physical disk block corresponding to the at least one data cluster, where a correspondence between a data cluster in the first virtual disk and a physical disk block is recorded in the storage mapping table, and setting the target physical disk block to be available.Type: GrantFiled: November 14, 2017Date of Patent: July 14, 2020Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Jianqing Liu, Xingshui Dong, Lin Zhang
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Patent number: 10712948Abstract: A method for mapping storage system resources is provided. The method includes receiving identification information from a plurality of storage system resources of at least one data center, and receiving performance information from the plurality of storage system resources. The method includes generating a physical or virtual mapping, in one or more dimensions, of locations of each of the plurality of storage system resources, relative to the at least one data center, and representing the identification information and the performance information in the physical or virtual mapping of each of the plurality of storage system resources.Type: GrantFiled: October 28, 2016Date of Patent: July 14, 2020Assignee: Pure Storage, Inc.Inventor: John D. Davis
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Patent number: 10705962Abstract: Embodiment of this disclosure provides a mechanism to use a portion of an inactive processing element's private cache as an extended last-level cache storage space to adaptively adjust the size of shared cache. In one embodiment, a processing device is provided. The processing device comprising a cache controller is to identify a cache line to evict from a shared cache. An inactive processing core is selected by the cache controller from a plurality of processing cores associated with the shared cache. Then, a private cache of the inactive processing core is notified of an identifier of a cache line associated with the shared cache. Thereupon, the cache line is evicted from the shared cache to install in the private cache.Type: GrantFiled: December 21, 2017Date of Patent: July 7, 2020Assignee: Intel CorporationInventors: Carl J. Beckmann, Robert G. Blankenship, Chyi-Chang Miao, Chitra Natarajan, Anthony-Trung D. Nguyen
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Patent number: 10698828Abstract: A computer-implemented method, according to one embodiment, includes: sending one or more instructions to calculate a combined size of fragments included in the fragmented files, sending one or more instructions to designate a portion of cache which corresponds to at least the combined size of the fragments, sending one or more instructions to send a copy of each non-fragmented file from a first drive directly to a second drive in which the second sequential storage medium is loaded, sending one or more instructions to use the designated portion of the cache to accumulate the fragments included in the fragmented files, and sending one or more instructions to send a copy of each of the fragments corresponding to a given fragmented file from the cache to the second drive in response to determining that all of the fragments corresponding to the given fragmented file have been accumulated in the cache.Type: GrantFiled: April 10, 2018Date of Patent: June 30, 2020Assignee: International Business Machines CorporationInventors: Noriko Yamamoto, Tsuyoshi Miyamura, Tohru Hasegawa, Hiroshi Itagaki, Shinsuke Mitsuma, Sosuke Matsui
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Patent number: 10664194Abstract: A memory device includes a processing device configured to iteratively determine a set of read results based on reading a subset of memory cells according to a set of read levels determine an update direction based on the set of read results, wherein the update direction corresponds to one of the set of read levels; determine whether a change condition is met; generate an updated read level for the set of read levels based on applying an adjustment step to one of the read levels in the set of read levels along the update direction, wherein the adjustment step is: a first step size in response to the change condition not being met, and a second step size in response to the change condition being met.Type: GrantFiled: May 16, 2018Date of Patent: May 26, 2020Assignee: Micron Technology, Inc.Inventors: Michael Sheperek, Larry J. Koudele, Steve Kientz
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Patent number: 10664594Abstract: Methods for accelerated code injection detection using operating system controlled memory attributes are performed by systems and apparatuses. The methods optimize search operations for memory segments in system and virtual memories by searching for segment attributes. A set of memory segments is determined wherein each memory segment in the set includes specific attributes. The memory segments in the set are ranked for a threat level based on segment attribute. The threat level is used to determine subsequent actions including providing indications of the memory segments in the set and initiating execution of an anti-malware application. Relevant segment attributes used for the segment search can be dynamically updated in an attribute list. Segment attributes of a segment can be determined by accessing a memory manager of an operating system via an API.Type: GrantFiled: June 30, 2017Date of Patent: May 26, 2020Assignee: Microsoft Technology Licensing, LLCInventors: Abhishek Kumar Singh, Aditya Joshi, Freddie L. Aaron, Peter A. Loveless, Tino Morenz
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Patent number: 10664167Abstract: A data transmitting method, a memory storage device and a memory control circuit unit are provided. The method is used for a data transmitting operation between the memory storage device and a host system. The host system is recorded with a plurality of submission queues, and the method includes: obtaining at least one first command in a first submission queue from the host system and determining whether a first data quantity of the at least one first command matches a first predetermined condition; obtaining at least one second command in a second submission queue from the host system if the first data quantity matches the first predetermined condition; and sequentially performing a data accessing operation corresponding to the at least one first command and the at least one second command on a rewritable non-volatile memory module in the memory storage device.Type: GrantFiled: March 8, 2017Date of Patent: May 26, 2020Assignee: PHISON ELECTRONICS CORP.Inventor: Ming-Hui Tseng
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Patent number: 10657067Abstract: A memory management unit circuit includes a plurality of ports with a plurality of translation buffer units. Each translation buffer unit includes a translation lookaside buffer circuit and a translation logic circuit configured to perform virtual to physical address translation using the translation lookaside buffer circuit. A translation lookaside buffer circuit prefetch logic circuit monitors virtual memory access requests received at the corresponding port of the memory management unit circuit and detects satisfaction of at least one trigger condition. In response, address translation prefetch requests are generated. A control circuit transmits the address translation prefetch requests to a physical memory circuit and receives address translation data for populating the translation lookaside buffer.Type: GrantFiled: September 12, 2016Date of Patent: May 19, 2020Assignee: Xilinx, Inc.Inventors: Sarosh I. Azad, Bhaarath Kumar
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Patent number: 10649778Abstract: A method of optimized congruence class matching for concurrent memory translation requests to avoid memory access conflicts with respect to a virtual memory managed by a processor is provided. The method includes initiating a first table walk by a first memory access of the concurrent memory translation requests and pending a subsequent table walk initiated by a subsequent memory access of the concurrent memory translation requests. Then, the method determines whether the subsequent table walk will cause a memory access conflict with the first table walk based on the optimized congruence class matching. The subsequent memory access is rejected when the subsequent table walk will cause the memory access conflict with the first table walk.Type: GrantFiled: December 4, 2018Date of Patent: May 12, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David Campbell, Dwain A. Hicks, Christian Jacobi, Kerey M. Tassin
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Patent number: 10649657Abstract: Apparatuses, systems, and methods are disclosed for log-based storage for different data types in non-volatile memory. An apparatus may include a non-volatile memory element and a controller. A non-volatile memory element may include a first portion of memory, an intermediate storage, and a second portion of memory. A controller may be configured to receive a plurality of data units. A controller may be configured to classify units of data using a first data type and a second data type. A controller may be configured to store a first unit of data having a first data type in a first portion of memory and a second unit of data having a second data type in intermediate storage. Further, a controller may relocate a second unit of data to a second portion of memory.Type: GrantFiled: March 22, 2018Date of Patent: May 12, 2020Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Mikhael Zaidman, Eyal Ittah, Rotem Sela, Amir Shaharabany
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Patent number: 10642530Abstract: Computer systems and methods for scheduling garbage collection in a distributed environment that includes multiple partitions that reference various data blocks that store data objects. A global occupancy aggregator may access occupancy information for each of the partitions from an occupancy index of each of the partitions. This occupancy information specifies a portion of storage resources occupied by those data blocks referenced by each of the partitions. The global occupancy aggregator may aggregate the accessed occupancy information to generate a global occupancy index that combines the occupancy information of the partitions. The global occupancy aggregator may generate a global schedule for garbage collection for the partitions based on the global occupancy index. The global schedule specifies which of the data blocks included in the global occupancy index are to be subjected to garbage collection.Type: GrantFiled: February 20, 2019Date of Patent: May 5, 2020Assignee: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: Shane Kumar Mainali, Rushi Srinivas Surla
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Patent number: 10642520Abstract: In a distributed data processing system with a set of multiple nodes, a first data shuffle memory pool is maintained at a data shuffle writer node, and a second data shuffle memory pool is maintained at a data shuffle reader node. The data shuffle writer node and the data shuffle reader node are part of the set of multiple nodes of the distributed data processing system. In-memory compression is performed on at least a portion of a data set from the first data shuffle memory pool. At least a portion of the compressed data is transmitted from the first data shuffle memory pool to the second data shuffle memory pool in a peer-to-peer manner. Each of the first data shuffle memory pool and the second data shuffle memory pool may include a hybrid memory configuration.Type: GrantFiled: April 18, 2017Date of Patent: May 5, 2020Assignee: EMC IP Holding Company LLCInventors: Junping Zhao, Kenneth J. Taylor, Randall Shain, Kun Wang