Abstract: In a method of tiering data in a computing environment, data service status information is obtained at a first storage environment regarding a data service operation performed on one or more data sets that qualify for storage at a second storage environment based on a given policy, and, based on the obtained data service status information, a determination is made to store the one or more data sets at the second storage environment without performing a reverse operation of the data service operation on the one or more data sets.

Abstract: Handling fingerprint collisions in a storage system that includes one or more storage devices, including: determining whether a fingerprint associated with a first data segment matches a fingerprint associated with a data segment stored within the storage system; responsive to determining that the fingerprint associated with the first data segment matches the fingerprint associated with the data segment stored within the storage system, determining whether the first data segment matches the data segment stored within the storage system; and responsive to determining that the first data segment does not match the data segment stored within the storage system, resolving a fingerprint collision between the first data segment and the data segment stored within the storage system.

Abstract: A method and an apparatus for controlling an access to a disk array. The method comprises: receiving a command for writing to a first stripe of the plurality of stripes; and determining a first parity position for the first stripe by searching a mapping table, the mapping table recording a first mapping between the first stripe and the first parity position allocated in the first stripe, the first parity position being arranged in a first disk of the plurality of disks having a minimum wearing level. The embodiments of the present disclosure further disclose a corresponding apparatus. The embodiments of the present disclosure provides a solution for controlling an access to a disk array, which can achieve a dynamic balance of wearing levels among all of the disks in a RAID, thereby making it possible to control or manage a failure order of the disks.

Abstract: Methods and devices that receive commands at a command interface and uses control circuitry configured to implement the command. A routing pipeline is configured to translate and route the command from the command interface to the control circuitry. The routing pipeline includes clock circuitry. The clock circuitry includes a clock delay line and multiple cloned delay lines derived from the clock delay line. Each of the cloned delay lines are dedicated to a command type of multiple command types. The routing pipeline also includes delay circuitry configured to utilize the cloned delay lines to shift a data pin signal of the semiconductor device or shift a data strobe pin signal of the semiconductor device.

Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.

Abstract: In one embodiment, a storage drive is configured to receive a selective flush command which causes the storage drive to selectively flush write data which has been identified in connection with the selective flush command, from volatile buffer memory to a nonvolatile storage memory. Conversely, write data stored in the volatile buffer memory which is not identified in connection with the selective flush command, may remain unaffected by the selective flush command, and thus may remain stored in the volatile buffer memory without being flushed to the nonvolatile storage memory as a result of the selective flush command. Other aspects are described herein.

Abstract: In a state where one of physical storage regions is allocated to each of unit regions included in a logical storage region, an apparatus identifies, from among the unit regions, first unit regions which have been allocated from physical storage regions whose allocations to the first unit regions are to be changed. The apparatus sequentially selects, from among the first unit regions, a second unit region as a candidate for data migration, and instructs data migration of the second unit region between the physical storage regions. The apparatus determines whether data migration of any one of the unit regions whose data has been instructed to be migrated is being executed on each of multiple divided regions obtained by dividing a physical storage region to which data of the second unit region is to be migrated, and instructs data migration of the second unit region based on the determination.

Abstract: A computer-implemented method according to one embodiment includes creating, at a block storage system separate from a host system, a structural representation of image layer data utilized at the host system, mapping the structural representation created at the block storage system to the image layer data utilized at the host system, and performing one or more operations on the image layer data, utilizing the structural representation created at the block storage system.

Abstract: An information processing apparatus includes a processor, a plurality of memories, and a memory control circuitry coupled to the processor and the plurality of memories. The memory control circuitry controls access to the plurality of memories. The memory control circuitry includes a plurality of memory control circuits corresponding respectively to the plurality of memories, and a request distribution circuit that outputs the memory access request and a setting change request from the processor to one of the plurality of memory control circuits. Each of the plurality of memory control circuits includes an address translation control circuit that replaces bits of an address included in the memory access request based on allocation of bits changed based on the setting change request, and an access control circuit.

Abstract: A block storage service can ensure volumes are placed in a same region as an attached virtual machine instance for performance and durability guarantees. A region can reference multiple things, but one example is that a volume is within a same spine as a virtual machine in order to meet performance guarantees. Each region can have a buffer of server computers held in reserve for volumes having a type where performance guarantees are required. If performance guarantees cannot be met, a rejection is transmitted to the customer. In another embodiment, the customer can provide a list in priority order of different volume types so that if a desired volume type cannot be placed, then alternative volume types can be used.

Abstract: Managing memory access requests for a plurality of processor cores includes: storing admission control information for determining whether or not to admit a predetermined type of memory access request into a shared resource that is shared among the processor cores and includes one or more cache levels of a hierarchical cache system and at least one memory controller for accessing a main memory; determining whether or not a memory access request of the predetermined type made on behalf of a first processor core should be admitted into the shared resource based at least in part on the stored admission control information; and updating the admission control information based on a latency of a response to a particular memory access request admitted into the shared resource, where the updating depends on whether the response originated from a particular cache level included in the shared resource or from the main memory.

Abstract: Examples include methods for obtaining one or more location hints applicable to a range of logical block addresses of a received input/output (I/O) request for a storage subsystem coupled with a host system over a non-volatile memory express over fabric (NVMe-oF) interconnect. The following steps are performed for each logical block address in the I/O request. A most specific location hint of the one or more location hints that matches that logical block address is applied to identify a destination in the storage subsystem for the I/O request. When the most specific location hint is a consistent hash hint, the consistent hash hint is processed. The I/O request is forwarded to the destination and a completion status for the I/O request is returned. When a location hint log page has changed, the location hint log page is processed. When any location hint refers to NVMe-oF qualified names not included in the immediately preceding query by the discovery service, the immediately preceding query is processed again.

Abstract: In an embodiment, a processor includes a plurality of cores, with at least one core including prefetch logic. The prefetch logic comprises circuitry to: receive a prefetch request; compare the received prefetch request to a plurality of entries of a prefetch filter cache; and in response to a determination that the received prefetch request matches one of the plurality of entries of the prefetch filter cache, drop the received prefetch request. Other embodiments are described and claimed.

Abstract: A semiconductor device includes a first substrate on which an interface unit connectable to a host device is provided, a first memory module on the first substrate, and a first controller on the first substrate. The first controller includes a control unit that controls the first memory module, and a switching unit that switches an operation mode in response to a command from the host device. A first connecting portion is provided on the first substrate and is electrically connected to the first memory module and the first controller. The first controller can directly access a second memory module through the first connecting portion. Thus, for example the first controller can read data stored in the second memory module depending on operation mode.

Abstract: A method of managing objects in an archive system includes assigning a number of addresses to each of a plurality of nodes, dividing an object into a sequence of blocks, uniformly distributing the sequence of blocks across the plurality of nodes by, calculating a hash value of a unique identifier of the object to be used as an address for a first block in the sequence, storing the first block at a node to which the address is assigned, for each subsequent block in the sequence, calculating a subsequent address from a hash value of the address of an immediately previous block in the sequence and storing the subsequent block at a node to which the calculated subsequent address is assigned, iteratively calculating a hash value of the hash value of the subsequent address if the calculated subsequent address is assigned to a node where a previous block is stored, and storing the subsequent block at a node to which an address corresponding to the iteratively calculated hash value is assigned.

Abstract: A cache coherent data processing system includes at least non-overlapping first, second, and third coherency domains. A master in the first coherency domain of the cache coherent data processing system selects a scope of an initial broadcast of an interconnect operation from among a set of scopes including (1) a remote scope including both the first coherency domain and the second coherency domain, but excluding the third coherency domain that is a peer of the first coherency domain, and (2) a local scope including only the first coherency domain. The master then performs an initial broadcast of the interconnect operation within the cache coherent data processing system utilizing the selected scope, where performing the initial broadcast includes the master initiating broadcast of the interconnect operation within the first coherency domain.

Abstract: A method and a device for accessing a cache memory are provided. The method comprises: generating, by a bit prediction unit (BPU), a prediction bit corresponding to an instruction instructing to access the cache memory from a central processing unit (CPU); generating, by an instruction execution unit (IEU), a virtual address corresponding to the instruction; generating, by a load/store unit (LSU), a predicted cache index according to the prediction bit and a part of a virtual page offset of the virtual address; and reading, by the LSU, data from the cache memory by using the predicted cache index. Therefore, the maximum size of the cache memory could be increased.

Abstract: An example apparatus according to an aspect of the present disclosure includes an address scrambler circuit including a sub-wordline scrambler circuit configured to receive a first subset of bits of a row hammer hit address. The sub-wordline scrambler circuit is configured to perform a first set of logical operations on the first subset of bits to provide a second subset of bits, and to perform a second set of logical operations on the first subset of bits and the second subset of bits to provide a third subset of bits of an row hammer refresh address.

Abstract: A memory device includes a nonvolatile memory having a first block and a memory controller configured to exchange data with the nonvolatile memory. The memory controller includes a first processor to divide the first block into first and second domains, a second processor to generate a reclaim signal by determining whether to perform reclaiming on each of the first and second domains and a third processor performer which reclaims each of the first and second domains according to the reclaim signal and merges the first and second domains.

Abstract: Provided is a system and method for converting active data identified by a garbage collection operation into erasure coded fragments. In one example, the method may include identifying data blocks in use and interspersed among garbage data blocks not in use in cloud storage based on a garbage collection operation, extracting object data from the identified data blocks in use into a data container while leaving object data of the garbage data blocks not in use, and fragmenting a predetermined amount of extracted object data stored within the data container, the fragmenting comprising converting the predetermined amount of object data into a plurality of fragments including data fragments storing portions of the data and parity fragments for reconstructing the data, and writing the plurality of fragments in a distributed manner among a plurality of storage nodes.