Abstract: In general, embodiments of the technology relate to method for resolving a library path in a distributed system. The method includes receiving a path resolution request, issuing a first request to a first node server to obtain a first library name index (LNI) associated with a first portion of the library path, obtaining the first LNI, and generating, based on the first LNI, a second request to a second node server of the plurality of node servers, where the second request is associated with a second portion of the library path. The method further includes after not receiving a second response to the second request: issuing a request message to a set of node servers, receiving, from one of the node servers, a third response to the request message, and resolving the entire library path using, at least in part, the third response.

Abstract: A forwarding pipeline of a forwarding engine includes a mirror bit mask vector with one bit per supported independent mirror session. Each bit in the mirror bit mask vector can be set at any point in the forwarding pipeline when the forwarding engine determines that conditions for a corresponding mirror session are met. At the end of the forwarding pipeline, if any of the bits in the mirror bit mask vector is set, then a packet, the mirror bit mask vector and a pointer to the start of a mirror destination linked list are forwarded to the multicast replication engine. The mirror destination linked list typically defines a rule for mirroring. The multicast replication engine mirrors the packet according to the mirror destination linked list and the mirror bit mask vector.

Abstract: In an embodiment, a processor may implement an access map-pattern match (AMPM)-based prefetch circuit with features designed to improve prefetching accuracy and/or reduce power consumption. In an embodiment, the prefetch circuit may be configured to detect that pointer reads are occurring (e.g. “pointer chasing.”) The prefetch circuit may be configured to increase the frequency at which prefetch requests are generated for an access map in which pointer read activity is detected, compared to the frequency at which the prefetch requests would be generated in the pointer read activity is not generated. In an embodiment, the prefetch circuit may also detect access maps that are store-only, and may reduce the frequency of prefetches for store only access maps as compared to the frequency of load-only or load/store maps.

Abstract: Systems and methods for optimizing storage system performance are disclosed. A method includes: determining an expected lifetime of each of at least one computing instance; determining a disk data extent evaluation period for each of the at least one computing instance based on the determined expected lifetime; determining an input/output (I/O) wait time threshold for each of the at least one computing instance; determining an I/O wait time of each of the at least one computing instance using the determined disk data extent evaluation period; and in response to the determined I/O wait time of one or more of the at least one computing instance exceeding the determined I/O wait time threshold of the computing instance, moving at least one data extent associated with the one or more computing instance exceeding the determined I/O wait time threshold from hard disk drive storage to solid state drive storage.

Abstract: In general, embodiments of the invention include methods and apparatuses for securely storing computer system data. Embodiments of the invention encrypt and decrypt SATA data transparently to software layers. That makes it unnecessary to make any software modifications to the file system, device drivers, operating system, or application. Encryption key management is performed either remotely on a centralized Remote Management System or locally. Embodiments of the invention implement background disk backups using snapshots. Additional security features that are included in embodiments of the invention include virus scanning, a virtual/network drive, a RAM drive and a port selector that provides prioritized and/or background access to SATA mass storage to a secure subsystem.

Abstract: An identification of one or more memory pages that are associated with the guest operating system may be received by a hypervisor and from a guest operating system. The hypervisor may receive a request from the guest operating system to initiate a tracking operation for the one or more memory pages. The tracking operation may be initiated for the one or more memory pages in response to receiving the request from the guest operating system. Furthermore, the one or more memory pages may be freed in view of the tracking operation that has been initiated by the hypervisor.

Abstract: Techniques and computing devices for compression memory coloring are described. In one embodiment, for example, an apparatus may include at least one memory, at least on processor, and logic for compression memory coloring, at least a portion of the logic comprised in hardware coupled to the at least one memory and the at least one processor, the logic to determine whether data to be written to memory is compressible, generate a compressed data element responsive to determining data is compressible, the data element comprising a compression indicator, a color, and compressed data, and write the compressed data element to memory. Other embodiments are described and claimed.

Abstract: Implementations of the disclosure provide for size adjustable volumes for containers. A method of the disclosure includes determining, by a processing device of the PaaS system, a size used space in a storage volume with respect to a container associated with an execution of an application. The size is a summation of current usage of disk space for the storage volume by the application. This size of the used space is compared to a threshold size. The threshold size indicates a determined amount of the storage volume allocated to the container. Responsive to the size meeting the threshold size, an increase in the allocated amount of the storage volume associated with the container is regulated by the processing device.

Abstract: In one embodiment, a memory interface employs selective memory mode authorization enforcement in accordance with the present description to ensure that memory modes of operation which have not been authorized, are not permitted to proceed. In one embodiment, mode control logic receives from memory control logic of the memory interface, memory mode selection data which is compared to a mode authorization classification structure to determine if the memory mode being selected in association with a memory transaction request is authorized or otherwise permitted. Memory mode enablement logic of the mode control logic enables the requested memory mode associated with a memory transaction request if it is determined that the selected memory mode associated with the memory transaction request is authorized. Other aspects are described herein.

Abstract: Provided are a computer program product, system, and method for using an access increment number to control a duration during which tracks remain in cache. Tracks in a storage in the cache are indicated in a cache list. For each of the tracks indicated in the cache list, an access value is updated when one of the tracks is accessed in the cache. An access to a track in the cache indicated in the cache list is received. A determination is made as to whether an access increment number for the accessed track, wherein the access increment number is greater than one. The access value for the accessed track is incremented by the determined access increment number in response to the track being accessed in the cache. The access value for one of the tracks is used to determine whether to initiate to demote the track from the cache.

Abstract: Technology is described herein for operating non-volatile storage. In one aspect, a memory controller replaces an original data buffer pointer(s) to a host memory data buffer(s) with a replacement data buffer pointer(s) to a different data buffer(s) in the host memory. The original data buffer pointer(s) may be associated with a specific read command. For example, the original data buffer pointer(s) may point to data buffer(s) to which data for some range of logical addresses (which may be read from the non-volatile storage) is to be transferred by a memory controller of the non-volatile storage. The replacement data buffer pointer(s) could be associated with a different read command. However, it is not required for the replacement data buffer pointer(s) to be associated with a read command. The replacement data buffer pointer(s) may point to a region of memory that is allocated for exclusive use of the memory controller.

Abstract: A memory controller includes a memory interface that is connected to a non-volatile memory that includes a plurality of memory cells, and a control unit. The control unit controls the memory interface to perform writing of data that has a first number of bits to a first memory cell in an n-bit write mode (where n is 2 or more), and when performing reading of the data written into the first memory cell, to control the memory interface to perform reading of data in an m-bit read mode (where m is less than n), as a result of which data that has a second number of bits which is smaller than the first number of bits, is returned from the first memory cell.

Abstract: A technique includes determining that a row of memory has been activated at a threshold rate. Upon reaching the threshold rate, a refresh rate for the row of memory and an adjacent row of memory may be increased. Subsequent to the increase, the refresh rate may be returned to a default rate.

Abstract: A storage enclosure includes a plurality of hard drive sub-boards, each configured to include a plurality of hard drives. A local logic device manages each hard drive sub-board. A master logic device manages the local logic devices. The master logic device receives management commands from a host computer system coupled to the storage enclosure, and routes those commands to specific local logic devices. The local logic devices then relay the commands to specifically targeted hard drives. Thus, each hard drive within the storage enclosure can be independently controlled, allowing a single hard drive to be powered down without powering down other hard drives in the enclosure.

Abstract: A data training method of a storage device, which includes a storage controller and a nonvolatile memory device, includes transmitting a read training command to the nonvolatile memory device, receiving a first training pattern output from the nonvolatile memory device in response to the read training command, receiving a second training pattern output from the nonvolatile memory device in response to the read training command, comparing the received first training pattern and the received second training pattern with a reference pattern, and determining a read timing offset of the storage controller depending on the comparison result.

Abstract: A memory transaction-level modeling method and a memory transaction-level modeling system are provided. The memory transaction-level modeling method is used for simulating the operation of outputting at least one command to the memory. The memory includes a plurality of banks each of which corresponds with a bank status table. The memory transaction-level modeling method includes the following steps: An event is received. Whether one of the bank status tables is needed to be updated is determined. If one of the bank status tables is needed to be updated, this bank status table is recovered according to a TMP queue. A command is outputted to the memory according to a command queue. The outputted command is stored in the TMP queue. Some of the bank status tables are updated and others of the bank status tables are kept unchanged.

Abstract: A method and apparatus for identifying process use on storage array resources is provided. A first process (e.g. an IO driver such as an MPIO driver) on each host collects process information of application processes running on that host. The process/device information is forwarded to the storage array where it is added to a process correlation data structure and correlated with assigned devices of the storage array. The host name that provided the process information is also added to the process correlation data structure. A name of the application is also correlated to the process name in the process correlation data structure. The date the device was last used is periodically updated in the process correlation data structure. The process correlation data structure may then be used to identify devices that have not recently been used and to identify the host, application, and process that uses the devices.

Abstract: A processor includes a cache memory and a cache controller. The cache controller fetches first data from a first location of an information handling system, stores the first data to a first cache line of a plurality of cache lines, determines first proximity information for the first data based upon the first location, stores the first proximity information in a first proximity tag associated with the first cache line, and evicts the first cache line from the cache based upon the first proximity tag.

Abstract: A method begins by a processing module receiving a checked write slice request from a requesting entity. The method continues by determining that locally stored encoded data slices do not include the requested encoded data slice. The method continues by identifying an alternate location for the requested encoded data slice. The method continues by determining whether the alternate location is associated with storage of the encoded data slice. The method continues when the alternate location is associated with the storage of the encoded data slice, by issuing a favorable checked write slice response to a requesting entity. The method can include facilitating transfer of the requested encoded data slice from the alternate location to the storage unit for storage.

Abstract: Methods, computing systems and computer program products implement embodiments of the present invention that include receiving a request including a specified number of logical volumes, and identifying, in a storage system including multiple storage pools having storage space, respective first amounts of the storage space that are available in the multiple storage pools. Based on the specified number of logical volumes and the first amounts of the storage space, a set of volume sizes indicating second amounts of the storage space are defined, and a given volume size indicating a maximum size for the specified number of logical volumes is identified. Upon conveying the maximum size to a user, and receiving, from the user, a specified size less than or equal to the maximum size, the specified number of the volumes having the specified size can be provisioned, wherein each of the volumes is stored in a given storage pool.