Abstract: A storage apparatus includes a first memory, which is nonvolatile, a first controller that controls the first memory, a wireless antenna, a second memory, which is operable based on power supplied from the wireless antenna, and a second controller that is operable based on the power supplied from the wireless antenna, and performs communication using the wireless antenna. When performing communication with an external apparatus using the wireless antenna, the second controller performs authentication of the external apparatus, and stores in the second memory an authentication result indicating whether the authentication succeeded or failed. If the authentication result indicates that the authentication succeeded, the second controller permits reading by the external apparatus of first data from the second memory by communication using the wireless antenna or writing by the external apparatus of second data to the second memory by communication using the wireless antenna.

Abstract: One or more techniques and/or computing devices are provided for utilizing snapshots for data integrity validation and/or faster application recovery. For example, a first storage controller, hosting first storage, has a synchronous replication relationship with a second storage controller hosting second storage. A snapshot replication policy rule is defined to specify that a replication label is to be used for snapshot create requests, targeting the first storage, that are to be replicated to the second storage. A snapshot creation policy is created to issue snapshot create requests comprising the replication label. Thus a snapshot of the first storage and a replication snapshot of the second storage are created based upon a snapshot create request comprising the replication label. The snapshot and the replication snapshot may be compared for data integrity validation (e.g., determine whether the snapshots comprise the same data) and/or quickly recovering an application after a disaster.

Abstract: Apparatuses, systems, and methods are disclosed for mapping-based wear leveling for non-volatile memory. An apparatus may include one or more non-volatile memory elements, and a controller. A controller may maintain a logical-to-physical mapping for converting logical addresses to physical addresses. A logical-to-physical mapping may include a translation table that associates groups of logical addresses with groups of physical addresses, and one or more mathematical mappings. A mathematical mapping for a group of logical addresses may associate individual logical addresses within the group of logical addresses with individual physical addresses within a corresponding group of physical addresses. A controller may change at least one mathematical mapping. A controller may move data based on at least one changed mapping.

Abstract: A data storage service stores a dataset on a set of storage nodes in accordance with a first encoding. A set of shards constituting quorum, and one or more additional shards, are stored on the storage nodes. The data storage system determines to store the dataset according to a second encoding, in which the second encoding has a greater number of shards. The data storage system reconfigures the storage of the dataset in accordance with the second encoding, such that the reconfigured storage forms additional shards for the second encoding by combining portions of shards of the first encoding.

Abstract: An arithmetic processing apparatus includes, a plurality of core memory groups, each of core memory groups including a plurality of arithmetic processing circuits, cache memory circuitry, shared by the plurality of arithmetic processing circuits, including a cache memory, a cache tag that stores a state of the cache memory, a tag directory that stores data possession information by a cache memory in another core memory group, and a memory access control circuit that receives a first memory access request from the cache memory circuitry and controls access to a memory other than a cache memory included in the cache memory circuitry, and a cache memory control circuit that receives a second memory access request from the arithmetic processing circuits and a third memory access request from the another core memory group and controls access to the cache memory.

Abstract: A system, method, and computer-readable storage medium for mapping block numbers within a region to physical locations within a storage system. Block numbers are mapped within a region according to a fractal-based space-filling curve. If the region is not a 2k by 2k square, then the region is broken up into one or more 2k by 2k squares. Any remaining sub-region is centered within a 2k by 2k square, the 2k by 2k square is numbered using a fractal-based space-filling curve, and then the sub-region is renumbered by assigning numbers based on the order of the original block numbers of the sub-region.

Abstract: Updating aging information for memory backing a virtual address-backed virtual machine (VM). A virtual memory address (VA) is allocated, within a page table entry (PTE), to a process backing the VM. Based on memory access(es) by the VM to a non-mapped guest-physical memory address (GPA), the GPA is identified as being associated with the VA; an HPA is allocated for the accessed GPA; a host-physical memory address (HPA) is associated with the VA within the PTE; the GPA is associated with the HPA within a second level address translation (SLAT) structure entry; and an accessed flag is set within the SLAT entry. Aging information is updated, including identifying the SLAT entry; querying a value of the accessed flag in the SLAT entry; clearing the accessed flag in the SLAT entry without invalidating the SLAT entry; and updating aging information for the VA and/or HPA based on the queried value.

Abstract: A technique for accessing memory in an accelerated processing device coupled to stacked memory dies is provided herein. The technique includes receiving a memory access request from an execution unit and identifying whether the memory access request corresponds to memory cells of the stacked dies that are considered local to the execution unit or non-local. For local accesses, the access is made “directly”, that is, without using a bus. A control die coordinates operations for such local accesses, activating particular through-silicon-vias associated with the memory cells that include the data for the access. Non-local accesses are made via a distributed cache fabric and an interconnect bus in the control die. Various other features and details are provided below.

Abstract: A memory system includes a memory array having a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: select a garbage collection (GC) source block storing valid data, calculate a valid data measure for the GC source block for representing an amount of the valid data within the GC source block, and designate a storage mode for an available memory block based on the valid data measure, wherein the storage mode is for controlling a number of bits stored per each of the memory cells for subsequent or upcoming data writes.

Abstract: Techniques described herein relate to systems and methods of data storage, and more particularly to providing layering of file system functionality on an object interface. In certain embodiments, file system functionality may be layered on cloud object interfaces to provide cloud-based storage while allowing for functionality expected from a legacy applications. For instance, POSIX interfaces and semantics may be layered on cloud-based storage, while providing access to data in a manner consistent with file-based access with data organization in name hierarchies. Various embodiments also may provide for memory mapping of data so that memory map changes are reflected in persistent storage while ensuring consistency between memory map changes and writes. For example, by transforming a ZFS file system disk-based storage into ZFS cloud-based storage, the ZFS file system gains the elastic nature of cloud storage.

Abstract: Techniques are provided for asynchronous semi-inline deduplication. A multi-tiered storage arrangement comprises a first storage tier, a second storage tier, etc. An in-memory change log of data recently written to the first storage tier is evaluate to identify a fingerprint of a data block recently written to the first storage tier. A donor data store, comprising fingerprints of data blocks already stored within the first storage tier, is queried using the fingerprint. If the fingerprint is found, then deduplication is performed for the data block to create deduplicated data based upon a potential donor data block within the first storage tier. The deduplicated data is moved from the first storage tier to the second storage tier, such as in response to a determination that the deduplicated data has not been recently accessed. The deduplication is performed before cold data is moved from first storage tier to second storage tier.

Abstract: A programmable data pattern for repeated writes to memory can enable efficient writing of a data pattern to multiple memory locations without transmitting the data pattern for each write. In one embodiment, a memory device includes input/output (I/O) circuitry to receive a command, a register to store a value to indicate a source of a data pattern to write in response to receipt of the command, and access circuitry to, in response to receipt of the command, write the data pattern to memory based on the source indicated by the value in the register.

Abstract: Decompressing sliding window compressed data requires reference to previously decompressed character sequences. Previously decompressed data is stored in a history buffer to satisfy these ‘back references.’ As each decompressed/decoded character is emitted, it is stored in this history buffer. Thus, for each decompressed character that is emitted, the history buffer may need to be accessed at least twice—once to retrieve the backreference, and once to store the emitted character. A pipeline architecture is disclosed that stores decompressed characters in a write queue that coalesces eight or more emitted characters before they are stored in the history buffer memory. This reduces collisions between accessing the history buffer memory to retrieve the backreferences and the storing of the emitted character. This also allows the use of a single-ported memory which is less expensive than a multi-ported memory.

Abstract: Disclosed is a method, apparatus, and/or computer program product for reducing latency in a processor with regard to the execution of noncacheable operations that includes receiving noncacheable operations from one or both of the level 2 cache and a level 3 cache, sending the noncacheable operations to a noncacheable unit (NCU) associated with a core of the processor, executing the noncacheable operations by the NCU, and sending results of the executed noncacheable operations to a host bridge for output to an input/out device. The noncacheable operations bypass the core of the processor.

Abstract: A storage array in one embodiment is configured to communicate over one or more networks with a plurality of host devices. The storage array is further configured to detect process tags assigned to respective input-output operations by a given one of the host devices, the process tags being of at least first and second distinct types so as to distinguish at least respective first and second distinct processes generating corresponding ones of the input-output operations on the given host device. Responsive to a particular one of the detected process tags being of the first type, the storage array provides a first level of priority for processing of the corresponding input-output operation, and responsive to a particular one of the detected process tags being of the second type, the storage array provides a second level of priority different than the first level of priority for processing of the corresponding input-output operation.

Abstract: An information handling system may implement a method for controlling cache flush size by limiting the amount of modified cached data in a data cache at any given time. The method may include keeping a count of the number of modified cache lines (or modified cache lines targeted to persistent memory) in the cache, determining that a threshold value for modified cache lines is exceeded and, in response, flushing some or all modified cache lines to persistent memory. The threshold value may represent a maximum number or percentage of modified cache lines. The cache controller may include a field for each cache line indicating whether it targets persistent memory. Limiting the amount of modified cached data at any given time may reduce the number of cache lines to be flushed in response to a power loss event to a number that can be flushed using the available hold-up energy.

Abstract: A data operation method and an electronic device are provided. The method includes assigning a reserved area of a memory of an electronic device, which receives power associated with maintaining a data write state when the supply of a main power is blocked to a file system of a RAMDisk associated with processing a data input/output (I/O) and controlling file processing of the file system of the RAMDisk.

Abstract: Reading and copying data as file data in a persistent memory storage device. A method may be practiced in a virtual machine environment. The virtual machine environment includes a persistent memory storage device. The persistent memory storage device has the ability to appear as a memory device having available memory to a virtual machine on a host and as a file to the host. The method includes acts for copying data stored in the persistent memory storage device for a first virtual machine. The method includes the host reading data from the persistent memory storage device as file data. The method further includes the host writing the data from the persistent memory storage device as file data.

Abstract: A thread on a processor core executes one or more instructions to write file data for a file into a persistent memory save area. The instructions to write the file data have the effect of storing the file data for the file in the cache associated with the processor core. The thread running on the processor core flushes the file data from the cache to the persistent memory save area while retaining the file data in the cache. The thread running on the processor core copies the file data from the cache for the processor core into a persistent copy of the file that is stored in persistent memory.

Abstract: For accessing files from block-level backups of a virtual disk, an apparatus is disclosed. The apparatus includes a changed block module that obtains a list of changed blocks between a previous and a current backup of a virtual disk. The apparatus includes a mapping module that maps logical clusters of the virtual disk to the changed blocks and identifies files corresponding to the logical clusters. The apparatus further includes a changed file module that designates the files corresponding to the logical clusters as changed files, unless current attributes of the files for the current backup match attributes of the files in a backup file index corresponding to the previous backup of the virtual disk. The changed file module further stores the current attributes and extents for the changed files within blocks of a backup storage device for updating in the backup file index.