Abstract: Along with the miniaturization of the semiconductor memory device, the resistor and parasitic capacitance of the wires become large, which prevents the semiconductor memory device from being speeded up. In a semiconductor memory device having a semiconductor substrate having a main surface, a first memory cell row having a plurality of first memory cells arranged in parallel to a first direction in plan view on the main surface, a first word line connected to the plurality of first memory cells, a first word line driver for changing a potential of the first word line, and a control circuit for outputting a first predecode signal to the first word line driver via the first predecode line in response to a clock signal and an address signal, a repeater is inserted between the control circuit and the first word line driver.

Abstract: An apparatus is provided which comprises: a stack comprising a magnetic insulating material (MI such as EuS, EuO, YIG, TmIG, or GaMnAs) and a transition metal dichalcogenide (TMD such as MoS2, MoSe2, WS2, WSe2, PtS2, PtSe2, WTe2, MoTe2, or graphene), wherein the magnetic insulating material has a first magnetization; a magnet with a second magnetization, wherein the magnet is adjacent to the TMD of the stack; and an interconnect comprising a spin orbit material, wherein the interconnect is adjacent to the magnet.

Abstract: A memory system may include a memory device comprising a memory device including a plurality of nonvolatile memories, each nonvolatile memory including a plurality of blocks; and a controller configured to: perform a background read operation on a select nonvolatile memory among the plurality of nonvolatile memories using an initial read voltage; store the initial read voltage, as a history read voltage, in a history table; select the history read voltage from the history table in response to a read request from a host; and perform an initial read operation on the select nonvolatile memory using the history read voltage.

Abstract: Provided herein may be a memory device and a method of operating the same. The memory device may include a memory cell array including multiple planes, a peripheral circuit configured to perform an operation on the multiple planes, a control memory configured to store control codes for controlling the peripheral circuit, and a plurality of independent control logic configured to, when a command corresponding to each of the planes is received from a memory controller, control the peripheral circuit with reference to a control code corresponding to the command in response to the command. The control memory includes a common memory configured to be accessible in common by the plurality of independent control logic, and a temporary storage including areas respectively corresponding to the planes.

Abstract: According to one or more embodiments, a memory system includes a nonvolatile semiconductor memory, a capacitor, a constant current circuit, a measurement circuit, and a controller. The capacitor stores charges to be supplied to the nonvolatile semiconductor memory. The constant current circuit extracts the charge from the capacitor at a constant current. The measurement circuit measures a terminal voltage of the capacitor. The controller controls the nonvolatile semiconductor memory. The controller calculates a capacitance value of the capacitor based both on a resistance value of a leakage resistance of the capacitor and a change in the measured terminal voltage over time in each of a first period during which the capacitor naturally discharges and a second period during which the constant current circuit extracts the charge from the capacitor.

Abstract: Apparatuses are described that include stacked arrays of memory cell strings and their methods of operation. Apparatuses include architectures that reduce the use of several common components, allowing greater device density and smaller device size for a given semiconductor area.

Abstract: An integrated circuit memory device having: a memory cell; a current sensor connected to the memory cell; a voltage driver connected to the memory cell; and a bleed circuit connected to the voltage driver. During an operation to read the memory cell, the voltage driver drives a voltage applied on the memory cell. The bleed circuit is activated to reduce the voltage during a time period in which the current sensor operates to determine whether or not at least a predetermined level of current is presented in the memory cell.

Abstract: To reduce the area of a memory cell having a backup function. A storage device includes a cell array, and a row circuit and a column circuit that drive the cell array. The cell array includes a first power supply line, a second power supply line, a word line, a pair of bit lines, a memory cell, and a backup circuit. The cell array is located in a power domain where power gating can be performed. In the power gating sequence of the cell array, data in the memory cell is backed up to the backup circuit. The backup circuit is stacked over a region where the memory cell is formed. A plurality of wiring layers are provided between the backup circuit and the memory cell. The first power supply line, the second power supply line, the word line, and the pair of bit lines are located in different wiring layers.

Abstract: A method of protecting a DRAM memory device from the row hammer effect, the memory device comprising a plurality of banks composed of memory rows, may be implemented by at least one logic prevention device configured to respectively associate contiguous sections of rows of a bank with sub-banks. The prevention logic is also configured to execute a preventive refresh cycle of the sub-banks that is entirely executed before the number of rows activated in a sub-bank exceed a critical hammer value. A DRAM memory device, a buffer circuit or a controller of such a memory may comprise the logic for preventing the row hammer effect.

Abstract: Technologies for a three-dimensional (3D) multi-bit non-volatile dynamic random access memory (nvDRAM) device, which may include a DRAM array having a plurality of DRAM cells with single or dual transistor implementation and a non-volatile memory (NVM) array having a plurality of NVM cells with single or dual transistor implementations, where the DRAM array and the NVM array are arranged by rows of word lines and columns of bit lines. The nvDRAM device may also include one or more of isolation devices coupled between the DRAM array and the NVM array and configured to control connection between the dynamic random access bit lines (BLs) and the non-volatile BLs. The word lines run horizontally and may enable to select one word of memory data, whereas bit lines run vertically and may be connected to storage cells of different memory address.

Abstract: A method is described. The method includes receiving from a memory controller configuration information for a testing sequence and storing the configuration information in configuration register space of the driver circuit. The method also includes controlling the next testing sequence. The testing sequence includes sweeping values of a tap coefficient of a DFE circuit of the driver circuit and sweeping a voltage of a slicer of the driver circuit. The method includes sending results of the testing sequence to the memory controller. The results are to determine a value for the DFE tap coefficient.

Abstract: The present technology relates to a semiconductor memory device and a method of operating the semiconductor memory device. The semiconductor memory device includes a memory cell array including a plurality of memory blocks, which are assigned as a plurality of normal blocks, a plurality of first replacement blocks, a plurality of second replacement blocks, a first CAM block, and a second CAM block, a peripheral circuit configured to perform an erase operation and a program operation on the plurality of memory blocks, and a control logic configured to control the peripheral circuit to perform a growing bad block check operation on a target block during the program operation on a selected target block among the normal memory blocks.

Abstract: A variety of applications can include a memory device designed to perform sensing of a memory cell of a string of memory cells using a modified shielded bit line sensing operation. The modified shielded bit line sensing operation includes pre-charging a data line corresponding to the string with the string enabled to couple to the data line. The modified shielded bit line sensing operation can be implemented in a hybrid initialization routine for the memory device. The hybrid initialization routine can include a sensing read routine corresponding to an all data line configuration of data lines of the memory device and a modified sensing read routine corresponding to a shielded data line configuration of the data lines with selected strings enabled during pre-charging. A read retry routine associated with the modified sensing read routine can be added to the hybrid initialization routine. Additional devices, systems, and methods are discussed.

Abstract: Memories having an array of memory cells might include a plurality of voltage generation systems each having a respective output selectively connected to a respective access line, and a voltage regulator having an input connected to the output of each of the voltage generation systems, and having an output selectively connected to the respective access line for each of the voltage generation systems.

Abstract: An integrated circuit may include an amplifier circuit configured to receive a pull-up voltage in response to a pull-up enable signal, receive a pull-down voltage in response to a pull-down enable signal, and amplify a voltage difference between a first line and a second line through the pull-up and pull-down voltages; a first delay path configured to generate the pull-down enable signal by delaying an input signal; and a second delay path configured to generate the pull-up enable signal by delaying the input signal, wherein a change in a delay of the first delay path due to variation of a power supply voltage is smaller than a change in a delay of the second delay path due to the variation.

Abstract: The present disclosure discloses a ternary content addressable memory based on a memory diode, which includes a plurality of kernel units having functions of storing data, erasing/writing data, and comparing data; the kernel units are arranged in an array, all kernel units in a unit of row are connected to a same matching line, and all kernel units in a unit of column are connected to a same pair of complementary search signal lines; the kernel unit includes two memory diodes; top electrodes of a first memory diode and a second memory diode are respectively connected to a pair of complementary search signal lines, and bottom electrodes of the first memory diode and the second memory diode are connected to a same matching line.

Abstract: A memory includes memory cells having two select transistors per cell. Each of the two select transistors are coupled to two different word lines with each word line being controlled by a separate addressable word line driver circuit. In some embodiments, providing two different word lines from two different word line drivers may provide for a memory where the word lines can apply different voltages based on the memory operation being performed.

Abstract: A semiconductor device includes a read/write control circuit, a core circuit, and a data conversion circuit. The read/write control circuit generates a read strobe signal and a read address from an internal address/command signal based on an internal read command during a self-write operation, generates a write strobe signal after the read strobe signal is generated, and generates a write address from the internal address/command signal. The core circuit is synchronized with the read strobe signal to output read data stored in a bank selected by the read address and is synchronized with the write strobe signal to store write data into the bank or another bank which is selected by the write address. The data conversion circuit changes a pattern of the read data to generate the write data.

Abstract: A computing device in some examples includes an array of memory cells, such as 8-transistor SRAM cells, in which the read bit-lines are isolated from the nodes storing the memory states such that simultaneous read activation of memory cells sharing a respective read bit-line would not upset the memory state of any of the memory cells. The computing device also includes an output interface having capacitors connected to respective read bit-lines and have capacitance that differ, such as by factors of powers of 2, from each other. The output interface is configured to charge or discharge the capacitors from the respective read bit-lines and to permit the capacitors to share charge with each other to generate an analog output signal, in which the signal from each read bit-line is weighted by the capacitance of the capacitor connected to the read bit-line. The computing device can be used to compute, for example, sum of input weighted by multi-bit weights.

Abstract: Methods and apparatus for sensing a memory cell using lower offset, higher speed sense amplifiers are described. A sense amplifier may include an amplifier component that is configurable to operate in an amplifier mode or a latch mode. In some examples, the amplifier component may be configured to operate in the amplifier or latch mode by activating or deactivating switching components inside the amplifier component. When configured to operate in the amplifier mode, the amplifier component may be used, during a read operation of a memory cell, to pre-charge a digit line and/or amplify a signal received from the memory cell. When configured to operate in the latch mode, the amplifier component may be used to latch a state of the memory cell. In some cases, the amplifier component may use some of the same internal circuitry for pre-charging the digit line, amplifying the signal, and/or latching the state.