Patents Examined by Minh N. Tang
  • Patent number: 11169200
    Abstract: A method for characterizing an integrated circuit that includes ramping the supply voltage to an integrated circuit as a function of time for each of the transistors in the integrated circuit, and measuring a power supply current for the integrated circuit during the ramping of the power supply voltage. The measured peaks in the power supply current are a current pulse that identifies an operation state in which each of the transistors are in an on state. The peaks in the power supply current are compared to the reference peaks for the power supply current for a reference circuit having a same functionality as the integrated circuit to determine the integrated circuit's fitness.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: November 9, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Raphael P. Robertazzi, Peilin Song, Franco Stellari
  • Patent number: 11167321
    Abstract: A solar panel cleaning system includes: an automated cleaning device for cleaning a surface of a reference cell panel; a cleaning device controller in communication with a motor of the automated cleaning device, the cleaning device controller configured to receive a signal corresponding to measurement of a current of photovoltaic system. The cleaning device controller activates the automated cleaning device to clean a surface of the reference cell panel when the received signal indicates that a measurement of the current of the photovoltaic system is to be taken.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: November 9, 2021
    Inventor: Ryan Bower Jones
  • Patent number: 11131705
    Abstract: A request to perform a test with one or more memory components can be received. Available test resources of a test platform that is associated with memory components can be determined. The desired characteristics of the one or more memory components that are specified by the test can be determined. One or more of the available test resources of the test platform to the test can be assigned based on characteristics of respective memory components associated with the one or more of the available test resources and the desired characteristics of the one or more memory components of the test. Furthermore, the test can be performed with the assigned one or more of the available test resources of the test platform.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: September 28, 2021
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Aswin Thiruvengadam, Sivagnanam Parthasarathy, Frederick Jensen
  • Patent number: 11125803
    Abstract: The present application relates to a technique of reducing the occurrence of a spot breakdown near a probe needle with the intention of preventing damage on the probe needle during a test implemented by applying a high voltage to a semiconductor device. In a method of measuring a semiconductor device, the semiconductor device includes: a semiconductor substrate (1), an epitaxial layer (2), at least one second conductivity type region (3) of a second conductivity type formed in a part of the surface layer of the epitaxial layer to have a contour, a Schottky electrode (11), an anode electrode (12), and a cathode electrode (13). A voltage is applied while the probe needle (21) is brought into contact with the upper surface of the anode electrode in a range in which the contour of the at least one second conductivity type region is formed in a plan view.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: September 21, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventors: Koji Okuno, Shozo Shikama, Yoichiro Tarui
  • Patent number: 11119147
    Abstract: An environment control device and a chip testing system are provided. An apparatus body of the environment control device includes a plurality of accommodating chambers. Each of the accommodating chambers has a temperature adjusting device disposed therein. Each of the accommodating adjusting devices includes a temperature adjuster, a contacting structure, a frame body, and an elastic annular enclosed member. When a chip testing device carrying a plurality of chips is disposed in one of the accommodating chambers, and the contacting structure contacts one side of the chips, the elastic annular enclosed member is abutted against the chip testing device, and the chip testing device and the contacting structure jointly define an enclosed space. The temperature adjuster can correspondingly adjust the temperature of the contacting structure so that the chip testing device can perform a predetermined testing process on the chips in a predetermined temperature environment.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: September 14, 2021
    Assignee: ONE TEST SYSTEMS
    Inventors: Chen-Lung Tsai, Gene Rosenthal
  • Patent number: 11105845
    Abstract: An integrated circuit (IC) chip for providing a safety-critical value includes first and second processing paths. The first processing path includes a first processing element and is coupled to receive a first input signal on a first input pin and to provide a first output signal that provides the safety-critical value on an output pin. The second processing path includes a second processing element and is coupled to receive a second input signal and to provide a second output signal. The first processing path and the second processing path are independent of each other. A smart comparator on the IC chip receives the first output signal and the second output signal and initiates a remedial action responsive to a difference between the first output signal and the second output signal reaching a configurable threshold.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: August 31, 2021
    Assignee: Texas Instruments Incorporated
    Inventors: Jeffrey Earl Stafford, Prasanth Viswanathan Pillai, Ashish Arvind Vanjari
  • Patent number: 11099233
    Abstract: The present disclosure discloses a chip abnormality detecting circuit and a chip abnormality detecting device. The circuit includes an abnormal signal detecting circuit configured to detect a reverse cutoff characteristic of an electrostatic discharge (ESD) protection diode of the chip to be detected, and output a corresponding detection signal.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: August 24, 2021
    Assignees: HKC Corporation Limited, Chongqing HKC Optoelectronics Technology Co., Ltd.
    Inventor: Xiaoyu Huang
  • Patent number: 11092620
    Abstract: Provided is a conduction inspection device member, wherein cracks and voids are less likely to form in conductive parts, conduction performance is less likely to be impaired even when a conduction test is repeated, and contact marks are less likely to remain in the portion of the member in contact with a member to be tested. Also provided is a conduction inspection device comprising the conduction inspection device member. The conduction inspection device member comprises a substrate 13, through holes 11, and conductive parts 12. The multiple through holes 11 are arranged in the substrate 13, the conductive parts 12 are housed inside the through holes 11, and the conductive parts 12 contain conductive particles 2. The conductive particles 2 each comprise a substrate particle 21 and a conductive layer 22 on the surface of the substrate particle 21. The conductive layer 22 has multiple protrusions 23 on the outer surface thereof.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: August 17, 2021
    Assignee: SEKISUI CHEMICAL CO., LTD.
    Inventors: Masao Sasadaira, Xiaoge Wang
  • Patent number: 11092619
    Abstract: An active split-signal Fo and 2Fo harmonic impedance load pull tuner uses a single signal source, a wideband harmonic amplitude and phase modulator-frequency doubler. The Fo source signal path is divided between input and output of the DUT; the output portion is processed to generate independently controlled synchronous amplitude and phase controlled Fo and 2Fo signals, which are then amplified and re-injected into the output of the DUT after being pre-matched using a passive harmonic tuner. A harmonic receiver is used to synthesize in situ the required Fo and 2Fo load impedances. Passive 3Fo tuning is also possible independently.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: August 17, 2021
    Inventor: Christos Tsironis
  • Patent number: 11092641
    Abstract: An inspection apparatus includes: a stage on which an inspection target is mounted; a temperature adjustment mechanism configured to adjust a temperature of the stage; an inspecting part configured to exchange electrical signals for an electrical characteristics inspection with the inspection target; a probe card having terminals in contact with the inspection target; an intermediate connection member having connectors electrically connecting the inspecting part and the probe card; a position adjustment mechanism configured to adjust a relative position between the stage and the probe card; a temperature measurement member configured to measure a temperature of the intermediate connection member; a preliminary temperature adjusting part configured to adjust a temperature of the probe card prior to the electrical characteristics inspection; and a determining part configured to determine whether or not the temperature of the probe card is stabilized, based on the temperature of the intermediate connection membe
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: August 17, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Jun Fujihara
  • Patent number: 11092651
    Abstract: A high-frequency characteristic inspection apparatus includes a pair of high-frequency probes that inspect an electrical characteristic of a plane circuit including a signal region and a ground region formed apart from each other by an S parameter obtained by pushing a tip against a surface of the plane circuit and discharging a high frequency and a measurement apparatus. The high-frequency probe includes a ground terminal that is in contact with the ground region at its tip and a signal terminal that is in contact with the signal region simultaneously with the ground terminal at its tip. The pair of high-frequency probes are configured to contact with a surface of the plane circuit at the same time while facing each other at a certain interval.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: August 17, 2021
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventor: Ryo Sakamaki
  • Patent number: 11067622
    Abstract: A method for testing a printed circuit board includes providing a printed circuit board having a first main section, a second main section, a bent connecting section and at least one monitoring conductor track. The connecting section is disposed between the first main section and the second main section. The monitoring conductor track runs from the first main section, in a curved manner through the connecting section, to the second main section. At least one electrical measurement value which is representative of the integrity of the at least one monitoring conductor track is detected. A printed circuit board, a control unit and methods for producing the printed circuit board and for operating the control unit are also provided.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: July 20, 2021
    Assignee: Vitesco Technologies GmbH
    Inventors: Detlev Bagung, Hubert Horn
  • Patent number: 11061082
    Abstract: A Hall effect sensor system includes a Hall effect sensor and a drive-sense circuit (DSC). The Hall effect sensor includes an input port to receive a DC (direct current) current signal and generates a Hall voltage based on exposure to a magnetic field. The DSC generates the DC current signal based on a reference signal and drives it via a single line that operably couples the DSC to the Hall effect sensor and simultaneously to sense the DC current signal via the single line. The DSC detects an effect on the DC current signal corresponding to the Hall voltage that is generated across the Hall effect sensor based on exposure of the Hall effect sensor to the magnetic field and generates a digital signal representative of the Hall voltage.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: July 13, 2021
    Assignee: SIGMASENSE, LLC.
    Inventors: Patrick Troy Gray, Gerald Dale Morrison, Daniel Keith Van Ostrand, Richard Stuart Seger, Jr.
  • Patent number: 11061055
    Abstract: A three-phase power meter can monitor power on both 3-wire and 4-wire power lines. The power meter measures at least two voltages between phase conductors of the power line, and at least one voltage between a phase conductor and a neutral conductor of the power line when the neutral conductor is available. Using at least some of the measured voltages, the power meter can then operate in a first mode when coupled to a 3-wire power line to determine power on the power line based on the measured voltages, or operate in a second mode when coupled to a 4-wire power line to determine power on the power line based on the measured voltages.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: July 13, 2021
    Assignee: Analog Devices International Unlimited Company
    Inventors: Petre Minciunescu, Seyed Amir Ali Danesh
  • Patent number: 11054465
    Abstract: A method of operating a probing apparatus is disclosed. The method includes providing a chuck configured to support a DUT, a probe card disposed above the DUT and having a probe, and an inspection module configured to determine positions of the DUT and the probe. The method further includes determining a first position of a DUT by an inspection module; moving a probe card to align a first position of a probe with the first position of the DUT; moving a chuck toward the probe; adjusting a temperature of the probe to a predetermined temperature by a temperature-controlling device; determining a second position of the probe by the inspection module after the adjustment of the temperature of the probe; moving the probe card to align the probe with the position of the DUT based on the determination of the second position of the probe; and probing the DUT.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: July 6, 2021
    Assignee: STAR TECHNOLOGIES, INC.
    Inventors: Choon Leong Lou, Yi Ming Lau
  • Patent number: 11041882
    Abstract: An active split-signal Fo and 2Fo harmonic impedance load pull tuner uses a single signal source, a wideband harmonic amplitude and phase modulator-frequency doubler. The Fo source signal path is divided between input and output of the DUT; the output portion is processed to generate independently controlled synchronous amplitude and phase controlled Fo and 2Fo signals, which are then amplified and re-injected into the output of the DUT after being pre-matched using a passive harmonic tuner. A harmonic receiver is used to synthesize in situ the required Fo and 2Fo load impedances. Passive 3Fo tuning is also possible independently.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: June 22, 2021
    Inventor: Christos Tsironis
  • Patent number: 11036898
    Abstract: Methods and systems for generating measurement models of nanowire based semiconductor structures based on re-useable, parametric models are presented herein. Metrology systems employing these models are configured to measure structural and material characteristics (e.g., material composition, dimensional characteristics of structures and films, etc.) associated with nanowire semiconductor fabrication processes. The re-useable, parametric models of nanowire based semiconductor structures enable measurement model generation that is substantially simpler, less error prone, and more accurate. As a result, time to useful measurement results is significantly reduced, particularly when modelling complex, nanowire based structures. The re-useable, parametric models of nanowire based semiconductor structures are useful for generating measurement models for both optical metrology and x-ray metrology, including soft x-ray metrology and hard x-ray metrology.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: June 15, 2021
    Assignee: KLA-Tencor Corporation
    Inventors: Houssam Chouaib, Alexander Kuznetsov
  • Patent number: 11022641
    Abstract: A modular computer system includes a plurality of circuit modules, each of which includes one or more components that are subject to failure, such as a vacuum tube. A carrier assembly is added to each circuit module of the modular computer system. The carrier assembly hosts monitoring circuitry that indicates the proper functioning of one or more components on the attached module. In one implementation, each module includes a vacuum tube, and a coil located on the carrier assembly is connected in series with the heater of the vacuum tube. A Hall effect sensor is positioned near the coil. If the heater of the vacuum tube fails, the flow of current through the coil is interrupted and is detected by the Hall effect sensor. The Hall effect sensor is connected to an LED that indicates failure of the vacuum tube.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: June 1, 2021
    Assignee: Vulcan Inc.
    Inventor: Keith John Perez
  • Patent number: 11022643
    Abstract: A testing apparatus includes a chip carrying device and a pressing device. The chip carrying device includes a circuit board and a plurality of electrically connecting units disposed on the circuit board. Each electrically connecting unit includes a main body disposed on the circuit board to form an accommodating slot, a lift structure partially arranged in the accommodating slot. A portion of the lift structure having a chip receiving slot passes through an opening of the main body. The pressing device includes a temperature conditioner being controllable to increase or decrease temperature. When the lift structure is pressed by a flat structure of the temperature conditioner, the probe assemblies are connected to one side of a chip received in the chip receiving slot, and the flat contacting surface is abutted against another side of the chip for transmitting heat energy there-between.
    Type: Grant
    Filed: September 2, 2019
    Date of Patent: June 1, 2021
    Assignee: ONE TEST SYSTEMS
    Inventors: Chen-Lung Tsai, Gene Rosenthal
  • Patent number: 11016216
    Abstract: Systems and methods to investigate multi-pipe structures for detection of corrosion and quantitative assessment of thickness in the multiple pipes can be implemented in a variety of applications. Systems can include a set of transmitters and multiple receivers arranged on a tool structure with variable distances to the transmitters of the set of transmitters, where the receivers are arranged to measure electromagnetic responses from a multi-pipe structure to excitation of the set of transmitters with the tool structure disposed in the multi-pipe structure. The electromagnetic responses may include responses correlated to a near field zone, a transition zone, and a far field zone, where the electromagnetic responses can be processed to recover individual thicknesses of each pipe of the multi-pipe structure. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: May 25, 2021
    Assignee: Halliburton Energy Services, Inc.
    Inventors: Luis Emilio San Martin, Reza Khalaj Amineh