Patents Examined by Minh Nguyen
  • Patent number: RE49164
    Abstract: According to one embodiment, a semiconductor device includes a first element isolating area, a first element area surrounding the first element isolating area, a second element isolating area surrounding the first element area a first gate electrode provided on and across the first element isolating area, the first element area, and the second element isolating area, and a second gate electrode isolated from the first gate electrode and provided on and across the first element isolating area, the first element area, and the second element isolating area.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: August 9, 2022
    Assignee: Kioxia Corporation
    Inventors: Kosuke Yanagidaira, Kazuhide Yoneya
  • Patent number: RE49209
    Abstract: An image sensor includes a plurality of photoelectric detectors, a plurality of color filters, and at least one pixel isolation region between adjacent ones of the photoelectric detectors. The color filters include a white color filter, and the color filters correspond to respective ones of the photoelectric detectors. The at least one pixel isolation region serves to physically and at least partially optically separate the photoelectric detectors from one another.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: September 13, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-Chak Ahn, Bum-Suk Kim
  • Patent number: RE49298
    Abstract: The present invention provides a light emitting element capable or realizing at least one of lower resistance, higher output, higher power efficiency (1 m/W), higher mass productivity and lower cost of the element using a light transmissive electrode for an electrode arranged exterior to the light emitting structure. A semiconductor light emitting element includes a light emitting section, a first electrode and a second electrode on a semiconductor structure including first and second conductive type semiconductor layers, the first and the second electrodes respectively including at least two layers of a first layer of a light transmissive conductive film conducting to the first and the second conductive type semiconductor and a second layer arranged so as to conduct with the first layer. First and second light transmissive insulating films are respectively arranged so as to overlap at least one part of the first and the second layers.
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: November 15, 2022
    Assignee: NICHIA CORPORATION
    Inventors: Masahiko Sano, Takahiko Sakamoto, Keiji Emura, Katsuyoshi Kadan
  • Patent number: RE49333
    Abstract: A solid state imaging device includes a substrate, in which the substrate includes a photoelectric conversion unit that generates a charge according to a light amount of incident light by a pixel unit, an accumulation unit that divides the charge of the pixel unit which is generated in the photoelectric conversion unit and accumulates the charge, a first element isolation unit that is formed at a boundary of the photoelectric conversion unit of the pixel unit, and a second element isolation unit that is formed at a boundary of the accumulation unit of a divided unit of the pixel.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: December 13, 2022
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Hiroaki Seko
  • Patent number: RE49336
    Abstract: The printing apparatus of the present invention includes: a print head; and a liquid storage container in which a liquid storage chamber that stores a liquid to be supplied to the print head, an atmosphere communication chamber that communicates with the atmosphere, and a communication flow path that causes the liquid storage chamber and the atmosphere communication chamber to communicate are formed integrally. The liquid storage container can take a first posture in which the atmosphere communication chamber is located under the liquid storage chamber in the direction of gravity and a second posture in which the atmosphere communication chamber and the liquid storage chamber are located side by side in the horizontal direction. In the case where the liquid storage container is in the second posture, the liquid injection portion and the communication flow path are located on the upper side of the liquid storage container.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: December 20, 2022
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Yukimichi Kimura, Takahiro Kiuchi, Junichi Kubokawa, Kyohei Sato, Koki Shimada, Masaya Shimmachi, Yusuke Tanaka, Hideaki Matsumura, Keiichiro Tsukuda, Tatsuo Nanjo
  • Patent number: RE49345
    Abstract: An aquarium having an adjustable lighting system for enhancing the display of fluorescent objects, such as fluorescent fish, contained within the aquarium under various external lighting conditions, such as a dark room or a brightly lit room. The aquarium comprises a tank and a plurality of light sources. Each light source emits light at a different wavelength spectrum which is selected to enhance the display of the fluorescent object under each type of external lighting condition. An electronic control is provided to control the operation of the plurality of light sources such that each light source may be selectively turned on/off based on the external lighting condition, or chronological criteria, to provide the best viewing experience.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: December 27, 2022
    Assignee: GloFish, LLC
    Inventor: Alan Blake
  • Patent number: RE49364
    Abstract: A memory element including a layered structure including a memory layer having magnetization perpendicular to a film face in which a direction of the magnetization is changed depending on information stored therein, a magnetization-fixed layer having magnetization perpendicular to the film face, which becomes a base of the information stored in the memory layer, and an intermediate layer that is formed of a non-magnetic material and is provided between the memory layer and the magnetization-fixed layer.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: January 10, 2023
    Assignee: Sony Corporation
    Inventors: Hiroyuki Uchida, Masanori Hosomi, Hiroyuki Ohmori, Kazuhiro Bessho, Yutaka Higo, Tetsuya Asayama, Kazutaka Yamane
  • Patent number: RE49406
    Abstract: The present invention provides a light emitting element capable or realizing at least one of lower resistance, higher output, higher power efficiency (1 m/W), higher mass productivity and lower cost of the element using a light transmissive electrode for an electrode arranged exterior to the light emitting structure. A semiconductor light emitting element includes a light emitting section, a first electrode and a second electrode on a semiconductor structure including first and second conductive type semiconductor layers, the first and the second electrodes respectively including at least two layers of a first layer of a light transmissive conductive film conducting to the first and the second conductive type semiconductor and a second layer arranged so as to conduct with the first layer. First and second light transmissive insulating films are respectively arranged so as to overlap at least one part of the first and the second layers.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: January 31, 2023
    Assignee: NICHIA CORPORATION
    Inventors: Masahiko Sano, Takahiko Sakamoto, Keiji Emura, Katsuyoshi Kadan
  • Patent number: RE49407
    Abstract: A lithium secondary battery pack of the present invention includes: a lithium secondary battery including an electrode body formed of a positive electrode and a negative electrode facing each other and a separator interposed therebetween, and a non-aqueous electrolyte; a PTC element; and a protection circuit including a field effect transistor. The lithium secondary battery has an energy density per volume of 450 Wh/L or more, the lithium secondary battery has a current density of 3.0 mA/cm2 or less, and a relational expression (1) and a relational expression (2) below are established where A (m?) is an impedance of the lithium secondary battery and B (m?) is an impedance of the entire circuit unit of the lithium secondary battery pack excepting the impedance A (m?) of the lithium secondary battery: A?50 m???(1) B/A?1??(2).
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: January 31, 2023
    Assignee: Maxell, Ltd.
    Inventors: Haruki Kamizori, Masayuki Yamada, Fusaji Kita
  • Patent number: RE49439
    Abstract: Described is an apparatus which comprises: a first die including: a processing core; a crossbar switch coupled to the processing core; and a first edge interface coupled to the crossbar switch; and a second die including: a first edge interface positioned at a periphery of the second die and coupled to the first edge interface of the first die, wherein the first edge interface of the first die and the first edge interface of the second die are positioned across each other; a clock synchronization circuit coupled to the second edge interface; and a memory interface coupled to the clock synchronization circuit.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: February 28, 2023
    Assignee: Intel Corporation
    Inventors: Surhud Khare, Dinesh Somasekhar, Shekhar Y. Borkar
  • Patent number: RE49525
    Abstract: An semiconductor device is provided. A fin is disposed on a substrate, extending in a lengthwise direction. A first recess is disposed on a sidewall of the fin so that the fin and the first recess is arranged in a straight line along the lengthwise direction. A gate structure crosses the fin in the first direction crossing the lengthwise direction. A spacer is disposed on sidewalk of the gate structure. A source/drain region is disposed in the first recess. The source/drain region is formed under the spacer. A silicide layer is disposed on the source/drain region. The silicide layer and the source/drain region fill the first recess.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: May 9, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-Il Bae, Bomsoo Kim, Yong-Min Cho
  • Patent number: RE49596
    Abstract: Discussed is a flexible display device to reduce a width of a bezel. The flexible display device includes a substrate being formed of a flexible material, a plurality of gate lines and a plurality of data lines crossing each other, a plurality of pads formed in a pad area of a non-display area, a plurality of links formed in a link area of the non-display area a plurality of insulation films formed over the entire surface of the substrate, and a first bending hole formed in a bending area of the non-display area, the first bending hole passing through at least one of the insulation films disposed under the link, wherein the bending area is bent such that the pads are disposed on the lower surface of the substrate.
    Type: Grant
    Filed: August 21, 2020
    Date of Patent: August 1, 2023
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Sang-Cheon Youn, Hyoung-Suk Jin, Chang-Heon Kang, Se-Yeoul Kwon
  • Patent number: RE49631
    Abstract: A semiconductor device and a production method thereof capable of reducing warps of a semiconductor wafer when packaging at a wafer level in a SiP type semiconductor device, is configured that an insulating layer is formed by stacking a plurality of resin layers on a semiconductor chip formed with an electronic circuit, wiring layers are buried in the insulating layer and electrically connected to electrodes, and formation areas of the plurality of resin layers become gradually smaller from an area of an upper surface of the semiconductor chip as they get farther from the semiconductor chip, so that a side surface and an upper surface of each of the resin layers and the upper surface of the semiconductor chip form a stepwise shape.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: August 29, 2023
    Assignee: SONY CORPORATION
    Inventor: Osamu Yamagata
  • Patent number: RE49657
    Abstract: Provided is an epitaxial wafer having an excellent gettering capability and a suppressed formation of epitaxial defects. The epitaxial wafer has a specified resistivity, and includes a modifying layer formed on a surface portion of the silicon wafer and composed of a predetermined element including at least carbon, in the form of a solid solution in the silicon wafer; and an epitaxial layer having a resistivity that is higher than the resistivity of the silicon wafer, wherein a concentration profile of the predetermined element in the modifying layer in a depth direction thereof meets a specified full width half maximum and a specified peak concentration.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: September 12, 2023
    Assignee: SUMCO CORPORATION
    Inventors: Takuro Iwanaga, Kazunari Kurita, Takeshi Kadono
  • Patent number: RE49661
    Abstract: A solid state imaging device includes a substrate, in which the substrate includes a photoelectric conversion unit that generates a charge according to a light amount of incident light by a pixel unit, an accumulation unit that divides the charge of the pixel unit which is generated in the photoelectric conversion unit and accumulates the charge, a first element isolation unit that is formed at a boundary of the photoelectric conversion unit of the pixel unit, and a second element isolation unit that is formed at a boundary of the accumulation unit of a divided unit of the pixel.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: September 19, 2023
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Hiroaki Seko
  • Patent number: RE49704
    Abstract: A semiconductor radiation detector device includes a semiconductor substrate. On one surface of the substrate are a MIG layer (241) of semiconductor of second conductivity type, a barrier layer (251) of semiconductor of first conductivity type, and pixel dopings of semiconductor of the second conductivity type. The pixel dopings are adapted to be coupled to at least one pixel voltage in order to create a source and a drain of a pixel-specific transistor. The device further includes a first conductivity type first contact, so that the pixel voltage is a potential difference between one of the pixel dopings and the first conductivity type first contact. The location of a main gate (983) corresponds at least partly to the location of a channel between the source and the drain. The device includes at least one extra gate (981, 982) horizontally displaced from the main gate (983).
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: October 17, 2023
    Inventor: Artto Aurola
  • Patent number: RE49715
    Abstract: A memory array comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually include a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region. At least a portion of the channel region is horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions. The memory cells individually include a capacitor comprising first and second electrodes having a capacitor insulator there-between. The first electrode is electrically coupled to the first source/drain region. The second capacitor electrodes of multiple of the capacitors in the array are electrically coupled with one another. A sense-line structure extends elevationally through the vertically-alternating tiers.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: October 24, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Martin C. Roberts, Sanh D. Tang, Fred D. Fishburn
  • Patent number: RE49794
    Abstract: A double sidewall image transfer process for forming FinFET structures having a fin pitch of less than 40 nm generates paired fins with a spacing determined by the width of a sidewall spacer that forms a second mandrel. Here, the fin pairs are created at two different spacings without requiring the minimum space for the standard sidewall structure. An enlarged space between paired fins is created by placing two first mandrel shapes close enough so as to overlap or merge two sidewall spacer shapes so as to form a wider second mandrel upon further processing. The fin pair created from the wider second mandrel is spaced at about 2 times the fin pair created from the narrower second mandrel. For some circuits, such as an SRAM bitcell, the wider second mandrel can be utilized to form an inactive fin not utilized in the circuit structure, which can be removed. In some embodiments, all dummy inactive fins are eliminated for a simpler process.
    Type: Grant
    Filed: October 8, 2020
    Date of Patent: January 9, 2024
    Assignee: Adeia Semiconductor Solutions LLC
    Inventors: Mary E. Weybright, Robert C. Wong
  • Patent number: RE49884
    Abstract: A system and method for imaging biological samples on multiple surfaces of a support structure are disclosed. The support structure may be a flow cell through which a reagent fluid is allowed to flow and interact with the biological samples. Excitation radiation from at least one radiation source may be used to excite the biological samples on multiple surfaces. In this manner, fluorescent emission radiation may be generated from the biological samples and subsequently captured and detected by detection optics and at least one detector. The detected fluorescent emission radiation may then be used to generate image data. This imaging of multiple surfaces may be accomplished either sequentially or simultaneously. In addition, the techniques of the present invention may be used with any type of imaging system. For instance, both epifluorescent and total internal reflection methods may benefit from the techniques of the present invention.
    Type: Grant
    Filed: June 8, 2021
    Date of Patent: March 26, 2024
    Assignee: ILLUMINA, INC.
    Inventors: Wenyi Feng, Jason Bryant, Steven Barnard, Maria Candelaria Rogert Bacigalupo
  • Patent number: RE49962
    Abstract: According to one embodiment, a semiconductor device includes first and second regions, a first insulating portion, and first, second, and third electrodes. The first region includes first and second partial regions, and a third partial region between the first and second partial regions. The second region includes fourth and fifth partial regions. The fourth partial region overlaps the first partial region. The fifth partial region overlaps the second partial region. The first insulating portion includes first, second, and third insulating regions. The first insulating region is provided between the second insulating region and the third partial region and between the third insulating region and the third partial region. The first electrode is electrically connected to the fourth partial region. The second electrode is away from the first electrode and is electrically connected to the fifth partial region. The third electrode is provided between the first and second electrodes.
    Type: Grant
    Filed: April 29, 2022
    Date of Patent: May 7, 2024
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Masahiko Kuraguchi, Yosuke Kajiwara, Aya Shindome, Hiroshi Ono, Daimotsu Kato, Akira Mukai