Semiconductor radiation detector
A semiconductor radiation detector device includes a semiconductor substrate. On one surface of the substrate are a MIG layer (241) of semiconductor of second conductivity type, a barrier layer (251) of semiconductor of first conductivity type, and pixel dopings of semiconductor of the second conductivity type. The pixel dopings are adapted to be coupled to at least one pixel voltage in order to create a source and a drain of a pixel-specific transistor. The device further includes a first conductivity type first contact, so that the pixel voltage is a potential difference between one of the pixel dopings and the first conductivity type first contact. The location of a main gate (983) corresponds at least partly to the location of a channel between the source and the drain. The device includes at least one extra gate (981, 982) horizontally displaced from the main gate (983).
The invention is related to semiconductor radiation detectors and particularly to semiconductor radiation detectors having a modified internal gate. A radiation detector is hereby defined as a device detecting photons, and/or high energy charged or neutral particles.
BACKGROUND OF THE INVENTIONThe patents U.S. Pat. No. 7,816,653, U.S. Pat. No. 8,148,760, and U.S. Pat. No. 8,288,837, which are incorporated herein by reference, disclose a semiconductor radiation detector having a so-called Modified Internal Gate (MIG). The MIG is an internal part of the semiconductor radiation detection, in which radiation-induced signal charges are collected so that the resulting net electric charge in the MIG causes measurable effects in the electric characteristics of pixels above it. Examples of such effects are changes in the current-carrying capability of the channel or base of a pixel-specific transistor. A barrier layer separates the MIG from said pixels. It constitutes, when appropriately biased, a potential energy barrier that keeps the accumulated signal charges in the MIG layer from mixing with charge carriers in the pixels, such as the charge carriers the flow of which constitutes the electric current through said channel or base. Additional information is also disclosed at the internet pages www.pixpolar.com/technology and www.pixpolar.com/blog as well as at several discussions on the blog www.image-sensors-world.blogspot.com.
In semiconductor radiation detectors the radiation induces electron hole pairs which are separated by an electric field. The charge type of the electron hole pair that is measured is referred to as signal charge and the opposite charge type is referred to as secondary charge.
The MIG detectors comprising typically a matrix of MIG pixels have several benefits over traditional radiation detectors like Complementary Metal Oxide Semiconductor (CMOS) image sensors. First of all, in the MIG pixel the interface generated charges do not mix with signal charges. Second, a buried channel having a large potential difference between the bottom of the channel and the interface can be utilized enabling considerable reduction in 1/f noise. Such a low 1/f noise buried channel results in much lower read noise. Third, Back-Side Illuminated (BSI) MIG pixels having 100% fill-factor can be easily designed. Fourth, it is easy to design fully depleted MIG pixels avoiding the diffusion of signal charges which enables very low cross-talk between pixels. Fifth, the MIG pixels comprise inherently a vertical anti-blooming mechanism meaning that blooming is not an issue. Sixth, thick fully depleted MIG pixels enable very good quantum efficiency for red and Near Infra-Red (NIR) light while cross-talk is kept at minimum level. Seventh, the signal charges are well aligned with the lowest channel threshold of the above lying readout transistor. Eighth, the MIG pixels enable linear current mode readout.
The ninth advantage is that the MIG pixels are very much compatible with analog CMOS processes. The reason for this is that leakage through the gate oxide is not an issue since the signal charge is not brought to the external gate. Another reason is that a pinned photo-diode is not required like in traditional CMOS image sensors. The pinned photodiode is difficult to design and it is actually an adaptation from Charge Coupled Devices (CCD) and it is not inherently present in a standard CMOS process. Also the interface quality is not an issue as it is in traditional CMOS image sensors. The outcome of these facts is that one has to develop a separate CMOS image sensor process for the production of traditional CMOS image sensors whereas an existing standard analog CMOS process can be used for the production of MIG image sensors.
Doped regions are physical entities, while the term pixel is more like a functional element, which means that—at least literally taken—pixels only appear in a semiconductor radiation detector when the power is on. Although separate contact dopings like the ones illustrated in
The first and second conductivity types correspond to n and p type or vice versa. In addition, in
The buried channel 261, 262 is not mandatory requirement for a MIG detector. A low 1/f noise buried channel offers, however, a considerable benefit for the MIG detector/pixel since it enables a significant reduction in the read noise and involves advantages in manufacturing. The latter fact is because the interface quality is of lesser importance due to the large potential difference between the interface and the channel. Thus a buried channel is an advantageous choice. A very important matter from noise point of view is also that when the pixel is reset one should be able to remove all the signal charges from the MIG layer 241, i.e., after reset the MIG layer should be fully depleted. During readout at the location where the signal charges are stored in the MIG layer the barrier layer should be fully depleted. If this is not the case the signal charges cannot properly modulate the threshold voltage of the channel and/or the current running in the channel meaning that the readout is disabled or at least inaccurate.
The arrangement of the opening 594 in the well doping 205 has been considered as the only reasonable choice for the following self-evident reasons. The fact that the STI and the contact doping are surrounded by the well doping means that the layered structure 241, 251, and 261 can be made thinner, which facilitates the coupling of the signal charges to the channel as well as the scaling of the pixel to smaller pixel sizes. In order to enable further thinning of the layered structure one could think that by arranging the opening of the well doping along the dashed line 295 the layered structure could be made even thinner because the source 213 and drain 214 dopings would be completely surrounded by the well doping 205. From the operation point of view this is, however, not recommendable since the highest threshold voltage or the highest channel resistance would be in the areas of the dashed ellipses 293 and 294 wherein the signal charge of MIG layer would have only very little effect due to the screening of the well doping.
For the above presented reasons the way to construct the opening in the well doping that has been considered the best—or even only—alternative is as depicted in
In case the external gate 181 of a single MIG pixel has to support three different voltage stages (readout, integration, and reset) the amount of signal charge that can be stored in the MIG layer can be very limited. One easy solution to this problem is that one can add a selection transistor to the source. In this manner one needs to utilize only two different voltages on the external gate 181, namely readout and reset. This improves the storing capacity, also known as the Full Well Capacity (FWC) of the MIG layer.
Another way to improve the FWC as well as the cross-talk is presented in
In case e.g. the semiconductor material is silicon, the electrically insulating material 335, 336, 337, and 338 is silicon dioxide, and the first conductivity type is n type and the second conductivity type is p type then it is beneficial to contact the walls 395, 396, 397, and 398 to the respective well dopings 305, 306, 307, and 308. In this manner no bias is required between the walls 395, 396, 397, and 398 and the well dopings 305, 306, 307, and 308 in order to form an accumulation or inversion layer of electrons at the interface between the substrate 301, 302, 303, and 304 and isolator walls 335, 336, 337, and 338. The reason for this is that the positive oxide charge in silicon dioxide is enough to create the accumulation or inversion layer of electrons. The benefit of the accumulation or inversion layer is that at the interfaces of the deep trenches protruding through the well dopings 305, 306, 307, and 308 it inhibits the formation of leakage current which would otherwise mix with the signal charges in the MIG layer (in the pixel of
In case the substrate material is silicon, the first conductivity type is n type, and the back-side layer 300 is formed of silicon dioxide an accumulation or inversion layer of electrons forms also at the back-side interface between the back-side layer 300 and the substrate 301, 302, 303, and 304 due to the positive oxide charge present in silicon dioxide. The great advantage of the arrangement is that the back-side silicon dioxide layer forms spontaneously on the back-side meaning that after the back-side thinning neither back-side implantation nor back-side laser annealing is required which simplifies processing and reduces back-side originated dark current. One should note, however, that even if the back-side layer 300 is formed spontaneously of silicon dioxide and only a simple trench 330 is used without the additional walls 335, 336, 337, and 338 as well as 395, 396, 397, and 398, the processing is still a demanding task due to the fact that high aspect ratio trenches are required since otherwise the fill-factor would be compromised. Another issue is naturally also that such a process would not be a standard CMOS process.
In the above listed patents (U.S. Pat. No. 7,816,653, U.S. Pat. No. 8,148,760, and U.S. Pat. No. 8,288,837 which are incorporated as reference) different types of reset structures have also been present which enable larger FWC. The problem with these reset structures has been, however, that they typically reduce the fill-factor.
Further, a publication WO 2007/077286 discloses a semiconductor radiation detector for detecting visible light. The semiconductor radiation detector comprises a structure wherein a first contact of a first conductivity type is adapted to collect secondary charges from a bulk layer being of first conductivity type material.
Document U.S. 2009/001435, in turn, discloses a semiconductor radiation detector device, which comprises means for reading signal charge from a modified internal gate layer using a floating gate configuration, in which a gate of a readout transistor floats in respect of said pixel voltage.
SUMMARY OF THE INVENTIONThe following presents a simplified summary in order to provide a basic understanding of some aspects of various invention embodiments. The summary is not an extensive overview of the invention. It is neither intended to identify key or critical elements of the invention nor to delineate the scope of the invention. The following summary merely presents some concepts of the invention in a simplified form as a prelude to a more detailed description of exemplifying embodiments of the invention.
According to an aspect of the invention there is provided a semiconductor radiation detector comprising the modified internal gate, in which the layered structure (MIG layer, barrier layer, and possibly the buried channel) can be made thinner facilitating pixel scaling. According to another aspect of the invention there is provided a reset structure which enables 100% fill-factor and which can potentially also be used for charge transfer.
Advantageous objectives of the invention are achieved with a semiconductor radiation detector comprising a semiconductor substrate; a modified internal gate layer of semiconductor of second conductivity type: a barrier layer of semiconductor of first conductivity type; pixel dopings of semiconductor of the second conductivity type, adapted to be coupled to at least one pixel voltage in order to create pixels corresponding to pixel dopings; first conductivity type first contact, said pixel voltage being defined as a potential difference between the pixel doping and the first conductivity type first contact; a main gate, and at least one extra gate horizontally displaced from the main gate.
An insight according to the invention can be utilized to build for example a tri-gate MIG transistor wherein the well doping completely surrounds the source and drain dopings. With the aid of the two extra gates artificial sources and drains can be created beneath the extra gates in order to insure that the highest threshold voltage or resistance of the channel is aligned with the signal charge present in the MIG layer.
In order to provide a reset structure enabling a high FWC without a reduction in the fill-factor a more weakly doped layered structure may be provided underneath a reset gate. Beneficially the reset gate can also be used for transfer of the signal charge.
The exemplary embodiments of the invention presented in this patent application are not to be interpreted to pose limitations to the applicability of the appended claims. The verb “to comprise” is used in this patent application as an open limitation that does not exclude the existence of also unrecited features. The features recited in depending claims are mutually freely combinable unless otherwise explicitly stated.
The novel features which are considered as characteristic of the invention are set forth in particular in the appended claims. The invention itself, however, both as to its construction and its method of operation, together with additional objects and advantages thereof, will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
CMOS transistors.
Parts of illustrated structures that have similar technical function are marked with the same reference designators throughout the drawings.
DETAILED DESCRIPTION OF EMBODIMENDS OF THE INVENTIONIn the following description we make use of certain basic vocabulary of semiconductor radiation detectors in which the amount of radiation-induced signal charge that accumulated within a pixel is detected with one or more pixel-specific transistors. A transistor is a semiconductor device where a region of semiconductor material, called the channel or the base, is located between two electrodes, which are a source and a drain in a field-effect transistor or an emitter and a collector in a bipolar junction transistor. The gate of a field effect transistor is a third electrode that is electrically insulated from the channel, so that the electric potential of the gate in relation to the source and drain (as well as to the bulk or substrate of the semiconductor detector) determines the current-carrying capability of the channel. In order to be called a gate, an electrode of a field-effect transistor must be suitably located in the structure so that the electric field that it induces has a measurable effect on at least part of the channel.
We also make use of a conventional selection concerning the way in which semiconductor radiation detectors are drawn in schematic cross-section representations. The lower edge of a cross section is said to represent the so-called back side of the detector chip, while its so-called front side is found at the top of the cross section. As such, the invention is not in any way bound to the definitions of back side and front side; in general we may say that the MIG-based transistor structures that are described in the following are on one surface, or some surface, of the substrate.
In addition there is an optional second conductivity type MIG layer enhancement doping 942. It is a region, the net doping of which is higher than the net doping of the remaining MIG layer around that region; the region of higher net doping in the MIG layer is vertically aligned with the gate 983. Enhancement dopings may be present also in the barrier layer 251 and in the buried channel 261; enhancement dopings of this kind could be all implanted with the same mask. In addition one could implant with the same mask also a doping beneath the MIG layer enhancement doping 942, which would be preferably of the first conductivity type. The purpose of the MIG layer enhancement doping 942 is to align the signal charges beneath the main (“external”) gate 983. Calling the gate 983 an “external” gate underlines its difference from the MIG layer 241, which constitutes—as its name indicates—an internal gate, or more appropriately a modified internal gate. In order to act as a gate, the main gate 983 is at a location which corresponds at least partly to the location of a channel between the source and the drain of the pixel-specific field-effect transistor.
In the structure of
A desirable feature from the operation point of view is that the highest channel threshold voltage and/or the highest channel resistance is beneath the main gate 983 with which the signal charges in the MIG layer are aligned. In order to achieve this goal the extra gates 981 and 982 are most advantageously biased such that threshold voltage and/or channel resistance is much lower beneath the extra gates 981 and 982 than beneath the main gate 983. We may characterize the location of the extra gates so that each extra gate is located above a corresponding MIG border region, at which a part of the channel in the pixel-specific transistor is vertically aligned with an edge of the MIG layer. In this manner an artificial source which is depicted by the dashed ellipse 991 is created beneath the gate 981 and an artificial drain which is depicted by the dashed ellipse 992 is created beneath the gate 982. The designator “artificial” is used here as a reminder of the fact that in the structural division of the transistor into doped regions, the regions illustrated with the ellipses 991 and 992 still belong to the channel, although operationally—taken an appropriate biasing of the external gates 981 and 982—they begin to behave as if they were extensions of the source and the drain respectively. This arrangement enables accurate readout of the signal charge present in the MIG layer.
In
The idea behind the double MIG pixel is that the signal charge can be transferred between the two MIGs beneath the main gates 983, 1085 in order to enable Non-Destructive Correlated Double Sampling (NDCDS) readout. The opening of the well doping comprises of three parts: lower one 694, middle one 695, and upper one 694. The reason why the lower and upper parts are similarly numbered as 694 is that the layered structure therein is identical. As depicted in
The source and drain contact dopings 921, 923, 922, and 924 may be connected separately to column wise lines, and the gates 782, 981, 982, 983, 1083, 1084, 1085 separately to row wise lines. In case it is assumed that the voltage span is 3.3 V, the first conductivity type is p type, the second conductivity type is n type, and that source current mode readout is utilized, the pixel can be operated for example in the following manner. First the pixel is in integration stage wherein the two main gates 983, 1085 are held at +2.5 V, the extra gates next to the drains 982, 1084 are held at +3.3 V, the extra gates next to the sources 981, 1083 are held e.g. at 0 V (or at +1 V) and the transfer and reset gate 782 is held at 0 V. In general we may say that taken the assumptions above, the following relation holds:
Vrg,i,Ves,i<Vmg,i<Ved,i
where
Vrg,i is the electric potential of the reset and transfer gate during integration,
Ves,i is the electric potential of the source-side extra gate during integration,
Vmg,i is the electric potential of the main gate during integration, and
Ved,i is the electric potential of the drain-side extra gate during integration. Next the signal charges present in the MIG layer of the lower part of the pixel are transferred to the MIG layer of the upper part of the pixel by first connecting e.g. +3.3 V to the source-side extra gate 1083 situated next to the upper main gate 1085, and then +1.5 V to the transfer and reset gate 782. Then the lower main gate 983 and the extra gate next to the drain 982 are connected to 0 V after which the transfer and reset gate is connected back to 0 V. In general we may say that we briefly create the conditions
Vmg,tr,Ved,tr<Vrg,tr
where
Vmg,tr is the electric potential of one main gate during transfer,
Ved,tr is the electric potential of a corresponding drain-side extra gate during transfer, and
Vrg,tr is the electric potential of a reset and transfer gate during transfer,
and subsequently pull the transfer and reset gate back to a lower potential. This way we make those signal charges, which originally accumulated in the MIG layer beneath that particular main gate, favor migrating horizontally within the MIG layer first beneath the reset and transfer gate and then onwards so that they finally join those signal charges that originally accumulated in the MIG layer beneath the main gate of the other transistor in the pixel.
After this the main gate 983 is connected to +2.5 V and the extra gates 981 and 982 are connected to +3.3 V. More generally the electric potential of the main gate in that transistor, beneath which the MIG layer was just emptied of signal charges, is kept at a lower electric potential than any of the immediately adjacent extra gates, and—if the other transistor in the pixel is read—it is kept also lower than the electric potential of the source-side extra gate of the other transistor in the pixel. The last-mentioned is not mandatory; the other transistor could also be kept closed by keeping said extra gate at a low potential. The purpose is in any case to ensure that the emptied MIG layer beneath said main gate also remains empty for a while. Then a first CDS (Correlated Double Sampling) measurement corresponding to an empty MIG is taken by measuring the source current on source contact doping 921.
After an empty-MIG measurement has been performed in the lower transistor of the pixel, the signal charges are transferred from the upper part of the pixel to the lower part by first connecting +1.5 V to the transfer and reset gate 782. Then the upper main gate 1085 and the upper extra gates 1083, 1084 are connected to 0 V after which the transfer and reset gate 782 is connected back to 0 V. The procedure is a mirror image of that above, where signal charge was first transferred from the MIG layer beneath the lower transistor to that beneath the upper, with the minor exception that the amount of signal charge to move now includes all signal charges that accumulated in the pixel during the preceding integration stage—the first signal charge transfer explained above only moved those signal charges that originally accumulated beneath one transistor.
Next the upper main gate 1085 is connected back to +2.5 V and the upper extra gates 1083, 1084 are connected to +3.3 V. Then a second CDS measurement corresponding to the total amount of signal charge present in the pixel is taken by measuring the source current on the source contact doping 921. Simultaneously a first CDS measurement can be made on the upper source contact doping 923. The final CDS readout result on source contact doping 921 is obtained by subtracting the second CDS readout result from the first CDS result.
In case the signal charges are further transferred from the lower part of pixel to the upper part of the pixel one can obtain another CDS readout result. Beneficially, the CDS readout results from the lower and upper part of the pixel are obtained with different gain settings so that two readout results with different sensitivity (ISO value; the acronym ISO comes from the International Organization for Standardization) settings can be provided. By performing multiple such NDCDS readouts one can naturally obtain several readout results that correspond to different ISO settings.
It should be noted that during the charge transfer state the main gate and the extra gates next to may be first connected to 0 V, after which the transfer and reset gate is shortly biased to +1.5 V and back to 0 V before said main gate is brought to +2.5 V and said extra gates are brought to +3.3 V. It should also be noted that the transfer procedures explained here are only examples, and after having read the explanation the person skilled in the art is capable of presenting other procedures where the idea is simply to control the movements of the collected signal charges with suitable potentials of the main gates, extra gates, as well as the transfer and reset gate.
The extra gates are available as very practical selection means: as was briefly suggested earlier, any transistor in any pixel can be kept closed by keeping an extra gate in such transistor at an electric potential (for example: at a sufficiently low electric potential) that causes the channel in said transistor to remain closed. Thus using the extra gates appropriately may enable leaving out pixel-specific selection transistors, which simplifies the structure of the detector.
The reset of the pixel is performed by connecting +0 V to the main gates 983, 1085 as well as to the extra gates 981, 982, 1083, 1084 and by connecting +3.3 V (or e.g. +2.8 V) to the transfer and reset gate 782. In general we may characterize the reset stage so that the electric potential of the reset (and transfer) gate is made so high in relation to the electric potentials of all other gates in the pixel that the resulting electric fields inside the semiconductor material is sufficient to drive all previously accumulated signal charges out of the MIG layer beneath the whole pixel.
One should note that it is also possible to readout two different rows simultaneously for example in source current readout mode by having e.g. the upper extra gate 1083 next to source closed (e.g. at 0 V) in a lower row and the lower extra gate 981 next to source closed in a upper row throughout the readout procedure of the two rows. The same applies also to source follower readout mode. In case drain current readout mode is used then afore described procedure can be utilized for the gates 982 and 1084 (instead of 981 and 1083).
It is important to note that the doping configuration beneath the gates of the pixel-specific selection transistors may be different. For example the pixel-specific selection transistors may have a doping configuration underneath the gate comprising any combination of the following:
first conductivity type well doping 205 (in case the well is not present underneath the gate there must be an opening in the well doping),
layered structure 241, 251, 261 (see
layered structure 842, 852, 862 (see
In this manner one can adjust the threshold voltages of individual selection transistors according to specific needs. In other words, one pixel may comprise at least two selection transistors which have different threshold voltages. For example if the drains of the selection transistors are connected to the extra gates it would be beneficial to have an as small threshold voltage as possible since this facilitates the formation of the artificial source and drain beneath the extra gates. It is also beneficial to make the well extend beneath the selection transistors, since this way there is no risk that signal charges would be inadvertently collected in the MIG layer beneath the selection transistors where they would be of no use to any measurement.
The pixel of
Proper MIG detector/pixel operation necessitates that a reverse bias is applied between the pixel dopings and a first conductivity type first contact which can be first conductivity type contact doping to the well doping (707, 1105), a first conductivity type contact doping contacting an optional first conductivity type backside conductive layer (200), or a first conductivity type contact to a backside first conductivity type accumulation or inversion layer.
Variations and modifications to the exemplary embodiments illustrated so far are possible without parting from the scope of protection defined by the appended claims. In the following we present some examples.
Even if the structures described so far have the extra gates on both sides of the main gate, it is possible to reap at least some of the same advantages by using an extra gate only on the source side or only on the drain side of the main gate. An asymmetric embodiment, in which only one extra gate is used, requires proper relations between the source, drain, and gate potentials that take the asymmetry into account.
Even if the lay-out drawings illustrate the various doping patterns as rectangles, this is only a matter of graphical clarity; it is perfectly possible to utilize the same principles in structures where doping areas have some other shapes, like hexagonal shapes for example. Also mixed embodiments are possible where some of the doping patterns are rectangular while others are triangular, curved, and/or polygonal.
Local variations in the net effective doping of the described layers, like local variations in the net doping of the MIG layer, are possible at various locations and they can be used to shape the electric fields that control the flow of the signal charges within the structure.
It is possible to replace at least some of the planar, essentially two-dimensional layered structures discussed so far with three-dimensional structures, where the three-dimensionality means that some structure has functionally significant changes in its horizontal dimensions at various depths.
Instead of a source current mode readout, other readout mechanisms such as drain current readout and source follower readout can be utilized.
The substrate can be of either conductivity type.
The number of masks used to create the implanted patterns is not limited by the invention. In the description above we have pointed out that for example the doping enhancements in a number of stacked layers may be produced with the same mask, but different masks could also be used.
A buried channel improves the operation of the artificial source and drain, since the gaps between the main gate and the extra gates can be larger than if no buried channel is used. The reason for this is that in case there is a buried channel, the threshold voltage beneath the gap is smaller than directly beneath the gates. If the buried channel was missing, the threshold voltage beneath the gaps would be larger than beneath the gates.
Claims
1. A semiconductor radiation detector device comprising at least one pixel, wherein the at least one pixel comprises a semiconductor substrate (100) and on one surface of the substrate in the following order: wherein the device further comprises a first conductivity type first contact, said pixel voltage being defined as a potential difference between one of the pixel dopings and the first conductivity type first contact, and a main gate (983) the location of which corresponds at least partly to the location of a channel between said source and said drain, wherein:
- a first layer (241) of semiconductor of second conductivity type, hereinafter the MIG layer,
- a barrier layer (251) of semiconductor of first conductivity type, configured to form a potential energy barrier for signal charges accumulated in said MIG layer during operation of the device,
- pixel dopings (921, 922, 1111, 1112, 121, 122) of semiconductor of the second conductivity type, which pixel dopings are adapted to be coupled to at least one pixel voltage in order to create a source and a drain of a pixel-specific transistor;
- the at least one pixel further comprises at least one extra gate (981, 982) next to the main gate (983) and the location of the at least one extra gate (981, 982) corresponds at least partly to the location of a channel between said source and said drain and wherein the at least one extra gate (981, 982) is external to said semiconductor material of the first conductivity type and the second conductivity type.
2. The semiconductor radiation detector device according to claim 1, comprising two extra gates, the location of a first extra gate is towards said source from the main gate, and the location of the other extra gate is towards said drain from the main gate.
3. The semiconductor radiation detector device according to claim 2, wherein each extra gate is located above a corresponding MIG border region at which a part of said channel is vertically aligned with an edge of said MIG layer.
4. The semiconductor radiation detector device according to claim 1, wherein each extra gate is located above a corresponding MIG border region at which a part of said channel is vertically aligned with an edge of said MIG layer.
5. The semiconductor radiation detector device according to claim 1, wherein said channel goes through a buried channel layer that connects said source and said drain on an opposite side of said barrier layer than said MIG layer.
6. The semiconductor radiation detector device according to claim 1, comprising electrically insulating material that separates said main gate and said extra gate or extra gates from said channel.
7. The semiconductor radiation detector device according to claim 6, wherein a common layer of electrically insulating material encapsulates both said main gate and said extra gate or extra gates.
8. The semiconductor radiation detector device according to claim 1, comprising in said MIG layer a region the net doping of which is higher than the net doping of the remaining MIG layer around said region, wherein said region is vertically aligned with said main gate.
9. The semiconductor radiation detector device according to claim 1, comprising a reset gate (682, 782) underneath of which the doping of the MIG layer (842) and barrier layer (852) is weaker than underneath the main gate (983).
10. The semiconductor radiation detector device according to claim 9, wherein said reset gate (682) is horizontally displaced from said main gate (181), and wherein both said reset gate (682) and said main gate (181) are located above a gap that separates said source (111) and said drain (112).
11. The semiconductor radiation detector device according to claim 9, wherein:
- said field-effect transistor is a first field-effect transistor of a pixel in the device, which pixel comprises also a second field-effect transistor that comprises a second source and a second drain,
- said reset gate is simultaneously a transfer gate that is located above a gap that separates the field-effect transistors of the pixel.
12. The semiconductor radiation detector device according to claim 1, comprising at least two pixel-specific selection transistors which have different threshold voltages.
13. A semiconductor radiation detector device comprising at least one pixel, wherein the at least one pixel comprises a semiconductor substrate and on one surface of the substrate the semiconductor radiation detector comprises: wherein:
- a first conductivity type well doping,
- a second conductivity type source doping and a second conductivity type drain doping inside said first conductivity type well doping,
- an opening in the first conductivity type well doping located in between said source doping and said drain doping,
- a first layer of semiconductor of second conductivity type, hereinafter the MIG layer, said MIG layer located in said opening of the first conductivity type well doping,
- a barrier layer of a semiconductor of first conductivity type arranged directly on the MIG layer in between the MIG layer and said one surface of the substrate and located in said opening of the first conductivity type well doping, said barrier layer configured to form a potential energy barrier for signal charges accumulated in said MIG layer during operation of the semiconductor radiation detector device,
- a channel between said source and said drain as well as between said one surface and said barrier layer, said channel carrying charges of said second conductivity type,
- a main gate external to the semiconductor substrate and located in between said source doping and said drain doping as well as on said opening in the first conductivity type well doping above said channel,
- the at least one pixel further comprises at least one extra gate external to the semiconductor substrate and located in between the main gate and the second conductivity type source doping or drain doping wherein the at least one extra gate is located above a boundary of said well doping and said opening, and wherein the at least one extra gate is adapted to be coupled to a potential such that the channel resistance is lower beneath the at least one extra gate than beneath the main gate such as to create inside the semiconductor substrate underneath the extra gate: an artificial source if the extra gate is located in between the second conductivity type source doping and the main gate, or an artificial drain if the extra gate is located in between the second conductivity type drain doping and the main gate.
14. The semiconductor radiation detector device according to claim 13, wherein the semiconductor radiation detector device comprises two extra gates, the location of a first extra gate is in between the second conductivity type source doping and the main gate, and the location of the other extra gate is in between the second conductivity type drain doping and the main gate.
15. The semiconductor radiation detector device according to claim 13, wherein a buried channel layer of semiconductor of second conductivity type is arranged directly on said barrier layer in between the barrier layer and said one surface of the substrate and located in said opening of the first conductivity type well doping, and wherein said channel goes through said buried channel layer.
16. The semiconductor radiation detector device according to claim 13, comprising electrically insulating material that separates said main gate and said extra gate or extra gates from said channel.
17. The semiconductor radiation detector device according to claim 13, wherein a common layer of electrically insulating material encapsulates both said main gate and said extra gate or extra gates.
18. The semiconductor radiation detector device according to claim 13, comprising in said MIG layer a region a net doping of which is higher than a net doping of the remaining MIG layer around said region, wherein said region is vertically aligned with said main gate.
19. The semiconductor radiation detector device according to claim 13, comprising next to said main gate on said opening of the first conductivity type well doping a reset gate underneath of which the doping of the MIG layer and barrier layer is weaker than underneath the main gate.
20. The semiconductor radiation detector device according to claim 19, wherein said second conductivity type source doping, said second conductivity type drain doping and said main gate correspond to a first field-effect transistor, and wherein the semiconductor radiation detector device further comprises a second field-effect transistor comprising a second source, a second drain and a second main gate, said second main gate located in said opening of the first conductivity type well doping
- said reset gate is located in between said main gate and said second main gate and said reset gate acting also as a transfer gate.
21. The semiconductor radiation detector device according to claim 13, comprising at least two pixel-specific selection transistors having different threshold voltages.
22. A semiconductor radiation detector device comprising at least one pixel, wherein the at least one pixel comprises a semiconductor substrate and on one surface of the substrate the semiconductor radiation detector comprises: wherein:
- a first conductivity type well doping,
- a second conductivity type source doping and a second conductivity type drain doping inside said first conductivity type well doping,
- an opening in the first conductivity type well doping located in between said source doping and said drain doping,
- a first layer of semiconductor of second conductivity type, hereinafter the MIG layer, said MIG layer located in said opening of the first conductivity type well doping,
- a barrier layer of a semiconductor of first conductivity type arranged directly on the MIG layer in between the MIG layer and said one surface of the substrate and located in said opening of the first conductivity type well doping, said barrier layer configured to form a potential energy barrier for signal charges accumulated in said MIG layer during operation of the semiconductor radiation detector device,
- a channel between said source and said drain as well as between said one surface and said barrier layer, said channel carrying charges of said second conductivity type,
- a main gate external to the semiconductor substrate and located in between said source doping and said drain doping as well as on said opening in the first conductivity type well doping above said channel,
- the at least one pixel further comprises next to said main gate on said opening of the first conductivity type well doping a reset gate underneath of which the doping of the MIG layer and barrier layer is weaker than underneath the main gate.
23. The semiconductor radiation detector device according to claim 22, wherein a buried channel layer of semiconductor of second conductivity type is arranged directly on said barrier layer in between the barrier layer and said one surface of the substrate and located in said opening of the first conductivity type well doping, and wherein said channel goes through said buried channel layer.
24. The semiconductor radiation detector device according to claim 22, comprising at least one extra gate external to the semiconductor substrate and located in between the main gate and the second conductivity type source doping or drain doping wherein the at least one extra gate is located above a boundary of said well doping and said opening, and wherein the at least one extra gate is adapted to be coupled to a potential such that the channel resistance is lower beneath the at least one extra gate than beneath the main gate such as to create inside the semiconductor substrate underneath the extra gate:
- an artificial source if the extra gate is located in between the second conductivity type source doping and the main gate, or
- an artificial drain if the extra gate is located in between the second conductivity type drain doping and the main gate.
25. The semiconductor radiation detector device according to claim 24, wherein the semiconductor radiation detector device comprises two extra gates, the location of a first extra gate is in between the second conductivity type source doping and the main gate, and the location of the other extra gate is in between the second conductivity type drain doping and the main gate.
26. The semiconductor radiation detector device according to claim 22, comprising in said MIG layer a region a net doping of which is higher than a net doping of the remaining MIG layer around said region, wherein said region is vertically aligned with said main gate.
27. The semiconductor radiation detector device according to claim 22, wherein said second conductivity type source doping, said second conductivity type drain doping and said main gate correspond to a first field-effect transistor, and wherein the semiconductor radiation detector device further comprises a second field-effect transistor comprising a second source, a second drain and a second main gate, said second main gate located in said opening of the first conductivity type well doping:
- said reset gate is located in between said main gate and said second main gate and said reset gate acting also as a transfer gate.
28. The semiconductor radiation detector device according to claim 22, comprising at least two pixel-specific selection transistors having different threshold voltages.
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Type: Grant
Filed: Sep 16, 2020
Date of Patent: Oct 17, 2023
Inventor: Artto Aurola (Espoo)
Primary Examiner: Minh Nguyen
Application Number: 17/022,935
International Classification: H01L 27/146 (20060101); H01L 31/113 (20060101);