Abstract: A method and apparatus for reducing the number of stages for measuring first and second switching speeds for PD/SOI transistors uses an inverter circuit which includes: a p-channel body-tied transistor; an n-channel body-tied transistor, coupled at their drains and gates; and a first and a second group of components tied to the bodies of the transistors. The first group restores body potentials for the transistors if the inverter circuit belongs to an even numbered stage of a ring oscillator. The second group provides body potentials for the transistors if the inverter circuit belongs to an odd numbered stage. After each transition of a waveform, the body potentials for the PD/SOI transistors are restored to the original potentials as stored in the capacitors. In this manner, a much smaller ring oscillator with fewer number of stages may be used to accurately measure the first and second switching speeds.

Abstract: A method and circuitry are provided for reducing duty cycle distortion in differential solid state delay lines. The differential solid state delay lines of the present invention include a plurality of delay line cells or stages connected in series. Because there may be asymmetry associated with the physical layout of each individual delay line cell or stage, it is advantageous to cross-connect every x stage of an n-stage delay line. Method, integrated circuit, electronic system and substrate embodiments including the differential solid state delay lines are also disclosed.

Abstract: In order to generate an output signal delayed compared to an input signal and with a defined mark-to-space ratio, it is useful to produce at least first and second intermediate signals delayed differently with respect to the input signal and to combine them to form the output signal so that a rising (or negative) edge of the first intermediate signal determines a rising edge of the output signal, and a rising (or negative) edge of the second intermediate signal determines a falling edge of the output signal. In particular a plurality of successive versions of an input timing signal delayed by an equal amount can be generated with a mark-to-space ratio of 50%.

Abstract: An adjustable filter, particularly for use as an antialiasing filter in digital telecommunications networks, includes adjustable capacitors which determine frequency response for the purpose of accurate alignment with a particular cut-off frequency. The active filter includes, in line with the invention, a control device with a measuring device for ascertaining the actual cut-off frequency of the filter. On the basis of the ascertained actual cut-off frequency of the filter and the information about the nominal cut-off frequency which is to be set, an adjustment parameter for the adjustable capacitor is selected from a memory arrangement. This adjustment parameter is used to adjust the adjustable capacitor such that the desired nominal cut-off frequency is obtained and, at the same time, the alignment is performed to achieve the nominal cut-off frequency with sufficient accuracy.

Abstract: A Phase Locked Loop (PLL) that has a substantially constant gain over a wide frequency range. The frequency range over which the PLL operates is divided into a number of frequency sub-ranges. The circuit includes a mechanism for adjusting the loop gain profile as the PLL moves from one frequency sub-range to another. When the PLL switches to a new frequency sub-range, the loop gain profile is adjusted to a pre-established value. Changes of frequency within each sub-range are then accomplished with the loop gain varying within a pre-established range.

Abstract: A frequency converter converts a first current signal having a first frequency into a second current signal having a second frequency different fro the first frequency. The frequency converter includes an adder and a switching circuit. The adder adds the first current signal and a reference current signal to output a third current signal. The switching circuit passes only that portion of the third current signal larger in magnitude than a threshold current to output the second current signal.

Abstract: Systems, methodologies, media, and other embodiments associated with making a frequency change through frequency synthesis and digital selection of out-of-phase synthesized signals are described. One exemplary system embodiment includes a locked loop logic (e.g., phase locked, delay locked) that may receive a reference clock signal, process the reference clock signal into signals with different phases, and make those signals available to a selection logic. The exemplary system may also include a state logic that stores frequency divisors that facilitate selecting and tracking output signals provided by the selection logic. The exemplary system may also include a phase logic that stores output signal phase data associated with computing, describing, and/or selecting an output signal.

Abstract: It is difficult to optimize the timing of the forward and reverse direction for high frequency bi-directional digital signals. Therefore, a digital system is provided that improves the adjustability of the timing by the emission of an additional clock pulse, together with the output clock pulse for the receiver and the feedback clock pulse for the PLL. The additional clock pulse is re-circulated using a delay line and is used to set the clock pulse of the reverse direction signals.

Abstract: An oscillator includes phase frequency detectors, each detecting the phase difference between two input signals (output signal and external reference signal) and outputting a control command signal for controlling the output signal to achieve a desired frequency on the basis of the phase difference. A plurality of ICs, each including a phase frequency detector, frequency dividers, a charge pump, and a lock detection circuit, is operated in parallel. A composite control command signal generated by combining outputs of the phase frequency detectors is output via a loop filter to a voltage-controlled oscillator. Whether phase noise is reduced sufficiently is determined on the basis of detection results by an amplitude detection circuit for detecting the amplitude of an AC component of the composite control command signal and the lock detection circuits. The phase frequency detectors are repeatedly reactivated until the phase noise is reduced sufficiently.

Abstract: A synchronization circuit for synchronizing low frequency digital circuitry and high frequency digital circuitry. The synchronization circuit produces an ordered series of clocks from the high-frequency digital clock. The clocks have a deterministic time relationship, with at least one clock having a period longer than the timing uncertainty associated with a synchronization signal. The synchronization signal is passed through a chain of latches, each one clocked by one of the divided down clocks with successively higher frequency. These latches align the synchronization signal with the clocks produced by the clock divider, ultimately aligning the synchronization signal with the high frequency clock. This synchronization circuit is described in connection with automatic test equipment used in the manufacture of semiconductor devices.

Abstract: The invention relates to a phase-locked loop circuit (1) in a radio transceiver for the detection of the linear operation of a first voltage controlled oscillator (2). The phase-locked loop circuit also has a frequency divider (8), a reference oscillator (10), a phase detector (12) to compare the phases of the reference oscillator (10) with a divided frequency of the frequency divider (8), and a charge pump (14) connected to the phase detector (12) and is characterized in that the connection (13) between the phase detector (12) and the charge pump (14) has at least one branch-off line (15) connected to at least one filter (22) having an output voltage that is related to the linear operation of the voltage controlled oscillator (2).

Abstract: A PLL circuit in which a phase offset between a reference clock and a feedback clock is reduced. PLL circuit 10 includes a dummy phase comparator 16 that simulates a phase comparator 11 and has a pair of comparison inputs to which the reference clock is input, a dummy charge pump 17 that simulates a charge pump 12 and causes an output voltage thereof to rise or fall based on an up signal or a down signal output from the dummy phase comparator 16, and an amplifier 19 for detecting a difference between the output voltage of the charge pump 12 and the output voltage of the dummy charge pump 17. The PLL circuit controls the pulse widths of up and down signals of both of the phase comparator 11 and the dummy phase comparator 16 based on the output voltage of the amplifier 19.

Abstract: A high-speed, half rate phase detector provides an effective solution to the problem of XOR gate response to the minimum width signal precursors (Q1 and Q2) of a phase signal that indicates a phase difference between a data signal and a clock signal by combining the precursor signals in a multiplexer and combining the multiplexed signal with the data signal in an XOR gate. This affords the transition information in the transitions of the precursor signals, which is significant of phase difference, without requiring the XOR gate to respond to the minimum widths of those pulses.

Abstract: A clock shaping device includes a first clock signal selection portion that selects between a reception clock signal and a back-up clock signal based on a detected loss in the reception clock signal. A second clock signal selection portion selects between a clock signal received from the first clock signal selection portion and a clock signal received from a quartz crystal oscillation circuit based on a detected loss in the back-up clock signal. A voltage controlled oscillation circuit has a frequency that varies with a control voltage being supplied and outputs a feedback loop output signal. A phase comparison portion generates a phase difference signal based on a comparison between the feedback loop output signal and a clock signal outputted from the second clock signal selection portion. A loop filter smoothes the phase difference signal and outputs the phase difference signal in the form of the control voltage.

Abstract: There is provided an input buffer circuit that, in one embodiment, includes an input buffer adapted to draw an operating current, a first buffer enabling circuitry operatively coupled to the input buffer and adapted to provide a first portion of the operating current to the input buffer, and second buffer enabling circuitry operatively coupled to the input buffer and adapted to provide a second portion of the operating current to the input buffer if the input buffer is expecting data, the second buffer enabling circuitry being adapted to be activated by a bias signal that is produced from an enable signal and a CLOCK signal.

Abstract: A PLL circuit that makes a voltage-controlled oscillator converge to a stable state within a short time and generates a clock signal with high stability even when discontinuity occurs in the period of a reference input signal is provided. The PLL circuit has a voltage-controlled oscillator for outputting a clock controlled, a first counter reset by the reference input signal having one period longer than a reference period within a predetermined period for outputting a first signal, a second counter for outputting a second signal, a reset pulse generating circuit for resetting the second counter, a loop filter for holding and outputting the control voltage varied by a phase error signal and a discontinuous input detecting part for detecting the reference input signal input initially after its period becomes longer than the reference period.

Abstract: In a power supply circuit, a main transistor, which transmits power from an input terminal to an output terminal, is controlled so that a detected voltage from an input voltage is consistent with a reference voltage indicating a target voltage. An output current is detected and a limited value of the output current is set so that the limited value increases gradually when the output voltage rises up to the target voltage. The main transistor is controlled so that the output current keeps a value less than or equal to the limited value. This configuration is able to suppress an overshoot of the output voltage, thanks to a gradually raised control of the limited value. Additionally, to avoid the influence of a ringing component of the input voltage, a delay control circuit to give a delay to the start of rise of the output voltage can be provided.

Abstract: A signal processing circuit includes a comparator having a fixed and a variable reference input for detection of a positive quasi-sinusoidal waveform pulse. A signal detection circuit includes a low pass input filter, a voltage input clamp, a variable detection threshold, and a zero crossing detector. The circuit produces an approximately square wave output substantially coinciding with the positive pulse of the quasi-sinusoidal waveform received, from a variable reluctance sensor. The circuit has a positive to negative zero crossing detector armed by a variable threshold of the positive quasi-sinusoidal pulse, thus providing variable noise immunity and a fixed phase relationship between the input and output signal for an input signal having a variable amplitude.

Abstract: A phase selector for selecting a differential output can include two matched transistor circuits. A first transistor circuit can receive a first differential input signal whereas a second transistor circuit can receive a second differential input signal. One of the transistor circuits can be used to dump an output current generated by the first differential input signal to Vdd. The other transistor circuit can be used to steer an output current generated by the second differential input signal to two output lines, thereby providing a differential output signal on the output lines.

Abstract: A position control apparatus includes a reverse displacement calculation unit configured to calculate a reverse displacement that represents an amount of movement made from a preceding reverse point to a current reverse point by an axis that performs a reversing motion; a reversing-time segmenting number number of consecutive occurrences of reversing motions calculation unit configured to compare the reverse displacement to a predetermined value, and, when the reverse displacement is less than the predetermined value, increase a value of a reversing-time segmenting number of consecutive occurrences of reversing motions, which is a coefficient indicating a number of segments per unit time during a reversing motion, and, when the reverse displacement is greater than or equal to the predetermined value, decrease the value of the reversing-time segmenting number number of consecutive occurrences of reversing motions; and a quadrant inversion compensation unit configured to automatically adjust a quadrant inversio