Abstract: Systems and methods can be employed to synchronize devices. One embodiment may include a system that includes an input that receives a synchronization signal having a frequency, and an oscillator that provides a clock signal having a frequency. The oscillator adjusts the frequency of the clock signal based on a comparison of an indication of the frequency for the synchronization signal and a corresponding indication of the frequency for the clock signal.

Abstract: A phase-lock loop generates an output clock signal from an input clock signal. The output clock signal is coupled through a clock tree and is fed back to a phase detector, which compares the phase of the output clock signal to the phase of the input clock signal. The output clock signal is generated by a voltage controlled oscillator having a control input coupled to receive an output from the phase detector, and a frequency multiplier coupled to the output of the voltage controlled oscillator. As a result, the CLKOUT signal generated by the frequency multiplier has a relatively high frequency while the voltage controlled oscillator, by operating at a relatively low frequency, uses relatively little power.

Abstract: Aspects for reducing jitter in a PLL of a high speed serial link include examining at least one parameter related to performance of a voltage controlled oscillator (VCO) in the PLL, and controlling adjustment of a supply voltage to the VCO based on the examining. A regulator control circuit performs the examining and controlling.

Abstract: A compensation circuit and method for compensating for variations in time delay adjustments of synchronizing circuits that synchronize an external clock signal applied to an integrated circuit with internal clock signals generated in the integrated circuit in response to the external clock signal. The time delay relationship between fine and coarse delay circuits of an adjustable delay circuit is adjusted to compensate for variations from an expected time delay relationship.

Abstract: A method for providing a phase-locked loop with reduced spurious tones is provided that includes comparing a reference clock signal to an internal clock signal to generate a first signal. The first signal is sampled based on a sampling clock signal to generate a second signal. The sampling clock signal is reduced with respect to the reference clock signal. The internal clock signal is generated based on the second signal.

Abstract: Delayed locked loop (DLL) circuits and methods using a coarse-fine lock structure which prevent malfunction due to jitter or noise that causes erroneous transitions from a coarse-lock to a fine-lock delay. A phase detector uses two feedback signals to detect a phase of an external clock signal (or reference signal) based on a phase difference between the two feedback signals, thereby enabling a more accurate determination as to when to transition from a coarse-lock to a fine-lock delay. The phase difference of the two feedback signals can be regulated by using frequency information to set a phase difference between the first and second feedback signals to renders the detection process more robust against noise or jitter over a wide frequency band from a low frequency to a high frequency, for determining when to transition from the coarse-lock to the fine-lock.

Abstract: A circuit for establishing frequency and phase alignment of clock signals across a domain of analog blocks coupled in a single integrated circuit. Different analog functions are implemented by selectively and electrically coupling different combinations of analog blocks. The analog blocks may be arrayed in a number of columns. The circuit is coupled to the analog blocks to supply a synchronized clock signal to all of the analog blocks in a combination of blocks, even when the blocks are in different columns. The circuit allows the frequency of the clock signal to be changed dynamically depending on the analog function to be achieved. The circuit also establishes phase alignment when a frequency change occurs.

Abstract: A phase locked loop with fast tune time and low phase noise contains a fast filter and a slow filter connected to a phase detector. The slow filter filters an error signal with a narrow bandwidth and provides a slow filter tune voltage. An integrator is connected to the slow filter for integrating the slow filter tune voltage and providing a tune voltage to a VCO. The integrator has a capacitor and operational amplifier. The fast filter filters and amplifies the error signal with a wide bandwidth and high gain to provide a fast filter tune voltage. A diode is connected to the fast filter output and to a non-inverting input of the operational amplifier. The diode is forward biased when the fast filter tune voltage is sufficient thereby causing an inverting input of the operational amplifier to change to the same level to rapidly change capacitor charge.

Abstract: A high-frequency oscillator that enables a plurality of frequency signals to be output. The high-frequency oscillator outputs in parallel a plurality of frequency components from within a frequency spectrum of an oscillation output of a crystal oscillator, selects one or a plurality of frequency components from among the plurality of frequency components, and outputs the selected components as high-frequency outputs. In this way, a plurality of high-frequency signals can be obtained from one crystal oscillator.

Abstract: Systems and methods for measuring the characteristics of voltage controlled oscillators within these circuits and initializing the circuits without coupling circuitry to the voltage control node that could introduce noise at this node. One embodiment includes a PLL circuit having a charge pump and control circuitry for driving the charge pump, where the control circuitry is configured to provide “up” and “down” signals to the charge pump in a normal operational mode or a test/initialization mode. In the normal mode, the control circuitry passes signals received from a phase frequency detector through to the charge pump as the up and down signals. In the test/initialization mode, the control circuitry overrides at least one of the signals received from the phase frequency detector to drive the charge pump to generate a selectable test voltage which is used by a voltage controlled oscillator to generate an output signal at a corresponding frequency.

Abstract: Digital duty cycle correction circuits are provided including a duty cycle detector circuit configured to generate first and second control values associated with a first internal clock signal and a second internal clock signal, respectively. A comparator circuit is also provided and is configured to compare the first control value to the second control value and provide a comparison result. A counter circuit is configured to perform an addition and/or a subtraction operation responsive to the comparison result to provide a digital code. A digital to analog converter is configured to generate third and fourth control values responsive to the digital code. Finally, a duty cycle corrector circuit is configured to receive first and second external clock signals and the first through fourth control values and generate the first and second internal clock signals having a corrected duty cycle.

Abstract: A semiconductor integrated circuit having a built-in PLL circuit which has two charge pump circuits for charging and discharging capacitive elements of a loop filter in response to signals generated by a phase comparator circuit. One of the two charge pump circuits has current sources which generate current values smaller than those generated by current sources of the other charge pump circuit. The loop filter has a first capacitive element connected to a charge/discharge node, and a second capacitive element connected to the charge/discharge node through a resistive element. The first capacitive element is charged and discharged by the one charge pump circuit, while the second capacitive element is charged and discharged by the other charge pump circuit. A charging current source of the one charge pump circuit operates simultaneously with a discharging current source of the other charge pump circuit, i.e., the charge pump circuits operate in opposite phase.

Abstract: A delay-locked loop circuit may include a frequency doubler for increasing a frequency of a clock signal and a frequency divider for decreasing the frequency of the clock signal. The delay-locked loop circuit can be selectively operated in a low frequency and a high frequency by the frequency doubler and the frequency divider.

Abstract: A circuit for changing clocks includes a clock generating circuit which generates an output clock signal by controlling a frequency of an original clock signal, and a control circuit which controls the clock generating circuit in response to an operation mode change signal indicative of a change from a first operation mode to a second operation mode of an external circuit operating based on the output clock signal, thereby changing the output clock signal from a first frequency corresponding to the first operation mode to an intervening frequency and then from the intervening frequency to a second frequency corresponding to the second operation mode, the intervening frequency having a frequency between the first frequency and the third frequency.

Abstract: The present invention provides a communication semiconductor integrated circuit wherein a first control voltage for a voltage-controlled oscillator circuit is controlled based on a feedback signal sent from a PLL loop to generate a carrier frequency signal used as a carrier, and under the generation of the carrier frequency signal, a second control voltage for the voltage-controlled oscillator circuit is controlled based on the output of a DA converter circuit for DA-converting a code generated based on transmit data to thereby frequency-modulate an oscillation signal. The communication semiconductor integrated circuit is provided with a frequency adjustment/control circuit which measures the frequency of an oscillation output of the voltage-controlled oscillator circuit and adjusts a reference current value of the DA converter circuit according to the difference between the measured value and a target value to thereby correct the frequency.

Abstract: Input conversion noises of a filter circuit are reduced. The circuit has plural circuit arrangements obtained by dividing the filter circuit so as to include at least one voltage controlled current source, and at least one circuit arrangement is an amplification circuit having an amplifying function for amplifying an input signal to the filter circuit at a set amplification factor. The amplification element circuit has: a loop circuit constructed by plural intra-loop voltage controlled current sources in which mutual conductance values have a predetermined corresponding relation; and a corresponding capacitor connected to a node in the loop circuit and having a capacitance depending on the corresponding relation so as to set a potential at the node to a predetermined potential corresponding to the amplification factor, and amplification element circuit has an electric nature which is independent of the amplification factor when seeing from the input side of the filter circuit.

Abstract: A clock duty cycle correction circuit. The duty cycle correction circuit is provided at a receiver in a clock distribution network to correct a duty cycle of a distributed clock signal.

Abstract: A phase synchronous multiple LC tank oscillator includes a plurality of oscillator stages that are configured to oscillate synchronously. The phase of each of the plurality of oscillator stages is substantially the same and the plurality of oscillators are inductively coupled. The synchronous oscillation is substantially caused by magnetic coupling. The oscillator stages may be electrically coupled during a first time period and the electrical coupling and disconnected or reduced during a second time period.

Abstract: A cluster of processing systems is provided wherein each processing system is set to operate at a unique operating frequency. Each unique frequency is set to differ from each other by at least a predetermined frequency differential or bandwidth. When clustered, the radiated emissions will not add. Rather, the RF energy is distributed over the predetermined frequency bandwidth and in so doing achieve a reduction of measured RF energy at any singular frequency. By using RF energy dispersal in systems consisting of aggregated processing elements as subsystems, the need for special or additional RF shielding is precluded. Current design and manufacturing techniques can continue to be used. Thus, reducing the overall cost of implementing aggregated systems.

Abstract: A digital adjustable chip oscillator comprises a voltage control oscillator, a reference voltage circuit, a voltage regulation circuit, a digital tuning circuit, a frequency detector and a programmable controller. The oscillator generates an oscillation signal and receives a control voltage and an operating voltage from the voltage regulation circuit and the reference voltage circuit to stabilize and adjust the frequency of oscillation signal. The digital tuning circuit receives a digital code stored in a programmable memory to adjust the control voltage. The frequency detector detects and compares the frequency of oscillation signal with a first and second frequency, wherein when the frequency of the oscillation signal lies between the first and second frequency, the frequency detector outputs a high voltage signal and otherwise the frequency detector outputs a low voltage signal. The programmable controller receives the high voltage signal to stop a programmable counter to acquire the digital code.