Abstract: A circuit relates to phase and frequency-locked loop circuits (PLL and FLL circuits) with a controllable tracking oscillator whose signal phase relationship or frequency, respectively, is influenced by an external parameter, a reference oscillator, as well as a phase or frequency comparator, the output signal of which is used to control the tracking oscillator in such a way that any phase or frequency errors are reduced. A circuit provides for an element for the measurement of the external parameter (such as a microprocessor) which is capable of receiving a signal representing the output signal of the phase or frequency comparator, and convert it into a measurement value that represents the present value of the external parameter. This external parameter can, for example, represent the ambient temperature or the supply voltage of the tracking oscillator.

Abstract: A clock signal generator, which requires no clock selection pin includes a multiplexer to which external and internal clocks are applied. The external clock is further coupled directly and via an inverting delay to a logic circuit, the output of which controls a switching device connected across a capacitor. The capacitor is coupled to a current source and to a comparator that is coupled to a reference voltage. The comparator output serves as the select control for the multiplexer. The switching device repeatedly discharges the capacitor in response to the external clock signal, but otherwise allows the capacitor to be charged by the current source. The external clock signal is coupled to the output of the multiplexer, as long as the capacitor is repeatedly discharged by the external clock signal at a frequency sufficient to maintain the voltage across the capacitor less than the reference voltage.

Abstract: A new Delay Locked Loop (DLL) circuit is interoperable with products having different applications by controlling the count of a DLL circuit according to the operating clock frequency. Therefore, the products having different applications can be manufactured in the same manufacturing processes and test processes. The DLL circuit includes: a clock buffer for receiving an external clock signal; a first frequency divider for dividing the buffered clock signal; a phase detector for detecting phase error; a DLL controller for generating shift-control signals; a delay line for locking between an internal clock signal and an external clock signal; a second frequency divider for dividing the internal clock signal; and a replica unit for modeling tAC path.

Abstract: A reference voltage is moved dynamically towards a voltage level of the last received value. The movement takes place over a predetermined fraction of a bit-time. The amount of movement is limited so that successive logical values don't result in an unusable reference voltage level. When the output of a receiver changes, a state machine sequences the selection of analog reference voltage inputs to a multiplexer to move an output reference voltage towards a steady-state signal voltage level for the value that was just received. When the sequence is complete, the state machine keeps the last value selected on the output until the output of the receiver changes value.

Abstract: A voltage controlled oscillator includes N (N is an integer equal to or more than 2) inversion-type differential amplifiers and a level converter. The N (N is an integer equal to or more than 2) inversion-type differential amplifiers are connected in a loop such that each of output signals outputted from one of the N inversion-type differential amplifiers has an opposite polarity to a corresponding one of output signals outputted from the next one of the N inversion-type differential amplifiers. The level converter is connected to one of the N inversion-type differential amplifiers as a last inversion-type differential amplifier to generate an oscillation signal from the output signals outputted from the last inversion-type differential amplifier. Each of the N inversion-type differential amplifiers operates in response to a predetermined voltage and a control voltage.

Abstract: A correction circuit for generating a control signal for correcting a characteristic change of a first transistor includes a control signal adjusting section including a constant voltage reduction element for determining either one of a maximum voltage and a minimum voltage of the control signal and a second transistor for determining a characteristic of the control signal, a gate electrode of the second transistor receiving a prescribed voltage; and a resistor section including two types of resistor elements having resistance values of different temperature dependency characteristics from each other, the resistor elements being connected in series. The constant voltage reduction element, the second transistor, and the resistor section are connected in series between a supply terminal and a ground terminal. The control signal is output from a connection point between the control signal adjusting section and the resistor section.

Abstract: A method for operating a master latch and a slave latch coupled to the master latch includes the steps of attempting to operate the master latch and the slave latch in a first mode in which (1) the master latch is held in an open condition; and (2) the slave latch is pulsed so as to latch data passed through the open master latch. If the master latch and the slave latch do not operate in the first mode, the master latch and the slave latch are operated in a second mode in which (1) a first clock signal is employed to latch data with the master latch; and (2) a second clock signal is employed to latch data latched by the master latch with the slave latch.

Abstract: DLL integrated circuits include least one delay element associated with the generation of an internal clock signal and a control circuit that is configured to periodically adjust a delay of said at least one delay element in response to a first clock signal (CLK). The control circuit is further configured to block at least one periodic adjustment of the delay of the at least one delay element in response to detecting excessive jitter with CLK. This DLL may be configured to block at least one periodic adjustment to a phase of an internal clock signal (ICLK) in response to detecting an excessive phase difference between the first clock signal (CLK) and a feedback clock signal (FCLK) derived from the internal clock signal (ICLK).

Abstract: A method for automatically calibrating a phase locked loop (PLL) system includes estimating a frequency value of an input signal applied to the system. Based on the estimated frequency value, a driving signal is generated for a plurality of internal switches in the PLL system. A PLL system may also implement this automatic calibration method.

Abstract: A change pump circuit included in a clock synchronizer is capable of preventing occurrence of an offset even though an output potential of a loop filter is varied, and includes a control circuit controlling a gate potential of a transistor such that predetermined constant current flows through the transistor connected between the line of a power-supply potential and an output node of the loop filter by a switching circuit, based on the output potential of the loop filter.

Abstract: A compensation circuit and method for compensating for variations in time delay adjustments of synchronizing circuits that synchronize an external clock signal applied to an integrated circuit with internal clock signals generated in the integrated circuit in response to the external clock signal. The time delay relationship between fine and coarse delay circuits of an adjustable delay circuit is adjusted to compensate for variations from an expected time delay relationship.

Abstract: A DLL circuit includes: an output dummy circuit having a prescribed propagation delay; a first delay element delaying a reference clock in accordance with a control signal and supplying the delayed signal to the output dummy circuit; a phase determination circuit comparing the phases of the reference clock and a feedback signal and supplying a control signal altering the delay amount of the first delay element; a second delay element receiving either the reference clock or the feedback signal, to serve as the trigger of the phase comparison operation, and delaying this signal by a delay amount; and a latch circuit latching the other signal not serving as the trigger of the phase comparison operation in synchronization with the rising edge of the output signal of the second delay element and supplying a signal turning on or off the input of the other signal to the phase determination circuit.

Abstract: When two sine-wave signals in quadrature, the integral of the output is equal to zero. Conversely, when an in-phase signal is inputted as one multiplicand and the output is set to zero, a quadrature signal is derived from the second multiplicand automatically. Any analog multiplier can be used. Examples using differential pair and conductance multiplier have been demonstrated. The multiplier operates over a wideband, and the in phase and quadrature signals can be equalized automatically.

Abstract: A circuit includes a first node having a first variable voltage and a second node having a second variable voltage. A clock signal generates the first variable and second variable voltages. A first transistor is coupled to the first node and provides a first current responsive to a first control voltage being applied to the first transistor gate. A second transistor is coupled to the second node and provides a second current responsive to a second control voltage being applied to the second transistor gate. A first control circuit is coupled to the first transistor gate and the second node. The first control circuit provides the first control voltage responsive to the first variable voltage. A second control circuit is coupled to the second transistor gate and the first node. The second control circuit provides the second control voltage responsive to the second variable voltage. The first and second currents are used to provide a duty cycle correction signal.

Abstract: An integrated low noise amplifier includes an on-chip balun, a line impedance matching circuit and an on-chip differential amplifier. The on-chip balun is operably coupled to convert a single ended signal into a differential signal. The line impedance matching circuit is operably coupled to the primary of the on-chip balun to provide impedance matching for a line carrying the single ended signal. The on-chip differential amplifier is operably coupled to amplify the differential signal and is impedance matched to the secondary of the on-chip balun.

Abstract: A system and method to extract a threshold voltage for a MOSFET include first and second stages, which include inputs that receive functionally related input currents, are connected to each other. The first stage includes a second input that is coupled to a corresponding input of the second stage through part of a voltage divider. Another part of the voltage divider is coupled between an internal gate node and the input of the second stage that receives the respective input current. The input of the second stage that receives the respective input current also provides an output voltage substantially equal to the threshold voltage for one or both of the MOSFETs.

Abstract: A sample-and-hold amplifier circuit has a switch, provided between an operational amplifier stage and an inverting amplifier stage, for connecting or cutting off the connection of the operational amplifier stage and the inverting amplifier stage. During the first operation phase (&phgr;1), the first and second switches are switched to the &phgr;1 side, the third switch is conductive, and the switch for connecting or cutting off the connection is nonconductive. Thus, sampling can be carried out so that first and second capacitors are charged by predetermined electrical charges. During the second operation phase (&phgr;2), the first and second switches are switched to the &phgr;2 side, the third switch is nonconductive, and the switch for connecting or cutting off the connection is conductive.

Abstract: A phase-locked loop having a phase detector for receiving a feedback signal and an input clock signal having an input clock frequency. The phase detector outputs or produces a phase error signal indicative of a comparison between the input clock signal and the feedback signal. The phase-locked loop also has a loop filter coupled to the phase detector to receive the phase error signal and to output an error correction signal which includes an error correction frequency having a value ranging from about [input clock frequency−(input clock frequency×about 0.00015)] to about [input clock frequency+(input clock frequency×about 0.00015)]. A voltage controlled oscillator is coupled to the loop filter for receiving the error correction signal and to generate an output signal of the phase-locked loop which is indicative of the feedback signal.

Abstract: A low-power phase detector with differential output may comprise a control signal generator. In one embodiment, two cyclic waveforms whose phase relationship is to be measured may be input to a control signal generator. The control signal generator may output a first control signal corresponding to the first cyclic waveform such that the control signal is de-asserted at a specific point with respect to the first cyclic waveform. For example, the control signal may be de-asserted corresponding to the rising edge of the first cyclic waveform. The control signal generator may also output a second control signal corresponding to the second cyclic waveform such that the control signal is asserted at a specific point with respect to the second cyclic waveform. For example, the control signal may be asserted corresponding to the falling edge of the second cyclic waveform.

Abstract: A method and circuitry are provided for reducing duty cycle distortion in differential solid state delay lines. The differential solid state delay lines of the present invention include a plurality of delay line cells or stages connected in series. Because there may be asymmetry associated with the physical layout of each individual delay line cell or stage, it is advantageous to cross-connect every x stage of an n-stage delay line. Method, integrated circuit, electronic system and substrate embodiments including the differential solid state delay lines are also disclosed.