Abstract: The device for controlling a setup/hold time of an input signal can change a setup/hold time of various control signals applied from an input buffer without physically changing the control device. The device for controlling a setup/hold time of an input signal has transmission gates for performing selectively switching operations according to a decoded test mode control signal, thereby selectively using a signal delay device in driving of drivers to appropriately control the setup/hold time of various control signals applied from a global bus line. Accordingly, the device for controlling a setup/hold time of an input signal can provide a technique which can optimize the setup/hold time at a small cost in comparison with a physical metal option control system.

Abstract: A master DLL circuit (3) generates a first delay signal (CKD) by delaying the master clock signal by a first delay time (T0) and generates a first pulse signal (Smp) having a pulse width (T0) of the first delay time, and generates a first control signal (Scp) which is changed in accordance with the first pulse signal (Smp), and adjusts the first delay time (T0) in accordance with the first control signal (Scp). Each slave DLL circuit (D1 to Dm) delays, by a second delay time (td), a delay internal clock signal, and outputs the delayed delay internal clock signals (CK1 to CKm) which form the multiphase clock signals. Each slave DLL circuit generates a second pulse signal (Ssp) having a pulse width (td) of the second delay time, and generates a second control signal (Scp1) which is changed in accordance with the first and second pulse signals (Smp, Ssp), and adjusts the second delay time (td) in accordance with the second control signal (Scp1), thus reducing a skew value of the multiphase clock signal.

Abstract: A traveling wave device for the combining or splitting of symmetric and asymmetric traveling wave energy includes a feed waveguide for traveling wave energy, the feed waveguide having an input port and a launching port, a reflector for coupling wave energy between the feed waveguide and a final waveguide for the collection and transport of wave energy to or from the reflector. The power combiner has a launching port for symmetrical waves which includes a cylindrical section coaxial to the feed waveguide, and a launching port for asymmetric waves which includes a sawtooth rotated about a central axis.

Abstract: A device responsive to an electromagnetic signal includes a conductor for conducting the electromagnetic signal, a magnetic structure disposed proximate the conductor to enable gyromagnetic interaction between the electromagnetic signal and the magnetic structure and a transducer disposed on the magnetic structure for controlling a domain pattern in the magnetic structure.

Abstract: A delay locked loop circuit has a quantifier for obtaining a measured delay quantity based on a time delay between an external signal and an internal signal. Based on the measured delay quantity, a delay controller controls a correction delay quantity applied to a signal path of the external signal to synchronize the external and internal signals.

Abstract: A DLL circuit having a low jitter in a semiconductor device, includes a delay model unit for compensating a time difference between an external clock signal and an internal clock signals and generating a compensation signal; an input buffer for receiving a reference clock signal and an inverted clock signal, and for outputting a clock signal and an inverted clock signal activated at each edges of the reference clock signal and the inverted clock signal; a phase detection unit for generating a comparison signal by comparing the compensation signal with the inverted clock signal, and for outputting the comparison signal with a normal mode or a fast mode; a control unit for generating a plurality of control signals by receiving the comparison signal, the inverted clock signal and the clock signal; a delay unit for delaying in response to the plurality of control signals; and an output buffer for outputting a delayed clock signal by receiving an output signal of the duty corrector.

Abstract: A latch circuit fetches a setting state of a fuse element. A latch clock generation circuit generates a latch clock based on a cyclic signal (frame signal, for example). The latch circuit cyclically fetches the setting state of the fuse element based on the latch clock. An analog value is adjusted based on the setting state of the fuse element latched by the latch circuit.

Abstract: A method for generating a signal with a frequency equal to a product of a reference frequency and a real number includes providing an output signal from an oscillator, and performing a first integer division of a frequency of the output signal by a first integer divider to obtain a first intermediate signal. A first measurement signal representative of a time difference between the first intermediate signal and a reference signal having the reference frequency is determined. The method further includes generating a first comparison signal derived from the first measurement signal, and generating a second comparison signal dependent on a period of the reference signal, on integer and decimal parts of the real number and on the first integer divider. The first and second comparison signals are compared to obtain an error signal representative of a time difference between a period of a current output signal and the period of the reference signal.

Abstract: A PLL circuit that optimally generates a clock signal with two reference signals having different frequencies. The PLL circuit includes a VCO for generating the clock signal in accordance with a control voltage. A first loop controls the frequency of the clock signal in accordance with a first reference signal. A second loop controls the phase of the clock signal in accordance with a second reference signal, whose cycle is longer than that of the first reference signal. The second loop supplies the VCO with the control voltage at a constant value until the difference between the frequencies of the first reference and clock signals converges to within a predetermined range. Then, the second loop supplies the VCO with a control voltage at a level corresponding to the difference between the phases of the second reference and clock signals.

Abstract: A clock multiplier circuit receives a clock input signal and generates a clock output signal. The clock multiplier circuit generates a number of pulses to be used as the clock output signal, wherein the pulses have a pulsewidth that is independent of the number of pulses generated and independent of the frequency of the clock input signal. The clock multiplier circuit includes an oscillator and a logic circuit which generates a control signal for synchronization of the pulses to the control signal and to mask the pulses after a selected number of pulses have been output as the clock output signal. The clock multiplier circuit causes a number of unmasked pulses to be output as the clock output signal in response to the control signal, while other pulses are masked.

Abstract: Clock doubler circuits and methods use counters to define the positions of the output clock edges. A plurality of counters are each clocked by a count clock relatively much faster than the input clock. A first counter counts for one input clock period, and the counted value is stored. The stored value is divided by two to provide the number of counts in half of the input clock period. The divided value is provided to a second counter that counts from zero to the divided value. Thus, the second counter generates a pulse halfway through the input clock period. Other counters running at the same clock rate can be used to generate pulses at other times in the input clock cycle, as desired. The pulses from the counters are used to provide output clock edges at predetermined times during the input clock cycle.

Abstract: Phased clock generator circuits and methods that use counters to define the desired positions of the phased output clock edges. A plurality of counters are each clocked by a count clock relatively much faster than the input clock. A first counter counts for one input clock period, and the counted value is stored. The stored value is then divided and added to provide the number of counts in various fractions of the input clock period. The divided and/or added values are provided to a second counter that counts from zero and generates various pulses at desired times throughout the input clock period. The pulses from the second counter are used (sometimes in combination with the input clock signal) to provide phased output clock signals at predetermined times during the input clock cycle. Some embodiments include a duty cycle correction feature. In some embodiments, duty cycle correction is optional.

Abstract: Clock multiplier circuits and methods use counters to define the positions of the output clock edges. A plurality of counters are each clocked by a count clock relatively much faster than the input clock. A first counter counts for one input clock period, and the counted value is stored. The stored value is then divided and added to provide the number of counts in various fractions of the input clock period. The divided and/or added values are provided to a second counter that counts from zero and generates various pulses at desired times throughout the input clock period. The pulses from the second counter are used (sometimes in combination with the input clock signal) to provide output clock edges at predetermined times during the input clock cycle.

Abstract: A system for impedance matched switching of an input signal from an input source includes a first switch, such as an FET, for controllably switching the input signal from an input terminal connected to the input source to an output terminal, the switching being controlled according to a control voltage. The system further includes a second switch, such as an FET, for controllably switching a matching impedance between the input terminal and ground according to the control voltage. When the input signal is prevented from passing from the input terminal to the output terminal by the first switch, the input signal passes through the matching impedance, which has an impedance characteristic substantially matched to an impedance characteristic of the input source.

Abstract: A clock extracting part has a first phase comparator circuit, a first up/down counter, a weighting circuit, a charge pump and a low-pass filter forming a voltage value determining part, and a voltage controlled oscillator circuit. A retiming clock generating part has a second up/down counter and a phase switching circuit. Furthermore, a phase adjusting part has a first counter, a second counter, a second phase comparator circuit and a third up/down counter forming a phase adjusting part. A clock data recovery circuit is formed by said clock extracting part, the retiming clock generating part, the phase adjusting part, and a first-in first-out memory part. Thereby, a clock data recovery circuit is obtained, in which jitter transfer characteristics and jitter tolerance satisfy the standards of both the SONET and SDH.

Abstract: A vibrating reed which includes a base; and a vibration arm section formed so as to protrude from this base wherein a through groove is formed in the vibration arm section, and a rigidity reinforcing section is provided in the through groove, and thus the frequency is not decreased and the CI value is not increased.

Abstract: A phase shift control voltage distribution scheme for a phased array utilizes analog voltage-proportional phase shift devices, to which respective input signals are supplied and from which phase-shifted output signals are produced. A voltage supply unit has a plurality of voltage outputs supplying respectively different analog voltages. A switch network coupled between voltage outputs of the multiple voltage supply unit and the voltage control inputs of the plurality of voltage-controlled phase shift elements, is operative to selectively couple any of the different voltages supplied by the multiple voltage supply unit to the voltage control inputs of any of the voltage-controlled phase shift elements.

Abstract: A time base including a resonator (4) and an integrated electronic circuit (3) for driving the resonator into oscillation and for producing, in response to the oscillation, a signal having a determined frequency. The resonator is an integrated micromechanical ring resonator supported above a substrate (2) and adapted to oscillate around an axis of rotation (O) substantially perpendicular to the substrate. The ring resonator includes a free-standing oscillating structure having a plurality of thermally compensating members (65) which are adapted to alter a mass moment of inertia of the free-standing oscillating structure as a function of temperature so as to compensate for the effect of temperature on the resonant frequency of the ring resonator.

Abstract: A comparator with hysteresis which achieves fast switching despite a low current consumption. The comparator comprises a first transistor (M1) and a second transistor (M2) whose gates form the inputs of the comparator. The main current paths of both transistors are connected to each other at one end, with a third transistor (M3) and a fourth transistor (M4) being provided. The gate of the third transistor is connected to the gate of the first transistor and its main current path is circuited between the one end of the main current paths of the first and second transistor and is connected via the main current path of the fourth transistor to the other end of the main current path of the second transistor. The gate of the fourth transistor is connected to the output signal or inverted output signal of the comparator. The comparator in accordance with the invention may be put to use e.g. in an ASK demodulator such as those used in RFID transponders.

Abstract: Circuits and methods align an internal signal with an external signal. A phase lock loop network receives the external signal to generate phase lock loop signals. A programmable ratio decoder provides a code. An alignment unit generates the internal signal based on at least one of the phase lock loop signals. The alignment unit aligns internal signal with the external signal based on the code.