Abstract: The locked frequency of a PLL is used to latch a test signal through various latching devices (flip-flops or the like). Various different delays are selectively applied to the test signal to provide a delayed test signal and the delayed test signal is measured to determine whether the delay in the test signal matches the jitter in the locked frequency of the PLL. When the delay in the test signal matches the jitter in the locked frequency of the PLL, the respective delay of the test-signal is used to determine the effective locked frequency of the PLL.

Abstract: A surface acoustic wave filter apparatus includes extensional-coupling-resonator-mode first through fourth SAW filter devices which are disposed on a piezoelectric substrate. Each SAW filter device includes three interdigital transducers (IDTs) arranged in a SAW propagating direction, and reflectors arranged such that they sandwich the IDTs therebetween. The SAW filter devices have a balanced-to-unbalanced input/output function. The reflectors of the first and second SAW filter devices are different from those of the third and fourth SAW filter devices in at least one of the number, the pitch, the duty, and the thickness of the electrode fingers of the reflectors.

Abstract: An integrated circuit device is discussed that includes a data output driver having two modes of operation for driving a data bus. The output driver includes a circuit to produce a full drive output high signal, a partial drive output high signal, a full drive output low signal and a partial drive output low signal. The output driver is protected against negative voltages on the data bus. The output driver is selectable and adaptable to drive terminated loads and unterminated loads.

Abstract: A clock recovery circuit capable of automatically adjusting the frequency range of a voltage-controlled oscillator (VCO). The clock recovery circuit includes a phase detector, a charge pump, a loop filter, a voltage-controlled oscillator, a frequency counter, and a frequency control unit. The phase detector receives an input signal, such as EFM clock, and a VCO clock and outputs a control signal according to phase differences between the EFM clock and the VCO clock. The charge pump controls the charge action according to the control signal. The loop filter is connected to the charge pump and outputs a voltage signal. The voltage-controlled oscillator receives the voltage signal from the loop filter and outputs the VCO clock. The frequency counter counts the frequency of the VCO clock and outputs an oscillation frequency.

Abstract: A circuit includes an input terminal, an output terminal and a latch. The input terminal receives an input signal. The latch is programmable with a value. The latch communicates the input signal to the output terminal in response to the circuit not being in a sleep mode and in response to the circuit being in the sleep mode, furnishes a second signal to the output terminal indicative of the value.

Abstract: A delay circuit including a delay section having two or more predetermined delay stages is disclosed. Each predetermined delay stage adds a predetermined delay time to an input signal. The delay circuit also includes selecting switch sections. At least one of the selecting switch sections includes: a buffer section for receiving a delayed input signal from one of the delay stages and a selecting section means directly connected to the buffer section for activating the buffer section to establish a delay path, wherein an output signal from the delay path has a desired delay time.

Abstract: Systems and methods are described for a core sync module. A method includes receiving a pair of input clock signals; utilizing a stratum clock state machine to control a multiplexer; utilizing the multiplexer to switch an input of a main clock between each of the pair of input clock signals; inducing a phase build-out activity; and transmitting an output clock signal. An apparatus includes a first input clock digital phase-locked loop; a second input clock digital phase-locked loop; a stratum clock state machine coupled to the first input clock digital phase-locked loop and to the second input clock digital phase-locked loop; and a main clock phase-locked loop coupled to the first input clock digital phase-locked loop, to the second input clock digital phase-locked and to the stratum clock state machine.

Abstract: A low voltage source of input edges is AC coupled to positive and negative edge differentiators. Each differentiator briefly drives ON a corresponding normally OFF switch, the pair of which switches serves as an impulse driver and that may be clamped to symmetrical opposing reference voltages. The bi-stable switch driver responds to a particular polarity impulse driver voltage by applying thereto through a load resistor a percentage of a power supply voltage of opposite polarity. The impulse driver is also coupled to a complementary pair of MOSFET switches that are in series between precise reference voltages of opposing polarities, and whose common junction may be connected to a current determining resistance. The output of the MOSFET switches may be assisted by an auxiliary bi-stable output driver that reduces the amount of load current drawn from those MOSFETS.

Abstract: A novel method and apparatus is presented for reducing the slew rate of transition edges of a digital signal on a node of an integrated circuit by connecting transistors with differing threshold voltages between the node and a voltage source and driving the gates of these transistors with the same driving signal.

Abstract: A semiconductor device includes a clock buffer block for receiving and buffering an external clock signal and then outputting an internal clock in response is a second control signal; a clock enable buffer block, which is enabled by a buffer enable signal, for comparing a reference voltage having a constant potential with a clock enable buffer signal and then generating a first control signal; a clock enable signal timing control block for outputting the second control signal by passing the clock enable signal to the clock buffer block in response to the buffer enable signal or by delaying the clock enable signal for a predetermined time; and a clock enable signal latch block for generating the enable signal after a power-up signal is inputted.

Abstract: A delay circuit generates delayed signals. The delay circuit includes a delay locked loop having an input terminal coupled to a periodic input signal, the delay locked loop generating one or more delayed periodic signals and a control signal for controlling the time delay between the periodic input signal and the delayed periodic signals. The delay circuit also includes a controlled delay circuit for generating one or more delayed periodic signals. The controlled delay circuit has an input terminal for receiving at least one of the delayed periodic signals from the delay locked loop and a delay control terminal coupled to the control signal from the delay locked loop for controlling the time delay between the delayed periodic input signal received from the delay locked loop and the one or more delayed periodic signals generated by the controlled delay circuit.

Abstract: An electronic system with semiconductor components allows electronic circuits with conventional semiconductor components to be used, having minimal supply voltages to guarantee stable operation, lowering said minimum supply voltages. The range of supply voltages of such a circuit for which operation is stable can be extended towards low values by the effect of mutual compensation of the respective behaviors of said semiconductor components in their respective transition regions.

Abstract: A squaring cell combines first and second exponential currents to approximate square law behavior. The exponential currents can be generated by current stacks having pairs of series-connected junctions. The exponential currents can be altered to change the shape of the exponential currents to better approximation true square law behavior. A multiplier combines four exponential currents to approximate a multiplication function. The exponential currents in the multiplier can be generated by current stacks that are cross-connected so as to generate two output currents, the difference of which represents the multiplication of two input signals.

Abstract: A crystal oscillator has a quartz-crystal unit, a first oscillating capacitor connected between a first end of the crystal unit and a reference potential point, a second oscillating capacitor connected between a second end of the crystal unit and the reference potential point, a CMOS inverter connected parallel to the crystal unit, and a feedback resistor connected across the inverter. The crystal oscillator can easily be incorporated into integrated circuits and has an increased variable oscillation frequency range. The crystal oscillator also has an adjustable capacitive assembly having selectable capacitances which is connected parallel to a combined capacitor comprising the first and the second oscillating capacitors.

Abstract: A phase locked loop design uses a diode operatively connected to a loop filter capacitor to control a leakage current of the loop filter capacitor. By positioning a diode in series with the loop filter capacitor, a voltage potential across the loop filter capacitor is reduced, thereby reducing the leakage current of the loop filter capacitor. Moreover, the leakage current of the loop filter capacitor is controlled in that it cannot exceed the current through the diode. Control and reduction of the loop filter capacitor leakage current leads to more reliable and stable phase locked loop behavior.

Abstract: A circuit and method for synchronized clocking of components such as registers. Registers are clocked by individual component clock signals having the same frequency but potentially different phases due to differing propagation delays. Separate component clock signals are received by registers are brought into phase by evaluating the phases of the component clock signals at the registers, and synchronizing the component clock signal of each register to that of the previous register in a sequence.

Abstract: A duty cycle correction (DCC) circuit including first and second clock dividers for dividing ordinary and sub-input clocks. Optional first and second variable delay devices delay the divided clocks. First and second mixers mix an optionally delayed ordinary divided clock and sub-ordinary divided clock, or an ordinary divided clock and an optionally delayed sub-ordinary divided clock. A logic combination device is included to produce a clock at the same frequency as the ordinary and sub-input clocks, with a corrected duty cycle.

Abstract: An operation control signal for an oscillator producing an internal clock signal phase-locked with a basic clock signal is applied to a second internal clock generating circuit. In the second internal clock generating circuit, with reference to the applied operation control signal, a control signal adjusting a phase and/or frequency difference between a synchronization target signal and a second internal clock signal is produced to adjust a phase and/or frequency of the second internal clock signal. A plurality of internal clock signals different in phase and/or frequency can be generated accurately and stably.

Abstract: A time base including a resonator (4) and an integrated electronic circuit (3) for driving the resonator into oscillation and for producing, in response to the oscillation, a signal having a determined frequency. The resonator is an integrated micromechanical ring resonator supported above a substrate (2) and adapted to oscillate in a first oscillation mode. The ring resonator includes a free-standing oscillating structure (6). Electrodes (100, 120; 130, 150) are positioned under the free-standing oscillating structure in such a way as to drive and sense a second oscillation mode in a plane substantially perpendicular to the substrate and having a resonant frequency which is different from the resonant frequency of the first oscillation mode, a frequency difference between the resonant frequencies of both oscillation modes being used for compensating for the effect of temperature on the frequency of the signal produced by the time base.

Abstract: The invention provides a multi-phase oscillator includes a delay loop buffer and plurality of oscillators. The delay loop buffer has N delay units. The oscillator can be a single phase oscillator, a 180° phase difference oscillator or a multiple phase difference oscillator. The N delay units are used to constitute a configuration having 360° phase shift where each delay unit has the same delay time and phase shift. Furthermore, a 180° phase difference oscillator composed of a plurality of inverters and a regenerator can be applied in the multi-phase oscillator.