Abstract: A phase-locked loop with a delay element (DLL) is described which is essentially characterized in that the delay element (3) has a chain of a number n delay units (33n), the outputs (34n) of which are fed to a locking monitoring circuit (4) which determines whether the delay time Tdelay of the delay element (3) lies within a range a*Tperiod<Tdelay<b*Tperiod, where 0.5<a<1 and 1<b<2, and wherein the locking monitoring circuit (4) performs a correction of this delay time when this condition is not met.

Abstract: A loop filter of a compensating phase-locked loop contains capacitors formed from transistors with thin gate oxide dielectric layers. Leakage current leaks through the capacitors. To avoid jitter in the output signal of the phase-locked loop that would otherwise be caused by the leakage current, a leakage compensation circuit is provided. The leakage compensation circuit of a first embodiment replicates the leakage current using a replication capacitor and a current mirror. The voltage across the replication capacitor is proportional to the control voltage of a voltage-controlled oscillator of the compensating phase-locked loop. A second embodiment generates the compensation current by controlling the voltage on the gate of a transistor. The gate voltage depends on charge added and subtracted by a charge pump in addition to the charge pumps in the loop filter. A third embodiment applies a leakage compensation circuit to a delay locked loop.

Abstract: The invention concerns a signal generator comprising a reference signal generator consisting of a microcontroller, a chopping switch, a sensor for sampling, and a comparator for delivering a value based on the difference between a sample signal and a reference signal. The signal generator also is configured to control the chopping switch and designed to deliver to the switch control level(s) which is/are based on the result(s) of said comparison. The invention is characterized in that the microcontroller comprises one or more input(s) receiving the result(s) of the comparison(s), and one or more output(s) through which the microcontroller is configured to deliver control level(s) to the chopping switches. Also, the microcomputer is programmed to update at predetermined times the control level(s) delivered on the basis of the received comparison result(s).

Abstract: A structure and associated method to control spark current in a phase lock loop circuit. The phase lock loop circuit includes a voltage controlled oscillator, a phase comparator circuit, and a charge pump circuit. The voltage controlled oscillator is adapted to provide a first signal comprising a first frequency. The phase comparator is adapted to compare the first signal comprising the first frequency to a reference signal comprising a reference frequency. The phase comparator is further adapted to provide a control signal representing a phase difference between the first signal and the reference signal. The charge pump circuit is adapted to receive the control signal and control the voltage controlled oscillator such that a phase of the first signal equals a phase of the reference signal. The charge pump circuit is further adapted to compensate for a spark current resulting from a switching mode of the control signal.

Abstract: An edge-triggered flip flop includes a clocking portion having first and second transistor stacks that are coupled to first and second storage nodes of a memory element, respectively. In at least one embodiment, a clock signal is applied to an input of at least one transistor in each stack and a delayed and possibly inverted version of the clock signal is applied to an input of at least one other transistor in each stack to clock new data into the memory element.

Abstract: A frequency converter configured to convert a first current signal having a first frequency into a second current signal having a second frequency different from the first frequency is disclosed, which comprises an adder configured to add the first current signal and a predetermined reference current signal to output a third current signal corresponding to the sum of the first current signal and the reference current signal, and a switching circuit configured to pass only that portion of the third current signal which is larger in magnitude than a threshold current to output the second current signal.

Abstract: A DLL circuit includes: an output dummy circuit having a prescribed propagation delay; a first delay element delaying a reference clock in accordance with a control signal and supplying the delayed signal to the output dummy circuit; a phase determination circuit comparing the phases of the reference clock and a feedback signal and supplying a control signal altering the delay amount of the first delay element; a second delay element receiving either the reference clock or the feedback signal, to serve as the trigger of the phase comparison operation, and delaying this signal by a delay amount; and a latch circuit latching the other signal not serving as the trigger of the phase comparison operation in synchronization with the rising edge of the output signal of the second delay element and supplying a signal turning on or off the input of the other signal to the phase determination circuit.

Abstract: An integrated circuit device includes a pin for receiving a DC voltage component signal. The device includes a signal source for applying an AC signal to the pin, a buffer for converting the AC signal into a digital signal, and a digital detector for detecting a frequency of the digital signal and outputting a predetermined detection signal. The predetermined detection signal is activated when the frequency of the digital signal is greater than or equal to a predetermined frequency. The predetermined detection signal is used as a signal for setting predetermined functional modes. The device further includes registers or a differential amplifier and a decoder for generating a plurality of functional mode signals.

Abstract: DLL integrated circuits include least one delay element associated with the generation of an internal clock signal and a control circuit that is configured to periodically adjust a delay of said at least one delay element in response to a first clock signal (CLK). The control circuit is further configured to block at least one periodic adjustment of the delay of the at least one delay element in response to detecting excessive jitter with CLK. This DLL may be configured to block at least one periodic adjustment to a phase of an internal clock signal (ICLK) in response to detecting an excessive phase difference between the first clock signal (CLK) and a feedback clock signal (FCLK) derived from the internal clock signal (ICLK).

Abstract: A level conversion circuit is composed of a level shift circuit for supplying a level-converted signal in the same phase as the input signal and a signal in the reverse phase thereto and a follow-up circuit responsive to the earlier of the output signals of the level shift circuit for generating an output signal, wherein the follow-up circuit consists of an inverter circuit in which two p-channel type MOS transistors and two n-channel type MOS transistors are connected in series between a first voltage terminal and a second voltage terminal, of which one pair is used as input transistors and the remaining pair of transistors are subjected to feedback based on the output signal of the level shift circuit to be quickly responsive to the next variation.

Abstract: A clock distribution network for clock distribution in an integrated circuit (IC) using digital feedback for skew compensation and jitter filtering. In an embodiment, a number of clock processor nodes are distributed throughout the clock distribution network on the IC at respective local clock regions. A master clock generator generates a master clock for distribution to the clock processor nodes, via the clock distribution network, to compensate clock skew and filter clock jitter locally at the respective local clock regions.

Abstract: A method includes receiving a pair of input clock signals; utilizing a stratum clock state machine to control a multiplexer; utilizing the multiplexer to switch an input of a main clock between each of the pair of input clock signals; inducing a phase build-out activity; and transmitting an output clock signal.

Abstract: A circuit and method of generating delayed tap signals can adjust a delay difference by interpolating two input clock signals as indicated by an offset information signal. In the circuit, first and second tap signals are generated by interpolating first and second clock signals in response to the offset information. A delay difference between output tap signals is adjusted by an amount indicated by the offset information. Thus, tap signals having a fine delay difference can be obtained by adjusting the offset information.

Abstract: A level shift circuit realizes a high-speed and power-saved operation particularly when the input voltage is at a low level. The level shift circuit includes a first gate voltage control circuit controlled by an inverted signal of an input signal, which is inserted between a gate of a third transistor and a second output terminal; a second gate voltage control circuit controlled by the input signal, which is inserted between a gate of a fourth transistor and a first output terminal; a first transistor; and a second transistor. When the input signal shifts from “H” to “L”, the first transistor turns OFF, the third transistor is turned ON by the first gate voltage control circuit, and then a voltage of the first output terminal rises. The second transistor turns ON, the fourth transistor is turned OFF by the second gate voltage control circuit, and the voltage of the second output terminal goes down.

Abstract: A circuit for controlling pulse width of a signal for driving a light emitting element, includes a pulse width control circuit capable of responding to multi-bit rates in the same circuit structure. For this purpose, the pulse width control circuit has a Tr/Tf control section controlling at least one of a rise time Tr and a fall time Tf of an input signal according to the bit rate of the input signal; a waveform shaping section shaping a signal output from the Tr/Tf control section to generate an output signal; and a control signal generating section generating a control signal for controlling an operation of the Tr/Tf control section based on pulse width control information.

Abstract: The invention provides a low power, high performance flip-flop. The flip-flop uses only one clocked transistor. The single clocked transistor is shared by the first and second branches of the device. A pulse generator produces a clock pulse to trigger the flip-flop. In one preferred embodiment the device can be made as a static explicit pulsed flip-flop which employs only two clocked transistors.

Abstract: A phase-locked loop includes a phase detector to measure a phase offset between a reference clock signal and a feedback clock signal, and to generate first and second output control signals having a pulse width corresponding to the phase offset. The phase locked loop further includes a first pulse width control circuit coupled to the phase detector to reduce the pulse width of the first output control signal producing a first modified output control signal, a second pulse width control circuit coupled to the phase detector to reduce the pulse width of the second output control signal producing a second modified output control signal, a first charge pump coupled to the phase detector to provide a first charge signal responsive to the first and second output control signals, and a second charge pump coupled to the first and second pulse width control circuits to provide a second charge signal responsive to the first and second modified output control signals.

Abstract: An electronic system includes a deskewing circuit configured to measure a delay and generate a synchronized signal according to the measured delay. The deskewing circuit may be configured to detect an overflow condition and respond accordingly, for example by asserting an overflow signal. Further, the deskewing circuit may be additionally or alternatively configured to detect successful measurement of the delay and respond, for example by executing a power saving and/or noise reducing procedure.

Abstract: A first circuit is to generate a data signal containing data. A second circuit is to utilize said data, where the first and second circuits are commonly clocked by a latch signal, further a circuit has a first level sensitive latch to latch the data signal from the first circuit upon receiving by way of a delay circuit the latch signal, and a second level sensitive latch to latch an output signal of the first level sensitive latch to the second circuit upon receiving the latch signal. Other embodiments are also described and claimed.

Abstract: Phase shifter circuits and methods use counters to define the positions of the output clock edges. A plurality of counters are each clocked by a count clock relatively much faster than the input clock. A first counter counts for one input clock period, and a delay value is determined based at least in part on the counted value. In some embodiments, the delay value has a maximum value that depends on the counted value. The delay value is provided to a second counter, which counts from zero to the delay value and generates a pulse one delay value after the beginning of the input clock period. A third counter running at the same clock rate generates a pulse after an additional delay. The pulses from the counters are used to provide output clock edges at predetermined times during the input clock cycle. Some circuits also perform a duty cycle correction.