Abstract: A memory device includes a memory cell array having a plurality of normal memory cells and a plurality of redundant memory cells therein, a fuse array configured to store an address and a master bit of a defective first memory cell therein, and a column decoder configured to select among a plurality of column select lines associated with the normal memory cells and a plurality of spare column select lines associated with the redundant memory cells. The column decoder has a first column repair circuit therein, which includes: (i) a first latch array having a plurality of latch elements therein, which are configured to store a column address of the defective first memory cell, and (ii) first compare logic configured to compare outputs of the plurality of latch elements with an external column address, and generate a first enable signal that indicates whether or not to repair the defective first memory cell, in response to said compare.

Abstract: Provided is a method for performing an aging test on a neural processing unit (NPU) with a capability of a runtime test. The method may comprise: performing an aging test on the NPU which comprises a plurality of functional components. The plurality of functional components may comprise at least one memory and plural processing elements. The performing of the aging test may include: performing a scan test on the NPU to verify whether at least one functional component in the NPU is defective or not; and performing a memory test on the at least one memory. At least one of the scan test and the memory test may be repeatedly performed to put a stress on the NPU for the aging test. The aging test may be repeated by a predetermined number.

Abstract: Systems, apparatuses, and methods provide for technology performs write current adjustment management in crosspoint persistent memory structures. Such technology determines whether to adjust a base current in response to a sampling of write-and-read operations on a set of addresses in a crosspoint persistent memory; determines whether a test current reduces a number of bit fails in response to a determination of whether to adjust the base current; and adjusts the base current based on the test current in response to a determination that the test current reduces the number of bit fails.

Abstract: Some implementations provide systems methods and devices for integrated circuit self-test. The integrated circuit includes interface circuitry configured to read test data and to write the test data into memory of the integrated circuit. The integrated circuit also includes test circuitry configured to test the interface circuitry based on the test data written into memory of the integrated circuit. Some implementations provide an integrated circuit configured for storing and reading data. The integrated circuit includes circuitry configured to write or read a first portion of data to or from a first memory via BIST circuitry of the first memory until a first BIST counter saturates. The integrated circuit also includes circuitry configured to write or read a second portion of the data to or from a second memory via BIST circuitry of the second memory until a second BIST counter saturates.

Abstract: A method is disclosed for scanning an array of memory cells arranged in rows and columns, where the array includes a scan chain partitioned into multiple sections. Each section includes a first scan multiplexer, a section buffer cell, and multiple memory cells. The method includes determining whether a scan shift mode is entered, asserting a scan enable signal to select second inputs of each first scan multiplexer when the scan shift mode is entered, coupling the scan input with the input of the section buffer cell of the first section, and coupling the output of the memory cell in the previous section with the input of the section buffer cell in the next section. The method further includes updating the contents of the section buffer cell and the memory cells using clock signals and scan word line pulses.

Abstract: A system is provided. The system comprises test devices, a transport device and a data processing device. The test devices perform tests different from each other to a memory device and output test results of the tests. The transport device transports the memory device to the test devices and comprises a first storage device. The first storage device stores the test results and a list of a part of test devices that have tested the memory device. The data processing device stores fabrication data of the memory device. When the transport device determines that the memory device is defective according to at least one of the test results, the data processing device generates a report according the at least one of the test results and the fabrication data.

Abstract: A nonvolatile memory device includes a control logic configured to generate a clock signal and a page buffer selection signal including information about a ratio of a number of page buffers on which a fail bit counting operation is performed to a total number of the plurality of page buffers, a fail bit counting circuit configured to select one or more page buffers from among the plurality of page buffers, repeat the fail bit counting operation on the selected one or more page buffers, and output a value of a number of fail bits with respect to the page buffers on which the fail bit counting operation is performed, and a predictor configured to generate a prediction value with respect to a total number of fail bits with respect to the plurality of page buffers.

Abstract: A storage device includes at least one nonvolatile memory device, a volatile memory device and a storage controller. The storage controller performs an error correction code (ECC) decoding on a read data read from the volatile memory device, in response to uncorrectable errors being detected in the read data, corrects the uncorrectable errors that are not correctable by the ECC decoding to generate corrected data by performing an erasure decoding on the read data, replaces a defective word-line of a first memory region with a redundancy word-line of a second memory region by performing a soft post package repair PPR on the first memory region that stores the read data, stores the corrected data in the second memory region and performs a re-read operation on the second memory region.

Abstract: An apparatus includes one or more control circuits that are configured to connect to a plurality of nonvolatile memory cells. The one or more control circuits are configured to detect a first boundary between written and unwritten portions of an open block and, in response to detecting the first boundary, check for a second boundary between written and unwritten portions of the open block in order to determine if the open block was subject to a non-uniform erase operation.

Abstract: During a command bus training (CBT), interconnected memory dice are accessed in a sequence determined (e.g., predetermined) by a bit sequence generator and via a shared data link for retrieving a respective set of feedback data of the CBT from each memory dice. This eliminates a need to individually train and/or control interconnected memory dice for the CBT; thereby, providing a flexible and scalable architecture that can accommodate a range of memory densities (e.g., a number of memory dice that are interconnected) and making it a valuable solution for high-performance memory applications.

Abstract: A memory system disclosed herein features left and/or right memory banks, with left and/or right input/output (IO) blocks aligned with the memory banks for managing data input and output. A control section, situated between the left and right input/output blocks, oversees memory operations, receives control signals, and performs stuck-at testing. The control section includes fault detection logic designed to output a first logic value (e.g., logic low) if logic values at each of its external inputs are identical, but output a second logic value (e.g., logic high) if not. The fault detection logic is capable of detecting stuck-at faults in the external inputs by performing both stuck-at-0 and stuck-at-1 testing. If only stuck-at-0 or stuck-at-1 faults are detected, the fault detection logic can pinpoint those faults by iteratively changing input values at each of its external inputs and observing the output of the fault detection logic.

Abstract: A memory device and read voltage setting method are provided. The memory device may be a 3D NAND flash memory circuit, and provides a high-capacity storage medium with favorable performance. The read voltage setting method includes: performing read verify operations on multiple memory cells according to multiple first reading voltage intervals and obtaining multiple first pass memory cells numbers; shifting the respective first reading voltage intervals by a shift voltage value to obtain multiple second reading voltage intervals; determining whether there is at least one consecutive equal number or a minimum number of the pass cells numbers and setting a read voltage according to the at least one equal number or the minimum number.

Abstract: A semiconductor memory device and control method thereof are provided, repairing defective bit lines even if the number of defective bit lines exceeds that of a spare bit line in any subarray in multiple subarrays. The semiconductor memory device includes a memory cell array having multiple subarrays, and a controller, configured to activate the word line and a corresponding word line in a second subarray which is separately arranged from the first subarray in a column direction when activating any word line in a first subarray of the plurality of subarrays. The controller is further configured to access the memory cells connected to the activated word line in the second subarray instead of the memory cells connected to the activated word line in the first subarray when a first condition (i.e., the number of defective bit lines exceeds the number of spare bit lines in the first subarray) is met.

Abstract: Methods, systems, and devices implementing self-timing read termination are described. A memory system may perform a read operation in which the memory system generates a first signal and a second signal to couple a first sense component and a second sense component with a global access line, respectively. The first sense component may be coupled with one or more memory cells via an access line, and the second sense component may be configured to determine one or more logic values of the one or more memory cells based on the coupling with the global access line. The memory system may support a self-timed termination of the first signal to decouple the first sense component from the global access line. The memory system may generate a third signal to terminate the first signal based on determining the one or more logic values.

Abstract: A memory device includes: a word line selector (X decoder) configured to select word lines; a memory cell having cells that are connected to the word lines and to bit line units so as to be arrayed in a matrix; a bit detector configured to detect, via the bit line units, the logic values of the bit data stored in the cells connected to a selected word line; a data output circuit configured to output data based on the results of detection by the bit detector; and a controller. Fixed values are stored in part of the cells corresponding to a predetermined number of bits, and the controller compares, with expected values, the fixed values read from the part of the cells via the bit detector and the data output circuit.

Abstract: A system for improving radiation tolerance of memory senses an amount of radiation exposure and, based on the sensed amount of radiation exposure, determines whether to perform one or more techniques for mitigating the effects of the radiation exposure. As an example, the system may perform a data refresh operation by re-writing data that has been corrupted by radiation, or the system may adjust the reference voltage used to read memory cells. In another example, the system may perform a fault repair operation by re-programming cells that have erroneously transitioned from a program state to an erase state. The system may selectively perform different radiation-mitigation techniques in a tiered approach based on the sensed amount of radiation in order to limit the adverse effects of the more invasive techniques.

Abstract: An apparatus includes vote aggregation circuitry configured to receive a first plurality of vote signals associated with an active memory state of a volatile memory and to generate a first vote aggregation signal based on the first plurality of vote signals. The vote aggregation circuitry is further configured to receive a second plurality of vote signals associated with a retention memory state of the volatile memory and to generate a second vote aggregation signal based on the second plurality of vote signals. The apparatus further includes memory bank control circuitry coupled to the vote aggregation circuitry and configured to provide a plurality of control signals to the volatile memory based on the first vote aggregation signal and the second vote aggregation signal. The plurality of control signals indicate, for each bank of a plurality of banks of the volatile memory, a mode associated with the bank.

Abstract: Apparatuses and methods for forcing memory cell failures in a memory device are disclosed. An example apparatus includes a column disable control circuit coupled to a plurality of column latch sets to receive match signals and associated column plane addresses, the column disable control circuit configured to provide redundant column select signals and column plane masking signals based on the match signals and associated column plane addresses, the column disable control circuit further configured to provide the redundant column select signal and the column plane masking signal corresponding to an active match signal and associated column plane address from a designated column latch set when a disable memory test mode is enabled to cause one or more memory cells of main memory to fail.

Abstract: An input/output circuit comprises a bypass circuit, a first latch, a second latch, a first transistor, and a second transistor. The bypass circuit is configured to directly receive a data signal and indirectly receive a write enable signal. The first latch is coupled between a first data line and a second data line. The second latch is operatively coupled to the first latch and configured to generate a data output signal based on a voltage level presented on the second data line. The first transistor is coupled to the first latch and gated by a sense enable signal. The second transistor is coupled to the first latch and gated by a clock signal. The first transistor and the second transistor are alternately activated in each of a plurality of operation modes of the input/output circuit.

Abstract: A storage device may speed up error correction by pre-characterizing weak cell information in a memory device. The storage device includes a memory device with cells that may store multiple bits. A controller executes a pre-characterization operation on the memory device to identify a slow cell and/or a fast cell on the memory device. The controller retrieves weak cell information for the slow cell and/or the fast cell. The controller converts the weak cell information into values used by an error correction engine and provides the values to the error correction engine to be used in decoding information retrieved from the memory device.