Abstract: A subsystem with an array of memory cells includes a scan chain with one or more chain segments of storage memory cells. Chain segments are separated by chain buffer memory cells. Memory cells of each chain segment are coupled with a sequence generator that generates a sequence of non-overlapping pulses from a pulse in a scan clock (SCLK) signal. The duration of the sequence equals at most a cycle of the SCLK signal. The scan chain applies the pulses to the memory cells backwards starting from the chain buffer memory cell. Memory cells may include a single latch. The array of memory cells may be included in a semiconductor memory subsystem. A scan chain that has a fault condition may be repaired by rerouting the scan chain to avoid the location of the fault condition and to add one or more redundant chain segments.

Abstract: Provided herein may be a storage device for supporting dynamic allocation of memory and a method of operating the same. The storage device may include a plurality of memory dies, a state detector configured to detect respective memory states of the plurality of memory dies, a memory information storage configured to store defect information that is information about memory dies in which defects have occurred among the plurality of memory dies, and a memory controller configured to, in response to a memory die allocation request for performing an operation corresponding to an externally provided operation request, determine allocation of a memory die based on a result of comparison between each detected memory state and the defect information.

Abstract: Self-test circuits of memory devices disclosed herein may include circuitry that adjusts the correspondence between logical and physical addresses to match pre-repair mapping of memory locations. That is, if a memory device has been repaired by remapping logical addresses to new physical addresses, the circuitry of the test circuit restores the pre-repair mapping of the memory device in some examples. In some examples, an unused global column redundancy data path may be repurposed to provide repair information to the self-test circuit to implement the pre-repair mapping.

Abstract: Apparatuses and techniques for implementing usage-based disturbance (UBD) counter repair are described. In example implementations, a memory device includes multiple memory rows, multiple corresponding UBD counters, a register, and a spare UBD counter. If a UBD counter is faulty, logic can substitute the spare UBD counter. To do so, the logic can store a row address corresponding to the faulty UBD counter in the register. The logic can increment a value in the spare UBD counter responsive to a row activation corresponding to the stored row address. A mitigation procedure on a row that may be affected by the activation can be performed based on the value. A host device can control, at least partially, the UBD counter repair process. In these manners, a repair of a faulty UBD counter can be accomplished faster and/or with fewer resources as compared to replacing a memory row and corresponding UBD counter.

Abstract: A memory module is provided, comprising a connector and a plurality of memory devices. Each memory device includes a memory array and a plurality of data connections, wherein a first subset of the plurality of data connections are configured to communicate data with a first portion of the memory array, and a second subset of the plurality of data connections are configured to communicate data with a second portion of the memory array. The first subset of the plurality of data connections of each of the plurality of memory devices are connected in parallel to first external contacts of the connector in a first addressable pseudo-channel, and the second subset of the plurality of data connections of each of the plurality of memory devices are connected in parallel to second external contacts of the connector in a second addressable pseudo-channel.

Abstract: A test and measurement system includes a multi-stack test subsystem including a plurality of test and measurement instruments, each instrument coupled to a device under test (DUT) to receive a plurality of test signals from the DUT during a test mode of operation. One test and measurement instrument is designated as a master and the remainder are designated as extension test and measurement instruments. The master communicates control signals to each of the extensions to synchronize the test and measurement instruments to simultaneously acquire the plurality of test signals provided by the DUT. An automation engine is coupled to the multi-stack test subsystem to receive the acquired plurality of test signals from the master, and the automation engine analyzes the acquired test signals to perform validation testing for each of plurality of test signals and simultaneously display results of the validation testing for the plurality of test signals.

Abstract: A memory device is provided. The memory device includes: a package substrate; a memory chip, with chip inputs/outputs (I/Os), and attached to the package substrate; and package terminals, disposed on the package substrate, and having: functional package terminals, connected to the chip I/Os; no-connect (NC) package terminals, arranged among the functional package terminals and not connected to any of the chip I/Os; and redesigned NC package terminals, as additional ones of the NC package terminals but connected to the chip I/Os, so as to be functioned as additional functional package terminals.

Abstract: The present disclosure provides a method for controlling bit line voltages in a three-dimensional memory device. The method includes ramping up a bit line clamp regulation voltage and a control signal regulation voltage. The method also includes ramping up a bit line clamp enabling voltage and a control signal enabling voltage. The method also includes increasing a bit line clamp voltage in one stage, and increasing a control signal voltage in two stages. The method also includes decreasing the control signal voltage. The method also includes ramping down the bit line clamp enabling voltage, the bit line clamp regulation voltage, the control signal enabling voltage, and the control signal regulation voltage. The method further includes decreasing the bit line clamp voltage.

Abstract: A memory device includes a memory cell array having a plurality of normal memory cells and a plurality of redundant memory cells therein, a fuse array configured to store an address and a master bit of a defective first memory cell therein, and a column decoder configured to select among a plurality of column select lines associated with the normal memory cells and a plurality of spare column select lines associated with the redundant memory cells. The column decoder has a first column repair circuit therein, which includes: (i) a first latch array having a plurality of latch elements therein, which are configured to store a column address of the defective first memory cell, and (ii) first compare logic configured to compare outputs of the plurality of latch elements with an external column address, and generate a first enable signal that indicates whether or not to repair the defective first memory cell, in response to said compare.

Abstract: Provided is a method for performing an aging test on a neural processing unit (NPU) with a capability of a runtime test. The method may comprise: performing an aging test on the NPU which comprises a plurality of functional components. The plurality of functional components may comprise at least one memory and plural processing elements. The performing of the aging test may include: performing a scan test on the NPU to verify whether at least one functional component in the NPU is defective or not; and performing a memory test on the at least one memory. At least one of the scan test and the memory test may be repeatedly performed to put a stress on the NPU for the aging test. The aging test may be repeated by a predetermined number.

Abstract: Systems, apparatuses, and methods provide for technology performs write current adjustment management in crosspoint persistent memory structures. Such technology determines whether to adjust a base current in response to a sampling of write-and-read operations on a set of addresses in a crosspoint persistent memory; determines whether a test current reduces a number of bit fails in response to a determination of whether to adjust the base current; and adjusts the base current based on the test current in response to a determination that the test current reduces the number of bit fails.

Abstract: Some implementations provide systems methods and devices for integrated circuit self-test. The integrated circuit includes interface circuitry configured to read test data and to write the test data into memory of the integrated circuit. The integrated circuit also includes test circuitry configured to test the interface circuitry based on the test data written into memory of the integrated circuit. Some implementations provide an integrated circuit configured for storing and reading data. The integrated circuit includes circuitry configured to write or read a first portion of data to or from a first memory via BIST circuitry of the first memory until a first BIST counter saturates. The integrated circuit also includes circuitry configured to write or read a second portion of the data to or from a second memory via BIST circuitry of the second memory until a second BIST counter saturates.

Abstract: A method is disclosed for scanning an array of memory cells arranged in rows and columns, where the array includes a scan chain partitioned into multiple sections. Each section includes a first scan multiplexer, a section buffer cell, and multiple memory cells. The method includes determining whether a scan shift mode is entered, asserting a scan enable signal to select second inputs of each first scan multiplexer when the scan shift mode is entered, coupling the scan input with the input of the section buffer cell of the first section, and coupling the output of the memory cell in the previous section with the input of the section buffer cell in the next section. The method further includes updating the contents of the section buffer cell and the memory cells using clock signals and scan word line pulses.

Abstract: A system is provided. The system comprises test devices, a transport device and a data processing device. The test devices perform tests different from each other to a memory device and output test results of the tests. The transport device transports the memory device to the test devices and comprises a first storage device. The first storage device stores the test results and a list of a part of test devices that have tested the memory device. The data processing device stores fabrication data of the memory device. When the transport device determines that the memory device is defective according to at least one of the test results, the data processing device generates a report according the at least one of the test results and the fabrication data.

Abstract: A nonvolatile memory device includes a control logic configured to generate a clock signal and a page buffer selection signal including information about a ratio of a number of page buffers on which a fail bit counting operation is performed to a total number of the plurality of page buffers, a fail bit counting circuit configured to select one or more page buffers from among the plurality of page buffers, repeat the fail bit counting operation on the selected one or more page buffers, and output a value of a number of fail bits with respect to the page buffers on which the fail bit counting operation is performed, and a predictor configured to generate a prediction value with respect to a total number of fail bits with respect to the plurality of page buffers.

Abstract: A storage device includes at least one nonvolatile memory device, a volatile memory device and a storage controller. The storage controller performs an error correction code (ECC) decoding on a read data read from the volatile memory device, in response to uncorrectable errors being detected in the read data, corrects the uncorrectable errors that are not correctable by the ECC decoding to generate corrected data by performing an erasure decoding on the read data, replaces a defective word-line of a first memory region with a redundancy word-line of a second memory region by performing a soft post package repair PPR on the first memory region that stores the read data, stores the corrected data in the second memory region and performs a re-read operation on the second memory region.

Abstract: An apparatus includes one or more control circuits that are configured to connect to a plurality of nonvolatile memory cells. The one or more control circuits are configured to detect a first boundary between written and unwritten portions of an open block and, in response to detecting the first boundary, check for a second boundary between written and unwritten portions of the open block in order to determine if the open block was subject to a non-uniform erase operation.

Abstract: During a command bus training (CBT), interconnected memory dice are accessed in a sequence determined (e.g., predetermined) by a bit sequence generator and via a shared data link for retrieving a respective set of feedback data of the CBT from each memory dice. This eliminates a need to individually train and/or control interconnected memory dice for the CBT; thereby, providing a flexible and scalable architecture that can accommodate a range of memory densities (e.g., a number of memory dice that are interconnected) and making it a valuable solution for high-performance memory applications.

Abstract: A memory system disclosed herein features left and/or right memory banks, with left and/or right input/output (IO) blocks aligned with the memory banks for managing data input and output. A control section, situated between the left and right input/output blocks, oversees memory operations, receives control signals, and performs stuck-at testing. The control section includes fault detection logic designed to output a first logic value (e.g., logic low) if logic values at each of its external inputs are identical, but output a second logic value (e.g., logic high) if not. The fault detection logic is capable of detecting stuck-at faults in the external inputs by performing both stuck-at-0 and stuck-at-1 testing. If only stuck-at-0 or stuck-at-1 faults are detected, the fault detection logic can pinpoint those faults by iteratively changing input values at each of its external inputs and observing the output of the fault detection logic.

Abstract: A memory device and read voltage setting method are provided. The memory device may be a 3D NAND flash memory circuit, and provides a high-capacity storage medium with favorable performance. The read voltage setting method includes: performing read verify operations on multiple memory cells according to multiple first reading voltage intervals and obtaining multiple first pass memory cells numbers; shifting the respective first reading voltage intervals by a shift voltage value to obtain multiple second reading voltage intervals; determining whether there is at least one consecutive equal number or a minimum number of the pass cells numbers and setting a read voltage according to the at least one equal number or the minimum number.