Abstract: Apparatuses and techniques for efficient handling of data errors and usage-based disturbances are described. To enable efficient utilization of time-limited resources, a memory device includes control circuitry that performs multiple different types of operations responsive to “confiscating” a refresh-pump time interval. The memory device is responsible for performing various functionalities internally while reducing the impact such functionalities may have on servicing memory requests from an external entity. Accordingly, a memory device may confiscate refresh-pump opportunities and instead perform other operations. To efficiently utilize a refresh-pump opportunity, the control circuitry can perform an error-handling operation on a codeword stored in a first bank and perform a usage-based disturbance mitigation operation on a row in a second bank during the confiscated time interval. Further, the usage-based disturbance mitigation operation can be performed across multiple banks except for the first bank.

Abstract: A data recover read (DRR) operation method of a nonvolatile memory system includes: performing a first read operation on adjacent memory cells, which are connected to an adjacent wordline adjacent to a target wordline, based on a first specific read level; obtaining a cell count value for the adjacent wordline; determining offset values for a normal read level of target memory cells, which are connected to the target wordline, based on the cell count value for the adjacent wordline; and performing a second read operation on the target memory cells, based on the determined offset values and a result of the first read operation.

Abstract: Example memory devices, systems, and methods for reducing program disturbance in memory devices are disclosed. One example method includes during an n-th loop of a program operation performed on a first memory cell in a memory cell array, applying a first voltage to a first bit line coupled to a second memory cell in the memory cell array, where the first memory cell and the second memory cell are coupled to a first word line. The first bit line is discharged to decrease a voltage of the first bit line from the first voltage to a second voltage, where the second voltage is lower than the first voltage. After the first voltage is applied to the first bit line, a second bit line is set to floating, where the second bit line is coupled to the first memory cell.

Abstract: A three-dimensional (3D) memory device includes a memory string, a coarse top select gate (TSG) line configured to couple a coarse threshold voltage (Vth_coarse) for programming the memory string, a word line configured to program the memory string, a buffer TSG line configured to couple a buffer threshold voltage (Vth_buffer) for programming the memory string, a fine TSG line configured to couple a fine threshold voltage (Vth_fine) for programming the memory string, and a coarse TSG cut disposed between the memory string and a second memory string adjacent the memory string. The 3D memory device can intrinsically increase the coarse threshold voltage (Vth_coarse), decrease leakage current, dynamically adjust and fine tune a threshold voltage (Vth) of the memory string, and increase TSG reliability.

Abstract: A semiconductor device may include a memory cell that is connected between a bit line and a word line, and a cell threshold voltage sensing circuit configured to provide a first voltage to the memory cell whenever a pulse is activated. The cell threshold voltage sensing circuit may generate a voltage corresponding to a current that flows through the memory cell whenever the pulse is activated, and may generate a threshold voltage sensing result signal by comparing the generated voltage with a reference voltage. The threshold voltage sensing result signal may be used to adjust the first voltage to a level corresponding to a threshold voltage of the memory cell, and the memory cell may be read using the adjusted first voltage to generate random data.

Abstract: An example apparatus includes a dividing circuit configured to divide an original data strobe signal supplied synchronously with a set of write data to generate first to fourth data strobe signals having mutually different phase from one another, a first data latch circuit configured to latch one of the set of write data synchronously with the first data strobe signal, the first data latch circuit being configured to be reset responsive to a first reset signal; a second data latch circuit configured to latch another of the set of write data synchronously with the second data strobe signal, the second data latch circuit being configured to be reset responsive to a second reset signal; and a burst counter circuit configured to activate the first and second reset signals responsive to the third and fourth data strobe signals.

Abstract: An apparatus includes one or more control circuit configured to connect to a nonvolatile memory cell structure that includes nonvolatile memory cells each having a programmable resistive element. The one or more control circuit is configured to receive an address that corresponds to a location in the nonvolatile memory cell structure and set a variable resistor according to the location. The variable resistor is connected in series with a selected nonvolatile memory cell that is located at the location. The one or more control circuit is further configured to drive a memory access current through the selected nonvolatile memory cell and the variable resistor in series.

Abstract: Systems, devices, methods, and storage media for managing refreshment of memory cells in memory systems are provided. In one aspect, a memory system includes: a non-volatile memory device including a plurality of memory cells and a memory controller coupled to the non-volatile memory device. The memory controller is configured to: refresh adjacent memory cells of a target memory cell of the plurality of memory cells, when a count of write operations performed on the target memory cell within a preset time duration is greater than a preset threshold.

Abstract: A semiconductor memory device includes a row hammer management circuit and a refresh control circuit. The row hammer management circuit counts the number of times of access on each memory cell row to store the counted values in count cells of each memory cell row as count data. A hammer address queue in the row hammer management circuit stores candidate hammer addresses, which are intensively accessed, in response to a number of the candidate hammer addresses reaching a second number, transitions a logic level of an error signal provided to the memory controller, and, in response to the number of the candidate hammer addresses reaching the first number, outputs one of the candidate hammer addresses as a hammer address. The refresh control circuit performs a hammer refresh operation on victim memory cell rows which are physically adjacent to a memory cell row corresponding to the hammer address.

Abstract: An array of memory cells can be configured into one or more scan chains that uses non-overlapping scan word line pulses in a direction opposite to a direction of the scan chain to shift scan bits in the direction of the scan chain from a scan chain input to a scan chain output. A memory cell may include a latch and a scan input multiplexer. The array includes a pulse generator to derive a pulse generator output from a clock pulse, and a digital delay line to generate the non-overlapping scan word line pulses from the pulse generator output. The scan chain may include a latch from an input buffer and may scan multiple columns or rows.

Abstract: A memory device including a repair circuit and an operating method of the memory device are provided. The operating method includes outputting a signal representing a pre-decoded faulty row address based on predecoding a faulty row address, outputting a signal representing a pre-decoded row address based on predecoding a row address, outputting hit signals based on comparing a bit value of the pre-decoded faulty row address with a bit value of the pre-decoded row address, outputting a repair enable signal based on the hit signals, and performing a row repair operation based on the repair enable signal.

Abstract: A memory device can include a first portion having a memory array comprising a plurality of memory cells and a first via chain segment for performing a test operation. The memory device can include a second portion comprising processing circuitry and a second via chain segment for performing the test operation. The memory device can also include an interconnect coupling the first portion and the second portion, the interconnect comprising a third via chain segment, wherein the first via chain segment, second via chain segment, and third via chain segment can be selected independently.

Abstract: A subsystem with an array of memory cells includes a scan chain with one or more chain segments of storage memory cells. Chain segments are separated by chain buffer memory cells. Memory cells of each chain segment are coupled with a sequence generator that generates a sequence of non-overlapping pulses from a pulse in a scan clock (SCLK) signal. The duration of the sequence equals at most a cycle of the SCLK signal. The scan chain applies the pulses to the memory cells backwards starting from the chain buffer memory cell. Memory cells may include a single latch. The array of memory cells may be included in a semiconductor memory subsystem. A scan chain that has a fault condition may be repaired by rerouting the scan chain to avoid the location of the fault condition and to add one or more redundant chain segments.

Abstract: Provided herein may be a storage device for supporting dynamic allocation of memory and a method of operating the same. The storage device may include a plurality of memory dies, a state detector configured to detect respective memory states of the plurality of memory dies, a memory information storage configured to store defect information that is information about memory dies in which defects have occurred among the plurality of memory dies, and a memory controller configured to, in response to a memory die allocation request for performing an operation corresponding to an externally provided operation request, determine allocation of a memory die based on a result of comparison between each detected memory state and the defect information.

Abstract: Self-test circuits of memory devices disclosed herein may include circuitry that adjusts the correspondence between logical and physical addresses to match pre-repair mapping of memory locations. That is, if a memory device has been repaired by remapping logical addresses to new physical addresses, the circuitry of the test circuit restores the pre-repair mapping of the memory device in some examples. In some examples, an unused global column redundancy data path may be repurposed to provide repair information to the self-test circuit to implement the pre-repair mapping.

Abstract: Apparatuses and techniques for implementing usage-based disturbance (UBD) counter repair are described. In example implementations, a memory device includes multiple memory rows, multiple corresponding UBD counters, a register, and a spare UBD counter. If a UBD counter is faulty, logic can substitute the spare UBD counter. To do so, the logic can store a row address corresponding to the faulty UBD counter in the register. The logic can increment a value in the spare UBD counter responsive to a row activation corresponding to the stored row address. A mitigation procedure on a row that may be affected by the activation can be performed based on the value. A host device can control, at least partially, the UBD counter repair process. In these manners, a repair of a faulty UBD counter can be accomplished faster and/or with fewer resources as compared to replacing a memory row and corresponding UBD counter.

Abstract: A memory module is provided, comprising a connector and a plurality of memory devices. Each memory device includes a memory array and a plurality of data connections, wherein a first subset of the plurality of data connections are configured to communicate data with a first portion of the memory array, and a second subset of the plurality of data connections are configured to communicate data with a second portion of the memory array. The first subset of the plurality of data connections of each of the plurality of memory devices are connected in parallel to first external contacts of the connector in a first addressable pseudo-channel, and the second subset of the plurality of data connections of each of the plurality of memory devices are connected in parallel to second external contacts of the connector in a second addressable pseudo-channel.

Abstract: A test and measurement system includes a multi-stack test subsystem including a plurality of test and measurement instruments, each instrument coupled to a device under test (DUT) to receive a plurality of test signals from the DUT during a test mode of operation. One test and measurement instrument is designated as a master and the remainder are designated as extension test and measurement instruments. The master communicates control signals to each of the extensions to synchronize the test and measurement instruments to simultaneously acquire the plurality of test signals provided by the DUT. An automation engine is coupled to the multi-stack test subsystem to receive the acquired plurality of test signals from the master, and the automation engine analyzes the acquired test signals to perform validation testing for each of plurality of test signals and simultaneously display results of the validation testing for the plurality of test signals.

Abstract: A memory device is provided. The memory device includes: a package substrate; a memory chip, with chip inputs/outputs (I/Os), and attached to the package substrate; and package terminals, disposed on the package substrate, and having: functional package terminals, connected to the chip I/Os; no-connect (NC) package terminals, arranged among the functional package terminals and not connected to any of the chip I/Os; and redesigned NC package terminals, as additional ones of the NC package terminals but connected to the chip I/Os, so as to be functioned as additional functional package terminals.

Abstract: The present disclosure provides a method for controlling bit line voltages in a three-dimensional memory device. The method includes ramping up a bit line clamp regulation voltage and a control signal regulation voltage. The method also includes ramping up a bit line clamp enabling voltage and a control signal enabling voltage. The method also includes increasing a bit line clamp voltage in one stage, and increasing a control signal voltage in two stages. The method also includes decreasing the control signal voltage. The method also includes ramping down the bit line clamp enabling voltage, the bit line clamp regulation voltage, the control signal enabling voltage, and the control signal regulation voltage. The method further includes decreasing the bit line clamp voltage.