Abstract: A non-volatile memory system programs memory cells from an erased threshold voltage distribution to programmed threshold voltage distributions by performing hole pre-charging of channels of unselected NAND strings in a selected block of a selected plane including applying a source voltage to a selected signal line of a plurality of signal lines that are isolated from each other. The selected signal line is positioned between the selected block and an unselected block and is connected to a selected source line of a plurality of source lines that are isolated from each other. The selected source line is connected to the selected block. The source voltage is greater in magnitude than any predetermined threshold voltage of the erased threshold voltage distribution. After the pre-charging, the system boosts channels of unselected NAND strings in the selected block and applies a program voltage to selected NAND strings in the selected block.

Abstract: A semiconductor device includes a central processing unit (CPU), a memory, a test data input terminal that receive test data, a test group identification terminal that receive a test group identification signal, a test data input control unit that receives the test group identification signal through the test group identification terminal and generates a memory write enable signal for allowing the test data to be written into the memory based on the test group identification signal, and a memory write control circuit that generates test data write address and selects the test data received through the test data input terminal based on the memory write enable signal to transfer the test data selected and the test data write address to the memory, whereby a test with the test data in the memory is executed.

Abstract: A motherboard assembly for testing memory components is described. The motherboard assembly has at least one CPU communicatively coupled with at least one memory channel, and a memory controller or BIOS programmed to continue booting in the presence of memory component failures. The memory controller or BIOS skips read/write training procedures when a failure is detected, and uses preset values for PHY registers from a previous successful booting procedure to continue the current booting without powering off. The memory controller or BIOS is also programmed to provide adjustable retention settings and adjustable speed settings without rebooting or powering off.

Abstract: A semiconductor device includes a memory circuit including a plurality of mats and configured to output first read data having a data sequence identical to a data sequence of pattern data after the start of a read operation during a test operation mode operation and configured to output a fail address including error information of the first read data, and a data processing circuit configured to output the first read data as data and configured to generate fail location information by encoding the fail address.

Abstract: A bank of a memory device may be divided into column planes. Each column plane may be associated with column selects. In some examples, a portion of a column plane associated with one column select may be used to store metadata associated with data of the remaining column selects. In some examples, the metadata may be mapped to the data based on a portion of a column address. In some examples, whether the memory device provides metadata responsive to a column address may be based on a value stored in a mode register. In some examples, the portion of the column plane associated with the one column select associated with metadata may also store error correction code data associated with the data of the remaining column selects.

Abstract: A memory device includes a base die configured to transmit transmission data that are driven to a first voltage range through a transmission line based on base data, and a core die configured to generate core data by shifting a voltage level of the transmission data received through the transmission line to a second voltage range.

Abstract: Apparatuses and techniques for efficient handling of data errors and usage-based disturbances are described. To enable efficient utilization of time-limited resources, a memory device includes control circuitry that performs multiple different types of operations responsive to “confiscating” a refresh-pump time interval. The memory device is responsible for performing various functionalities internally while reducing the impact such functionalities may have on servicing memory requests from an external entity. Accordingly, a memory device may confiscate refresh-pump opportunities and instead perform other operations. To efficiently utilize a refresh-pump opportunity, the control circuitry can perform an error-handling operation on a codeword stored in a first bank and perform a usage-based disturbance mitigation operation on a row in a second bank during the confiscated time interval. Further, the usage-based disturbance mitigation operation can be performed across multiple banks except for the first bank.

Abstract: A data recover read (DRR) operation method of a nonvolatile memory system includes: performing a first read operation on adjacent memory cells, which are connected to an adjacent wordline adjacent to a target wordline, based on a first specific read level; obtaining a cell count value for the adjacent wordline; determining offset values for a normal read level of target memory cells, which are connected to the target wordline, based on the cell count value for the adjacent wordline; and performing a second read operation on the target memory cells, based on the determined offset values and a result of the first read operation.

Abstract: Example memory devices, systems, and methods for reducing program disturbance in memory devices are disclosed. One example method includes during an n-th loop of a program operation performed on a first memory cell in a memory cell array, applying a first voltage to a first bit line coupled to a second memory cell in the memory cell array, where the first memory cell and the second memory cell are coupled to a first word line. The first bit line is discharged to decrease a voltage of the first bit line from the first voltage to a second voltage, where the second voltage is lower than the first voltage. After the first voltage is applied to the first bit line, a second bit line is set to floating, where the second bit line is coupled to the first memory cell.

Abstract: A three-dimensional (3D) memory device includes a memory string, a coarse top select gate (TSG) line configured to couple a coarse threshold voltage (Vth_coarse) for programming the memory string, a word line configured to program the memory string, a buffer TSG line configured to couple a buffer threshold voltage (Vth_buffer) for programming the memory string, a fine TSG line configured to couple a fine threshold voltage (Vth_fine) for programming the memory string, and a coarse TSG cut disposed between the memory string and a second memory string adjacent the memory string. The 3D memory device can intrinsically increase the coarse threshold voltage (Vth_coarse), decrease leakage current, dynamically adjust and fine tune a threshold voltage (Vth) of the memory string, and increase TSG reliability.

Abstract: A semiconductor device may include a memory cell that is connected between a bit line and a word line, and a cell threshold voltage sensing circuit configured to provide a first voltage to the memory cell whenever a pulse is activated. The cell threshold voltage sensing circuit may generate a voltage corresponding to a current that flows through the memory cell whenever the pulse is activated, and may generate a threshold voltage sensing result signal by comparing the generated voltage with a reference voltage. The threshold voltage sensing result signal may be used to adjust the first voltage to a level corresponding to a threshold voltage of the memory cell, and the memory cell may be read using the adjusted first voltage to generate random data.

Abstract: An example apparatus includes a dividing circuit configured to divide an original data strobe signal supplied synchronously with a set of write data to generate first to fourth data strobe signals having mutually different phase from one another, a first data latch circuit configured to latch one of the set of write data synchronously with the first data strobe signal, the first data latch circuit being configured to be reset responsive to a first reset signal; a second data latch circuit configured to latch another of the set of write data synchronously with the second data strobe signal, the second data latch circuit being configured to be reset responsive to a second reset signal; and a burst counter circuit configured to activate the first and second reset signals responsive to the third and fourth data strobe signals.

Abstract: An apparatus includes one or more control circuit configured to connect to a nonvolatile memory cell structure that includes nonvolatile memory cells each having a programmable resistive element. The one or more control circuit is configured to receive an address that corresponds to a location in the nonvolatile memory cell structure and set a variable resistor according to the location. The variable resistor is connected in series with a selected nonvolatile memory cell that is located at the location. The one or more control circuit is further configured to drive a memory access current through the selected nonvolatile memory cell and the variable resistor in series.

Abstract: Systems, devices, methods, and storage media for managing refreshment of memory cells in memory systems are provided. In one aspect, a memory system includes: a non-volatile memory device including a plurality of memory cells and a memory controller coupled to the non-volatile memory device. The memory controller is configured to: refresh adjacent memory cells of a target memory cell of the plurality of memory cells, when a count of write operations performed on the target memory cell within a preset time duration is greater than a preset threshold.

Abstract: A semiconductor memory device includes a row hammer management circuit and a refresh control circuit. The row hammer management circuit counts the number of times of access on each memory cell row to store the counted values in count cells of each memory cell row as count data. A hammer address queue in the row hammer management circuit stores candidate hammer addresses, which are intensively accessed, in response to a number of the candidate hammer addresses reaching a second number, transitions a logic level of an error signal provided to the memory controller, and, in response to the number of the candidate hammer addresses reaching the first number, outputs one of the candidate hammer addresses as a hammer address. The refresh control circuit performs a hammer refresh operation on victim memory cell rows which are physically adjacent to a memory cell row corresponding to the hammer address.

Abstract: An array of memory cells can be configured into one or more scan chains that uses non-overlapping scan word line pulses in a direction opposite to a direction of the scan chain to shift scan bits in the direction of the scan chain from a scan chain input to a scan chain output. A memory cell may include a latch and a scan input multiplexer. The array includes a pulse generator to derive a pulse generator output from a clock pulse, and a digital delay line to generate the non-overlapping scan word line pulses from the pulse generator output. The scan chain may include a latch from an input buffer and may scan multiple columns or rows.

Abstract: A memory device including a repair circuit and an operating method of the memory device are provided. The operating method includes outputting a signal representing a pre-decoded faulty row address based on predecoding a faulty row address, outputting a signal representing a pre-decoded row address based on predecoding a row address, outputting hit signals based on comparing a bit value of the pre-decoded faulty row address with a bit value of the pre-decoded row address, outputting a repair enable signal based on the hit signals, and performing a row repair operation based on the repair enable signal.

Abstract: A memory device can include a first portion having a memory array comprising a plurality of memory cells and a first via chain segment for performing a test operation. The memory device can include a second portion comprising processing circuitry and a second via chain segment for performing the test operation. The memory device can also include an interconnect coupling the first portion and the second portion, the interconnect comprising a third via chain segment, wherein the first via chain segment, second via chain segment, and third via chain segment can be selected independently.

Abstract: A subsystem with an array of memory cells includes a scan chain with one or more chain segments of storage memory cells. Chain segments are separated by chain buffer memory cells. Memory cells of each chain segment are coupled with a sequence generator that generates a sequence of non-overlapping pulses from a pulse in a scan clock (SCLK) signal. The duration of the sequence equals at most a cycle of the SCLK signal. The scan chain applies the pulses to the memory cells backwards starting from the chain buffer memory cell. Memory cells may include a single latch. The array of memory cells may be included in a semiconductor memory subsystem. A scan chain that has a fault condition may be repaired by rerouting the scan chain to avoid the location of the fault condition and to add one or more redundant chain segments.

Abstract: Provided herein may be a storage device for supporting dynamic allocation of memory and a method of operating the same. The storage device may include a plurality of memory dies, a state detector configured to detect respective memory states of the plurality of memory dies, a memory information storage configured to store defect information that is information about memory dies in which defects have occurred among the plurality of memory dies, and a memory controller configured to, in response to a memory die allocation request for performing an operation corresponding to an externally provided operation request, determine allocation of a memory die based on a result of comparison between each detected memory state and the defect information.