Patents Examined by Mohammed A Bashar
-
Patent number: 12009042Abstract: A trigger rate associated with a scan operation of a set of memory pages of a data block is identified. The trigger rate is compared to a threshold rate to determine that a condition is satisfied. In response to satisfying the condition, a refresh operation is executed on the set of memory pages of the data block.Type: GrantFiled: November 3, 2022Date of Patent: June 11, 2024Assignee: Micron Technology, Inc.Inventors: Vamsi Pavan Rayaprolu, Kishore Kumar Muchherla, Ashutosh Malshe, Gianni S. Alsasua, Harish R. Singidi
-
Patent number: 11994948Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit, an error log register and a control logic circuit. The memory cell array includes a plurality of memory bank arrays and each of the memory bank arrays includes a plurality of pages. The control logic circuit is configured to control the error correction circuit to perform an ECC decoding sequentially on some of the pages designated at least one access address for detecting at least one bit error, in response to a first command received from a memory controller. The control logic circuit performs an error logging operation to write page error information into the error log register and the page error information includes a number of error occurrence on each of the some pages determined from the detecting.Type: GrantFiled: February 3, 2023Date of Patent: May 28, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hoi-Ju Chung, Sang-Uhn Cha, Ho-Young Song, Hyun-Joong Kim
-
Patent number: 11996154Abstract: A page buffer circuit includes an intermediate circuit, a data storage circuit and an enhancive circuit. The intermediate circuit is coupled to a bit line coupled to a memory region and configured to apply a voltage having a voltage level, corresponding to a status of the memory region, to a sensing node. The data storage circuit is configured to store, therein, a value that corresponds to the status of the memory region in response to the voltage level. The enhancive circuit is coupled to the sensing node and configured to increase a capacitance of the sensing node in an enhancive interval during a selected operation.Type: GrantFiled: May 16, 2022Date of Patent: May 28, 2024Assignee: SK hynix Inc.Inventor: Hyung Jin Choi
-
Patent number: 11984177Abstract: A memory component comprises a memory unit including an array of memory cells, a controller of the memory unit, and a JTAG test interface including a plurality of contact pads adapted to connect the memory component with a host device and/or a test machine, wherein the test interface further comprises a plurality of test registers, which are configured to store the operating instructions for performing the test of the memory component, and wherein those test registers are organized in a matrix configuration, each row of the matrix being associated with a specific address. A related System-On-Chip device and a related method are further disclosed.Type: GrantFiled: September 30, 2022Date of Patent: May 14, 2024Inventors: Antonino Mondello, Alberto Troia
-
Patent number: 11984178Abstract: A flexible RAM loader including a shift register that includes a first data section coupled with a serial data input, and a second data section selectively coupled with a first parallel data input. The shift register is configured to load data serially from the serial data input to the first data section and the second data section when the second data section is uncoupled from the first parallel data input, and, when the second data section is coupled with the first parallel data input, configured to load data in parallel from the serial data input into the first data section and from the first parallel data input into the second data section. The flexible RAM loader also including a test register comprising a selection bit to couple the second data section with the first parallel data input.Type: GrantFiled: January 20, 2022Date of Patent: May 14, 2024Assignee: STMicroelectronics S.r.l.Inventor: Gabriele Solcia
-
Patent number: 11978507Abstract: To remedy short term data retention issues, a non-volatile memory performs a multi-pass programming process to program data into a set of non-volatile memory cells and identifies non-volatile memory cells that experienced downward threshold voltage drift after a first pass of the multi-pass programming process and prior to a final pass of the multi-pass programming process. The final pass of the multi-pass programming process comprises programming non-volatile memory cells not identified to have experienced the downward threshold voltage drift to a set of final target threshold voltages and purposefully overprogramming non-volatile memory cells identified to have experienced the downward threshold voltage drift to threshold voltages greater than respective final target threshold voltages by one or more offsets.Type: GrantFiled: March 8, 2022Date of Patent: May 7, 2024Assignee: Western Digital Technologies, Inc.Inventors: Ming Wang, Liang Li, Ke Zhang
-
Patent number: 11972814Abstract: The memory device includes a plurality of memory cells, which include a first set of memory cells and a second set of memory cells. A controller is in communication with the memory cells. The controller is configured to, in a first programming pass and then a second programming pass, program the memory cells of the first and second sets to respective final threshold voltages associated with a plurality of programmed data states. The controller is further configured to, in the first programming pass, verify the first set of memory cells at a first set of checkpoint data states and verify the second set of memory cells at a second set of checkpoint data states that is different than the first set of checkpoint data states.Type: GrantFiled: March 22, 2022Date of Patent: April 30, 2024Assignee: SanDisk Technologies, LLCInventors: Xue Bai Pitner, Yu-Chung Lien, Ravi Kumar, Jiahui Yuan, Bo Lei, Zhenni Wan
-
Patent number: 11972793Abstract: An integrated circuit device that has improved write margin at low operating voltages is disclosed. The integrated circuit device can include an SRAM array that has end power select circuits that can include selection circuits that provide a controllable impedance path between a power supply potential and an array power line. A power supply detection circuit may provide an assist enable signal when a power supply potential is low enough that write assist is needed. A power control circuit may provide end power control signals to end power select circuits to selectively control an impedance path between a power supply potential and an array power line to provide an I-R drop to a selected memory cell. In this way, write margins may be improved at low operating voltages.Type: GrantFiled: May 6, 2022Date of Patent: April 30, 2024Assignee: Mavagail Technology, LLCInventor: Darryl G. Walker
-
Patent number: 11955188Abstract: A semiconductor storage device of an embodiment includes a memory block, a resistance measurement circuit, and a control circuit. The memory block includes first to third control signal lines connected to gates of a first select gate transistor, a plurality of memory cell transistors, and a second select gate transistor. The resistance measurement circuit measures resistance of at least one control signal line among the first to third control signal lines. The control circuit performs erase, program, and read of data at the plurality of memory cell transistors included in the memory block. The control circuit determines, based on a measurement result of the resistance measurement by the resistance measurement circuit, whether to set a fail status to a result of erase verify that verifies the erase.Type: GrantFiled: March 9, 2022Date of Patent: April 9, 2024Assignee: Kioxia CorporationInventors: Hideki Igarashi, Wataru Makino
-
Patent number: 11955198Abstract: A lateral transfer path within an adjustable-width signaling interface of an integrated circuit component is formed by a chain of logic segments that may be intercoupled in different groups to effect the lateral data transfer required in different interface width configurations, avoiding the need for a dedicated transfer path per width configuration and thereby substantially reducing number of interconnects (and thus the area) required to implement the lateral transfer structure.Type: GrantFiled: January 16, 2023Date of Patent: April 9, 2024Assignee: Rambus Inc.Inventor: Frederick A. Ware
-
Patent number: 11942171Abstract: An example method may be used to perform concurrent compensation in a memory array. The example method may include decoding a prime row address corresponding to a respective prime memory cell row of a first row section of a memory array mat to provide a prime section signal, and in response to a determination that the prime row address matches a defective prime row address, providing a redundant section signal corresponding to a respective redundant memory cell row of a second row section of the memory array mat. In response to the prime section signal, initiating a first threshold voltage compensation operation on first sensing circuitry coupled to the first row section; and in response to the redundant section signal indicating a defective prime row, initiating a second threshold voltage compensation operation on second sensing circuitry coupled to the second row section concurrent with the first threshold voltage compensation operation.Type: GrantFiled: February 1, 2022Date of Patent: March 26, 2024Assignee: Micron Technology, Inc.Inventor: Harish V. Gadamsetty
-
Patent number: 11935610Abstract: A memory device includes: a memory cell array comprising a plurality of memory cells, the plurality of memory cells comprising a plurality of data memory cells including a first data memory cell and a plurality of backup memory cells including a first backup memory cell; a storage storing an error table configured to record errors in the plurality of data memory cells, the error table including a plurality of error table entries, each error table entry corresponding to one of the plurality of data memory cell and having an address and a failure count; and a controller configured to replace the first data memory cell with the first backup memory cell based on the error table.Type: GrantFiled: July 1, 2022Date of Patent: March 19, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hiroki Noguchi, Ku-Feng Lin, Yih Wang
-
Patent number: 11929716Abstract: The disclosure provides a Sense Amplifier (SA), a memory and a method for controlling the SA, and relates to the technical field of semiconductor memories. The SA includes: an amplifier module; an offset voltage storage unit electrically connected to the amplifier module and configured to store an offset voltage of the amplifier module in an offset elimination stage of the SA; and a load compensation unit electrically connected to the amplifier module and configured to compensate a difference between loads of the amplifier module in an amplification stage of the SA. The disclosure may improve an accuracy of reading data of the SA.Type: GrantFiled: September 13, 2021Date of Patent: March 12, 2024Assignees: ANHUI UNIVERSITY, CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Xiulong Wu, Li Zhao, Yangkuo Zhao, Jun He, Xin Li, Zhan Ying, Kanyu Cao, Wenjuan Lu, Chunyu Peng, Zhiting Lin, Junning Chen
-
Patent number: 11929134Abstract: Implementations described herein relate to performing a memory built-in self-test and indicating a status of the memory built-in self-test. A memory device may read one or more bits, associated with a memory built-in self-test, that are stored in a mode register of the memory device. The memory device may identify, based on the one or more bits, that the memory built-in self-test is enabled. The memory device may set a DMI bit of the memory device to a first value and perform the memory built-in self-test based on identifying that the memory built-in self-test is enabled. The memory device may set the DMI bit of the memory device to a second value based on a completion of the memory built-in self-test.Type: GrantFiled: June 17, 2022Date of Patent: March 12, 2024Assignee: Micron Technology, Inc.Inventor: Scott E. Schaefer
-
Patent number: 11929108Abstract: Provided are a memory detection method, a computer device and a storage medium. The method includes: initializing all storage units in a storage unit array; determining a plurality of target wordlines, two adjacent target wordlines being provided with a plurality of interfering wordlines therebetween; turning on the target wordlines, and performing a write operation on storage units connected to the target wordlines; performing repeatedly turn-on and turn-off of the interfering wordlines for a plurality of times; and performing a read operation on the storage units connected to the target wordlines. A write operation is performed on the storage units connected to the interfering wordlines by means of forced current sinking.Type: GrantFiled: March 22, 2022Date of Patent: March 12, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Dong Liu, Xikun Chu, Tianhao Diwu
-
Patent number: 11901025Abstract: A semiconductor memory device includes a memory cell array including memory cell row, each of which includes volatile memory cells, a row hammer management circuit, a repair control circuit and a connection logic. The row hammer management circuit counts access addresses associated with the memory cell rows to store counting values, and determines a hammer address associated with least one of the memory cell rows, which is intensively accessed, based on the counting values. The repair control circuit includes repair controllers, each of which includes a defective address storage, and repairs a defective memory cell row among the memory cell rows. The connection logic connects first repair controllers, which are unused for storing defective addresses, among the plurality of repair controllers, to the row hammer management circuit. The row hammer management circuit uses the first repair controllers as a storage resource to store a portion of the access addresses.Type: GrantFiled: April 28, 2022Date of Patent: February 13, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Seongjin Cho, Jungmin You
-
Patent number: 11901031Abstract: A memory device includes a fail test circuit configured to generate a fail flag indicating whether a failure was detected in a column line, on the basis of internal data outputted from the column line selected according to a column address, when performing a test, and control the fail flag to indicate that the failure was detected in the column line, on the basis of a fail control signal. The memory device also includes a repair information generation circuit configured to generate, from the column address, a repair column address for repairing the column line, on the basis of the fail flag.Type: GrantFiled: February 16, 2022Date of Patent: February 13, 2024Assignee: SK hynix Inc.Inventors: Yong Sun Kim, Mi Hyun Hwang
-
Patent number: 11894093Abstract: A memory device includes a first dynamic random access memory (DRAM) integrated circuit (IC) chip including first memory core circuitry, and first input/output (I/O) circuitry. A second DRAM IC chip is stacked vertically with the first DRAM IC chip. The second DRAM IC chip includes second memory core circuitry, and second I/O circuitry. Solely one of the first DRAM IC chip or the second DRAM IC chip includes a conductive path that electrically couples at least one of the first memory core circuitry or the second memory core circuitry to solely one of the first I/O circuitry or the second I/O circuitry, respectively.Type: GrantFiled: January 4, 2022Date of Patent: February 6, 2024Assignee: Rambus Inc.Inventor: Thomas Vogelsang
-
Patent number: 11894086Abstract: In some aspects of the present disclosure, a memory device is disclosed. In some aspects, the memory device includes a plurality of memory cells arranged in an array, an input/output (I/O) interface connected to the plurality of memory cells to output data signal from each memory cell, and a control circuit. In some embodiments, the control circuit includes a first clock generator to generate a first clock signal and a second clock signal according to an input clock signal and a chip enable (CE) signal and provide the first clock signal to the plurality of memory cells. In some embodiments, the control circuit includes a second clock generator to generate a third clock signal according to the input clock signal and a DFT (design for testability) enable signal. In some embodiments, the control circuit generates an output clock signal according to the second clock signal or the third clock signal.Type: GrantFiled: June 7, 2022Date of Patent: February 6, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jaspal Singh Shah, Atul Katoch
-
Patent number: 11887650Abstract: A semiconductor memory device having a flexible refresh skip area includes a memory cell array including a plurality of rows to store data, a row decoder connected to the memory cell array, a refresh area storage unit to store a beginning address and an end address of a memory area that is to be refreshed in which the memory area that is to be refreshed does not include a refresh skip area having a size is selectively and/or adaptively changed, and a refresh control circuit connected to the row decoder and the refresh area storage unit. The refresh control circuit controls a refresh operation for the area that is to be refreshed and not for the refresh skip area.Type: GrantFiled: March 22, 2023Date of Patent: January 30, 2024Inventors: Uksong Kang, Hoiju Chung