Abstract: In certain aspects, a memory device includes an array of memory cells, an input/output (I/O) circuit, and control logic coupled to the I/O circuit. The array of memory cells includes a plurality of banks including a plurality of main banks and a redundant bank. The I/O circuit is coupled to each pair of adjacent banks of the plurality of banks and configured to direct a piece of data to or from either bank of each pair of adjacent banks. The control circuit is configured to select one bank of each pair of adjacent banks based on bank fail information indicative of a failed main bank of the plurality of main banks. The control circuit is further configured to control the I/O circuit to direct the piece of data to or from the selected bank of each pair of adjacent banks.

Abstract: A local region to be repaired including the fail bit is determined. A preliminary repair LR circuit for repairing the local region to be repaired is determined (S210). A region level of the local region to be repaired is determined (S230) according to the number of available GR circuits other than any replacement GR circuit configured for replacing the preliminary repair LR circuit and the number of available LR circuits. It is controlled, according to the region level of the local region to be repaired, to repair the fail bit by the GR circuit or the LR circuit (S240).

Abstract: Apparatuses and methods including a test circuit in a scribe region between chips are described. An example apparatus includes: a first semiconductor chip and a second semiconductor chip, adjacent to one another; a scribe region between the first and second semiconductor chips; test address pads in the scribe region; and an address decoder circuit in the scribe region. The test address pads receive address signals. The address decoder provides first signals responsive to the address signals from the test address pads.

Abstract: A memory stores dummy data including a first data area having more “0” than “1” of a binary logic and a second data area having more “1” than “0” of the binary logic. An ECC processor detects a first error bit number related to the first data area and a second error bit number related to the second data area. A calculator calculates a relative difference of the first error bit number from the second error bit number. A comparator compares the relative difference with a predetermined value. A corrector corrects a read voltage on the basis of a result of comparison by the comparator.

Abstract: A method and an apparatus for determining a repair location for a redundancy circuit, and a method for repairing an integrated circuit are provided. At least one fail bit of a chip to be repaired is determined. At least one initial repair location for the redundancy circuit is initially assigned according to the at least one fail bit. At least one potential fail line is determined according to the at least one initial repair location. At least one predicted repair location is determined according to the at least one potential fail line. Each of the at least one predicted repair location is a location with a higher probability that a new fail bit appears. At least one final repair location for the redundancy circuit is determined according to the at least one fail bit and the at least one predicted repair location.

Abstract: A predefined data pattern is written using a plurality of values of a memory access parameter. A corresponding value of a data state metric associated with each value of a plurality of values of the memory access operation parameter is measured. An optimal value of the memory access operation parameter is selected from the plurality of values of the memory access operation parameter.

Abstract: Example embodiments provide for a storage device that includes a storage controller including a plurality of analog circuits and at least one nonvolatile memory device including a first region and a second region. The at least one nonvolatile memory device stores user data in the second region and stores trimming control codes in the first region as a compensation data set. The trimming control codes are configured to compensate for offsets of the plurality of analog circuits and are obtained through a wafer-level test on the storage controller. The storage controller, during a power-up sequence, reads the compensation data set from the first region of the at least one nonvolatile memory device, stores the read compensation data set therein, and adjusts the offsets of the plurality of analog circuits based on the stored compensation data set.

Abstract: Systems, methods, and apparatus to evaluate read margin when reading memory cells in a memory device. In one approach, a controller of a memory device applies an initial read voltage of an initial polarity to memory cells. Errors from the read are used to determine whether read retry is needed. If so, a pre-read voltage of an opposite polarity is applied, and errors determined. Based on the errors from applying the pre-read voltage, a polarity is selected for the read retry voltage. The read retry voltage of the selected polarity is then applied to the memory cells.

Abstract: A synapse memory system includes a plurality of synapse memory cells, a write portion, and read drivers. Each synapse memory cells is disposed at cross points of axon lines and dendrite lines and includes a plurality of analog memory devices and each synapse memory cell is configured to store a weight value according to an output level of a write signal. The plurality of analog memory devices is combined to constitute each synapse memory cell. The write portion is configured to write the weight value to each synapse memory cell and includes a write driver and an output controller. The write driver is configured to output the write signal to each synapse memory cell and the output controller is configured to control the output level of the write signal of the write driver. The read drivers are configured to read the weight value stored in the synapse memory cells.

Abstract: A memory device is described. The memory device includes logic circuitry to perform calibrations of resistive network terminations and data drivers of the memory device while the memory device is within a self refresh mode.

Abstract: A leakage detection circuit may include: a comparison circuit configured to compare an input voltage, which changes based on the level of an operation voltage node, to a reference voltage and configured to output a detection signal; and a state decision circuit configured to determine a count value that corresponds to a determination period based on the detection signal and configured to output leakage state information based on the count value.

Abstract: A method for generating a memory built-in self-test circuit includes steps of providing an editable file, wherein the editable file configured to be edited by a user to customize a memory test algorithm; performing a syntax parsing on the editable file to obtain the memory test data, wherein the memory test data being corresponding to the memory test algorithm; and generating the memory built-in self-test circuit based on the memory test data.

Abstract: Disclosed in some examples are methods, systems, devices, memory devices, and machine-readable mediums for using a non-defective portion of a block of memory on which there is a defect on a different portion. Rather than disable the entire block, the system may disable only a portion of the block (e.g., a first deck of the block) and salvage a different portion of the block (e.g., a second deck of the block).

Abstract: A semiconductor device is provided, which contains a memory bank including M primary word lines and R replacement word lines, a row/column decoder, and an array of redundancy fuse elements. A sorted primary failed bit count list is generated in a descending order for the bit fail counts per word line. A sorted replacement failed bit count list is generated in an ascending order of the M primary word lines in an ascending order. The primary word lines are replaced with the replacement word lines from top to bottom on the lists until a primary failed bit count equals a replacement failed bit count or until all of the replacement word lines are used up. Optionally, the sorted primary failed bit count list may be re-sorted in an ascending or descending order of the word line address prior to the replacement process.

Abstract: A memory calibration system includes a memory array having a plurality of memory cells, a sensing circuit coupled to the memory array, and calibration circuitry. A pattern of test data is applied to the memory array in order to generate calibration information based on output provided by the first sensing circuit in response to the application of the pattern of test data to the memory array. The generated calibration information is stored in a distributed manner within memory cells of the memory array. Some of the generated calibration information may be combined with data values stored in the plurality of memory cells as part of one or more operations on the stored data values.

Abstract: An apparatus includes a controller adapted to be coupled to memory components in parallel and configured to provide memory address signals and a controller clock signal to the memory components, a memory enable logic circuit coupled to the controller and adapted to be coupled to the memory components in parallel and configured to provide test-enable signals to the memory components. The test-enable signals enable, with the controller clock signal, the memory components to read locally stored memory values. The apparatus includes a multiplexer adapted to be coupled to the memory components in parallel and configured to receive from the memory components memory signals that include the memory values in respective sequences of the memory clock signals, and a pipeline coupled to the multiplexer and the controller and configured to receive the memory values from the multiplexer and send the memory values to a multiple input signature register of the controller.

Abstract: A TPM with programmable fuses in an SOC includes an on-die RAM storing a blown-fuse count and a TPM state read from off-die NV memory. During initialization, if the blown-fuse count is greater than a TPM state fuse count, a TPM state PIN-attempt-failure count is incremented, thereby thwarting a replay attack. If a PIN satisfies a PIN failure policy, and if a TPM state previously-passed-PIN indicator is set to true, a fuse is blown and the blown-fuse count incremented depending on the PIN being incorrect, but if the TPM state previously-passed-PIN indicator is set to false, a fuse is blown and the blown-fuse count incremented independent of whether the PIN is correct or incorrect. The TPM state fuse count is set equal to the blown-fuse count. If a counter cleared before processing the PIN remains cleared during the next initialization, a fuse voltage cut is detected and a penalty imposed.

Abstract: A memory device which can perform various memory tests without increasing a size of the memory device. The memory device includes: a first pad for receiving external ROM data from a memory controller; a second pad for receiving an external clock signal corresponding to the external ROM data from the memory controller; and a control logic connected to the first pad and the second pad and configured to perform an operation corresponding to the external ROM data in response to the external clock signal in a test mode.

Abstract: Embodiments of a system and method for providing a flexible memory system are generally described herein. In some embodiments, a substrate is provided, wherein a stack of memory is coupled to the substrate. The stack of memory includes a number of vaults. A controller is also coupled to the substrate and includes a number of vault interface blocks coupled to the number of vaults of the stack of memory, wherein the number of vault interface blocks is less than the number of vaults.

Abstract: A method of operating a non-volatile memory device includes performing a first sensing operation on the non-volatile memory device during a first sensing time including a first section, a second section, and a third section. The performing of the first sensing operation includes applying a first voltage level, which is variable according to a first target voltage level, to a selected word line in the first section, applying a second voltage level, which is different from the first voltage level, to the selected word line in the second section, and applying the first target voltage level, which is different from the second voltage level, to the selected word line in the third section. The first voltage level becomes greater as the first target voltage level becomes greater.