Patents Examined by Mohammed A Bashar
  • Patent number: 12223996
    Abstract: Embodiments of the present disclosure relate to an address selection circuit and a control method thereof, and a memory. The address selection circuit includes an address receiving circuit, a row hammer address generation circuit, and a decoding circuit. The address receiving circuit is configured to output a first address output signal in response to a first selection signal, where the first address output signal includes a received regular refresh address signal or an active address signal. The row hammer address generation circuit is configured to: generate a second address output signal and a row hammer address redundancy identifier according to the first selection signal, an actual active address signal, and the first address output signal. The decoding circuit is configured to: generate a target address and the actual active address signal according to the second address output signal and the row hammer address redundancy identifier.
    Type: Grant
    Filed: January 13, 2023
    Date of Patent: February 11, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Xianlei Cao, Xian Fan
  • Patent number: 12217804
    Abstract: A cache read method of a nonvolatile memory device including a plurality of page buffer units and cache latches, each page buffer units having a sensing latch and a sensing node line is provided. The method comprises performing a first on-chip valley search (OVS) read on a selected memory cell using a first sensing node line and a first sensing latch of a first page buffer unit of the plurality of page buffer units; storing first data sensed from the selected memory cell in the first sensing latch, the first data based on a result of the first OVS read; dumping the first data to sensing node lines of at least one page buffer unit, excluding the first page buffer unit, from among the plurality of page buffer units; and performing a second OVS read on the selected memory cell using the first sensing latch.
    Type: Grant
    Filed: October 5, 2022
    Date of Patent: February 4, 2025
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yongsung Cho, Min-Hwi Kim, Hosang Cho
  • Patent number: 12210774
    Abstract: Methods, systems, and devices for controlled and mode-dependent heating of a memory device are described. In various examples, a memory device or an apparatus that includes a memory device may have circuitry configured to heat the memory device. The circuitry configured to heat the memory device may be activated, deactivated, or otherwise operated based on an indication of a temperature (e.g., of the memory device). In some examples, activating or otherwise operating the circuitry configured to heat the memory device may be based on an operating mode (e.g., of the memory device), which may be associated with certain access operations or operational states (e.g., of the memory device). Various operations or operating modes (e.g., of the memory device) may also be based on indications of a temperature (e.g., of the memory device).
    Type: Grant
    Filed: February 22, 2022
    Date of Patent: January 28, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Peter Mayer, Michael Dieter Richter, Martin Brox, Wolfgang Anton Spirkl, Thomas Hein
  • Patent number: 12211573
    Abstract: Systems and methods for filtering data (DQ) signals are described herein. The systems and methods may involve operating a memory to enter a training mode and sending a command to a decoder while the memory is in the training mode. The decoder may generate a command/address waveform in response to the command. The systems and methods may involve transmitting a burst indicator waveform via a first pin of the memory. The burst indicator waveform may be generated by a burst indicator generator of the memory based on the command/address waveform.
    Type: Grant
    Filed: April 20, 2022
    Date of Patent: January 28, 2025
    Assignee: Micron Technology, Inc.
    Inventor: Kai Wang
  • Patent number: 12211572
    Abstract: A semiconductor device includes a multilevel receiver including a signal determiner receiving a plurality of multilevel signals and outputting a result of mutual comparison of the plurality of multilevel signals as an N-bit signal, where N is a natural number equal to or greater than 2. A decoder restores a valid signal among the N-bit signals from the signal determiner to an M-bit data signal, where M is a natural number less than N. A clock generator receives a reference clock signal, generates an input clock signal using the reference clock signal, inputs the input clock signal to the signal determiner, and determines a phase of the input clock signal based on an occurrence probability of an invalid signal not restored to the M-bit data signal among the N-bit signals.
    Type: Grant
    Filed: February 25, 2022
    Date of Patent: January 28, 2025
    Assignees: Samsung Electronics Co., Ltd., Korea University Research & Business Foundation
    Inventors: Kyoungho Kim, Chulwoo Kim, Hyunsu Park, Jincheol Sim
  • Patent number: 12211546
    Abstract: Embodiments relate to the field of semiconductor technology, and proposes a semiconductor device and a memory. The semiconductor device includes a pull-up circuit integration region, a pull-down circuit integration region and a compensation circuit integration region not overlapped with one another. The semiconductor device further includes an output circuit, and the output circuit includes: a pull-up circuit, a pull-down circuit, and a compensation circuit. The pull-up circuit is connected to a signal output line, and the pull-up circuit is positioned in the pull-up circuit integration region. The pull-down circuit is connected to the signal output line, and the pull-down circuit is positioned in the pull-down circuit integration region. The compensation circuit is configured to enhance a drive capability of an output signal from the signal output line, and the compensation circuit is positioned in the compensation circuit integration region.
    Type: Grant
    Filed: September 28, 2022
    Date of Patent: January 28, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Zhonglai Liu
  • Patent number: 12190982
    Abstract: A memory includes: first to Nth register circuits each suitable for receiving and storing a failure address transferred from a memory controller when a corresponding selection signal of first to Nth selection signals is activated, where N is an integer equal to or greater than 2; first to Nth resource latch circuits suitable for storing first to Nth resource signals indicating availability of the first to Nth register circuits, respectively; and a priority selection circuit suitable for activating, when two or more of the first to Nth resource signals are activated, one of selection signals respectively corresponding to the activated resource signals among the first to Nth selection signals.
    Type: Grant
    Filed: January 26, 2022
    Date of Patent: January 7, 2025
    Assignee: SK hynix Inc.
    Inventors: Seung Chan Kim, Keon Ho Lee
  • Patent number: 12190962
    Abstract: In a nonvolatile memory writing device that writes writing data transmitted from the microcomputer to a nonvolatile memory provided outside the microcomputer, the nonvolatile memory is a nonvolatile memory in which writing is protected and the protection is disabled by an electric signal from the microcomputer to the write-protect terminal of the nonvolatile memory, the write-protect terminal is connected to the power supply of the microcomputer, and when the electric signal from the microcomputer to the write-protect terminal is interrupted, the protection is disabled, even when the data is interrupted due to a change in the power supply voltage, it is possible to prevent garbled date due to the write protection signal during the write period of the write data.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: January 7, 2025
    Assignee: Mitsubishi Electric Corporation
    Inventors: Atsushi Kajita, Choji Hirota
  • Patent number: 12176036
    Abstract: A memory device and an operating method thereof adjust a slope of a word line voltage. The memory device includes a memory cell array including a plurality of cell strings, a voltage generating circuit configured to generate a word line voltage provided to a plurality of word lines, and a control logic configured to output a slope control signal adjusting a voltage level variation characteristic of the word line voltage provided from the voltage generating circuit, wherein, during a prepulse period of a read operation of the memory device, a slope of a first word line voltage provided to an edge group including one or more word lines, the edge group adjacent to a string selection line is greater than a slope of a second word line voltage provided to a center group including one or more word lines in a center region.
    Type: Grant
    Filed: August 4, 2022
    Date of Patent: December 24, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sara Choi, Hyunkook Park
  • Patent number: 12176031
    Abstract: A memory device includes a substrate with two or more memory die stacked in a three-dimensional stacked (3DS) configuration. The memory device includes a clock input configured to receive a clock from a host device. The memory device also includes a command input configured to receive command and address bits from the host device. The two or more memory die each include its own plurality of memory cells. Furthermore, each of the two or more memory die include a local control circuitry configured to receive or transmit a divided clock that is based on the clock.
    Type: Grant
    Filed: April 19, 2022
    Date of Patent: December 24, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Vijayakrishna J. Vankayala, Hari Giduturi, Jason M. Brown
  • Patent number: 12170126
    Abstract: A memory device includes a first dynamic random access memory (DRAM) integrated circuit (IC) chip including first memory core circuitry, and first input/output (I/O) circuitry. A second DRAM IC chip is stacked vertically with the first DRAM IC chip. The second DRAM IC chip includes second memory core circuitry, and second I/O circuitry. Solely one of the first DRAM IC chip or the second DRAM IC chip includes a conductive path that electrically couples at least one of the first memory core circuitry or the second memory core circuitry to solely one of the first I/O circuitry or the second I/O circuitry, respectively.
    Type: Grant
    Filed: January 23, 2024
    Date of Patent: December 17, 2024
    Assignee: Rambus Inc.
    Inventor: Thomas Vogelsang
  • Patent number: 12170106
    Abstract: According to one embodiment, a magnetic memory device includes first to third conductor layers, and a three-terminal-type memory cell connected to the first to third conductor layers. The first memory cell includes a fourth conductor layer, a magnetoresistance effect element, a two-terminal-type first switching element, and a two-terminal-type second switching element. The fourth conductor layer includes a first portion connected to the first conductor layer, a second portion connected to the second conductor layer, and a third portion which is connected to the third conductor layer. The magnetoresistance effect element is connected between the third conductor layer and the fourth conductor layer. The first switching element is connected between the second conductor layer and the fourth conductor layer. The second switching element is connected between the first conductor layer and the third conductor layer.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: December 17, 2024
    Assignee: Kioxia Corporation
    Inventors: Yoshiaki Asao, Masatoshi Yoshikawa
  • Patent number: 12154625
    Abstract: The memory device includes an array of memory cells, which are configured to retain multiple bits per memory cell, arranged in a plurality of word lines. A controller is configured to program the memory cells of a selected word line in a first programming pass. The first programming pass includes a plurality of programming pulses, each including the application of a programming voltage Vpgm by the controller to a control gate of the selected word line for a first duration. The controller is also configured to further program the memory cells of the selected word line in a second programming pass. The second programming pass includes a plurality of programming pulses, each of which includes the application of a programming voltage Vpgm by the controller to the control gate of the selected word line for a second duration that is different than the first duration.
    Type: Grant
    Filed: February 8, 2022
    Date of Patent: November 26, 2024
    Inventors: Sujjatul Islam, Ravi Kumar
  • Patent number: 12154644
    Abstract: A test device method includes: setting a core voltage of a memory device to a first voltage value and a peripheral voltage of the memory device to a second voltage value; testing the memory device by accessing the memory device based on the core voltage and the at least one peripheral voltage; adjusting the core voltage to a third voltage value and the at least one peripheral voltage of the memory device to a fourth voltage value; testing the memory device by reading the memory device based on the core voltage and the at least one peripheral voltage; adjusting the core voltage to a fifth voltage value and the at least one peripheral voltage of the memory device to a sixth voltage value; and testing the memory device by reading the memory device based on the core voltage and the at least one peripheral voltage.
    Type: Grant
    Filed: October 31, 2022
    Date of Patent: November 26, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Yao-Chang Chiu
  • Patent number: 12148467
    Abstract: Methods, systems, and devices for decoding for a memory device are described. A decoder may include a first vertical n-type transistor and a second vertical n-type transistor that extends in a third direction relative to a die of a memory array. The first vertical n-type transistor may be configured to selectively couple an access line with a source node and the second n-type transistor may be configured to selectively couple the access line with a ground node. To activate the access line coupled with the first and second vertical n-type transistors, the first vertical n-type transistor may be activated, the second vertical n-type transistor may be deactivated, and the source node coupled with the first vertical n-type transistor may have a voltage applied that differs from a ground voltage.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: November 19, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Paolo Fantini, Lorenzo Fratin, Fabio Pellizzer
  • Patent number: 12148494
    Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) circuit, a fault address register, a scrubbing control circuit and a control logic circuit. The memory cell array includes memory cell rows. The scrubbing control circuit generates scrubbing addresses based on refresh operations performed on the memory cell array. The control logic circuit controls the ECC circuit such that the ECC circuit performs an error detection operation on a plurality of sub-pages in a first memory cell row to count a number of error occurrences, and determines whether to correct a codeword in which an error is detected based on the number of error occurrences. An uncorrected or corrected codeword is written back, and a row address of the first memory cell row may be stored in the fault address register as a row fault address based on the number of error occurrences.
    Type: Grant
    Filed: February 28, 2023
    Date of Patent: November 19, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kiheung Kim, Sanguhn Cha, Junhyung Kim, Sungchul Park, Hyojin Jung, Kyung-Soo Ha
  • Patent number: 12142337
    Abstract: A device including a controller coupled to memory components via a forward data path, and a signature register coupled to the memory components via a backward data path. The controller provides memory address signals and a controller clock signal to the memory components via the forward data path, which includes first circuitry to provide test-enable signals to the memory components that enable the memory components to read stored memory values. The backward data path includes second circuitry to receive from the memory components a set of memory signals and combine them into a combined signal. Each memory signal is associated with a respective one of the memory components and includes at least one stored memory value read from the corresponding memory component. The signature register calculates a test signature based on the combined signal and compares the test signature to an expected signature.
    Type: Grant
    Filed: August 22, 2023
    Date of Patent: November 12, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Nitesh Mishra, Nikita Naresh
  • Patent number: 12142334
    Abstract: A memory device includes a content addressable memory (CAM) block storing a plurality of stored search keys. The memory device further includes control logic that determines a first number of memory cells in at least one string of the CAM block storing one of the plurality of stored search keys, the first number of memory cells storing a first logical value, and stores a calculated parity value representing the first number of memory cells in a page cache associated with the CAM block. The control logic further reads stored parity data from one or more memory cells in the at least one string, the one or more memory cells connected to one or more additional wordlines in the CAM block, and compares the calculated parity value to the stored parity data to determine whether an error is present in the one of the plurality of stored search keys in the CAM block.
    Type: Grant
    Filed: April 26, 2022
    Date of Patent: November 12, 2024
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Tomoko Ogura Iwasaki, Manik Advani, Ramin Ghodsi
  • Patent number: 12136451
    Abstract: A memory system includes a non-volatile memory provided with a plurality of physical blocks, and a controller configured to execute a refresh for the plurality of blocks of the non-volatile memory to rewrite data of a first plurality of blocks to a second plurality of blocks provided in the plurality of blocks. In a first time period from a previous writing to each block provided in the first plurality of blocks to completion of the refresh for each block, the controller is capable of dynamically controlling a time at which the refresh for each block is started.
    Type: Grant
    Filed: August 29, 2022
    Date of Patent: November 5, 2024
    Assignee: KIOXIA CORPORATION
    Inventor: Rei Kasedo
  • Patent number: 12125547
    Abstract: A TPM with programmable fuses in an SOC includes an on-die RAM storing a blown-fuse count and a TPM state read from off-die NV memory. During initialization, if the blown-fuse count is greater than a TPM state fuse count, a TPM state PIN-attempt-failure count is incremented, thereby thwarting a replay attack. If a PIN satisfies a PIN failure policy, and if a TPM state previously-passed-PIN indicator is set to true, a fuse is blown and the blown-fuse count incremented depending on the PIN being incorrect, but if the TPM state previously-passed-PIN indicator is set to false, a fuse is blown and the blown-fuse count incremented independent of whether the PIN is correct or incorrect. The TPM state fuse count is set equal to the blown-fuse count. If a counter cleared before processing the PIN remains cleared during the next initialization, a fuse voltage cut is detected and a penalty imposed.
    Type: Grant
    Filed: July 13, 2023
    Date of Patent: October 22, 2024
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Ling Tony Chen, Felix Domke, Ankur Choudhary, Bradley Joseph Litterell