Patents Examined by Mohammed A Bashar
  • Patent number: 10430090
    Abstract: According to one embodiment, a semiconductor device includes a non-volatile memory, a temperature measurement circuit that measures a temperature of the non-volatile memory, and a controller. The controller also writes information about the temperature which is measured by the temperature measurement circuit in the non-volatile memory together when writing data in the non-volatile memory. Further, the controller performs write-back processing of writing data, which is written at a temperature in a rewriting temperature range, back when the temperature measured by the temperature measurement circuit is not in the rewriting temperature range.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: October 1, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Daisuke Nakata, Yu Muraki
  • Patent number: 10430116
    Abstract: Devices and techniques for correcting for power loss in NAND memory devices are disclosed herein. The NAND memory devices may comprise a number of physical pages. For example, a memory controller may detect a power loss indicator at the NAND flash memory. The memory controller may identify a last-written physical page and determine whether the last-written physical page comprises more than a threshold number of low-read-margin cells. If the last-written physical page comprises more than the threshold number of low-read-margin cells, the memory controller may provide a programming voltage to at least the low-read-margin cells.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: October 1, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Michael G. Miller, Kishore Kumar Muchherla, Harish Singidi, Sampath Ratnam, Renato C. Padilla, Jr., Gary F. Besinga, Peter Sean Feeley
  • Patent number: 10424361
    Abstract: A method of generating a random number from an electronic circuit memory and/or a system with the electronic circuit memory. The memory comprises a block of ferroelectric two transistor, two capacitor (2T-2C), memory cells. The method comprises: (i) first, writing a predetermined programming pattern to the block cells in a one transistor, one-capacitor (1T-1C) mode, thusly writing, per cell, a same data state to both a first and second sub-cell of the cell; (ii) second, reading the cells in a 2T-2C mode to generate a random number comprising a random bit from each of the cells; (iii) third, restoring the random number into the cells in a 2T-2C mode, thusly writing, per cell, a complementary data state to both a first and second sub-cell of the cell, responsive to a respective random number bit; and fourth, imprinting the random number in each cell in the block.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: September 24, 2019
    Assignee: Texas Instruments Incorporated
    Inventors: John Anthony Rodriguez, Richard Allen Bailey
  • Patent number: 10418084
    Abstract: Methods, systems, and devices for operating a memory cell or memory cells are described. Cells of a memory array may be pre-written, which may include writing the cells to one state while a sense component is isolated from digit lines of the array. Read or write operations may be executed at the sense component while the sense component is isolated, and the cell may be de-isolated (e.g., connected to the digit lines) when write operations are completed. The techniques may include techniques accessing a memory cell of a memory array, isolating a sense amplifier from a digit line of the memory array based at least in part on the accessing of the cell, firing the sense amplifier, and pre-writing the memory cell of the memory array to a second data state while the sense amplifier is isolated. In some examples, the memory cell may include a ferroelectric memory cell.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: September 17, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Scott James Derner, Christopher John Kawamura
  • Patent number: 10418118
    Abstract: According to one embodiment, a memory device comprises a first memory cell configured to store data, a first word line connected to the first memory cell, a first circuit configured to supply a voltage to the first word line, a second circuit configured to control the first circuit, and a sequencer configured to control the first circuit and the second circuit. The sequencer, when data is written to the first memory cell, determines whether a condition is satisfied or not. The sequencer causes the second circuit to generate a first voltage, when the sequencer determines that the condition is not satisfied, and causes the second circuit to generate a second voltage which is higher than the first voltage, when the sequencer determines that the condition is satisfied.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: September 17, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Hiroki Date
  • Patent number: 10418072
    Abstract: Memories may include a first bi-directional select device connected between a first access line and a second access line, and a plurality of memory cells, each memory cell of the plurality of memory cells connected between the second access line and a respective third access line of a plurality of third access lines. Each memory cell of the plurality of memory cells comprises a respective second bi-directional select device, of a plurality of second bi-directional select devices, and a respective programmable element, of a plurality of programmable elements, connected in series.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: September 17, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Aaron Yip
  • Patent number: 10418085
    Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. An electronic memory device may include a plurality of plate portions separated by a plurality of segmentation lines, which may be oriented in a plane parallel to rows of a memory array or columns of the memory array, or both. The segmented plate may be employed instead of a single plate for the array. The one or more plate portions may be energized during access operations of a ferroelectric cell in order to create a voltage different across the cell or to facilitate changing the charge of the cell. Each of the plate portions may include one or more memory cells. The memory cells on a plate portion may be read from or written to after the plate portion is activated by a plate driver.
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: September 17, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Tae H. Kim, Corrado Villa
  • Patent number: 10402314
    Abstract: A semiconductor memory system and an operating method thereof include a controller configured to perform macro management; and a memory device including Nand pages, counters, a self-management component, and devoted memories, wherein the memory device is coupled and controlled by the controller, the Nand pages contains data corresponding to commands received from the controller, the counters are configured to track operation information corresponding to the Nand pages in accordance with the commands, the devoted memories are configured to record recovery information, and the self-management component configured to perform micro management in accordance at least in part with the operation information or the recovery information.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: September 3, 2019
    Assignee: SK hynix Inc.
    Inventor: Yungcheng Lo
  • Patent number: 10403353
    Abstract: Devices, systems, and methods for reducing noise couplings between propagation lines for size efficiency. In one embodiment, a memory device is provided, comprising a memory array and an input/output (I/O) circuit. The I/O circuit can include a first plurality of global data lines and a second plurality of global data lines. The second plurality of global data lines are directly interleaved between the first plurality of global date lines and are configured to shield the first plurality of global data lines. In some embodiments, the first plurality of global data lines are shorter in length than the second plurality of global data lines and are switched before the second plurality of global data lines are switched.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: September 3, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Michael V. Ho, Ravi Kiran Kandikonda
  • Patent number: 10402247
    Abstract: A non-volatile memory includes a page buffer array in which page buffers are arranged in a matrix form. A method of operating the non-volatile memory includes selecting columns from among multiple columns of the page buffer array, and counting fail bits stored in page buffers included in the selected columns.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: September 3, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bong-Soon Lim, Sang-Hyun Joo, Kee-Ho Jung
  • Patent number: 10403367
    Abstract: Provided herein may be a semiconductor memory device and a method of operating the same. The semiconductor memory device may include a plurality of pages each including a plurality of memory cells, peripheral circuits configured to perform a program operation of a selected page among the plurality of pages and a control logic configured to control the peripheral circuits such that a main program operation is performed on the selected page and, when the main program operation is completed, a compensation program operation is performed on memory cells having lower threshold voltage retention characteristics compared to remaining memory cells, among the memory cells included in the selected page.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: September 3, 2019
    Assignee: SK hynix Inc.
    Inventors: Hye Lyoung Lee, Bong Hoon Lee, Chan Lim
  • Patent number: 10395752
    Abstract: The present disclosure relates to a structure which includes a twin-cell memory which includes a first device and a second device and which is configured to store data which corresponds to a threshold voltage difference between the first device controlled by a first wordline and the second device controlled by a second wordline.
    Type: Grant
    Filed: October 11, 2017
    Date of Patent: August 27, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: John A. Fifield, Eric D. Hunt-Schroeder, Darren L. Anand
  • Patent number: 10388354
    Abstract: Methods, systems, and devices for operating a memory cell or memory cells are described. Cells of a memory array may be pre-written, which may include writing the cells to one state while a sense component is isolated from digit lines of the array. Read or write operations may be executed at the sense component while the sense component is isolated, and the cell may be de-isolated (e.g., connected to the digit lines) when write operations are completed. The techniques may include techniques accessing a memory cell of a memory array, isolating a sense amplifier from a digit line of the memory array based at least in part on the accessing of the cell, firing the sense amplifier, and pre-writing the memory cell of the memory array to a second data state while the sense amplifier is isolated. In some examples, the memory cell may include a ferroelectric memory cell.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: August 20, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Scott James Derner, Christopher John Kawamura
  • Patent number: 10388370
    Abstract: An electronic memristive device that has a complementary analog reconfigurable memristive bidirectional resistive switch. The device has a memristive layer sequence having a BFTO/BFO/BFTO three-ply layer and two electrodes. Titanium traps are arranged in the BFTO interfaces. As a result of mobile acid vacancies, the potential barriers at the interfaces of the electrodes with respect to the memristive layer sequence are in flexible form. By applying voltage pulses, the acid vacancies can be shifted from the interface with respect to the first electrode to the interface with respect to the second electrode, with raising of the potential barrier at one electrode bringing about complementary lowering of the potential barrier of the other electrode. The method for operating the device proposes adapted writing processes that use the overlaying of writing pulse sequences to achieve stipulation of a state pair of complementary resistor states.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: August 20, 2019
    Assignee: Helmholtz-Zentrum Dresden—Rossendorf e.V.
    Inventors: Heidemarie Schmidt, Kefeng Li, Ilona Skorupa, Nan Du
  • Patent number: 10388345
    Abstract: According to one embodiment, a memory device includes a preamplifier configured to execute a first read in which a first current relating to a memory cell is passed through a first path and a second current relating to the first current is passed through a second path, to generate a first voltage, to write first data to the memory cell; and to execute a second read in which a third current relating to the memory cell with the first data written thereto is passed through the first path and a fourth current relating to the third current is passed through the second path, to generate a second voltage; and a sense amplifier configured to determine data stored in the memory cell during execution of the first read based on the first voltage and the second voltage.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: August 20, 2019
    Assignee: TOSHIBA MEMORY CORORATION
    Inventors: Kosuke Hatsuda, Yoshiaki Osada, Yorinobu Fujino, Jieyun Zhou
  • Patent number: 10387075
    Abstract: A buffer circuit includes a primary interface, a secondary interface, and an encoder/decoder circuit. The primary interface is configured to communicate on an n-bit channel, wherein n parallel bits on the n-bit channel are coded using data bit inversion (DBI). The secondary interface is configured to communicate with a plurality of integrated circuit devices on a plurality of m-bit channels, each m-bit channel transmitting m parallel bits without using DBI. And the encoder/decoder circuit is configured to translate data words between the n-bit channel of the primary interface and the plurality of m-bit channels of the secondary interface.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: August 20, 2019
    Assignee: Rambus Inc.
    Inventor: Scott C. Best
  • Patent number: 10380045
    Abstract: This technology provides an electronic device and a method for fabricating the same. An electronic device in accordance with an implementation of this document may include a semiconductor memory, wherein the semiconductor memory may include: one or more variable resistance elements each exhibiting different resistance states for storing data, wherein each variable resistance element may include: a Magnetic Tunnel Junction (MTJ) structure including a free layer having a changeable magnetization direction, a pinned layer having a fixed magnetization direction and a tunnel barrier layer interposed between the free layer and the pinned layer; a seed layer disposed under the MTJ structure to facilitate a growth of the pinned layer or the free layer; and an amorphous metallic carbon layer disposed under the seed layer.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: August 13, 2019
    Assignee: SK hynix Inc.
    Inventor: Joo-Young Moon
  • Patent number: 10366733
    Abstract: Cache mode for word lines where the cache mode utilizes an internal timer for a memory cell to disable connection of a voltage to a transistor of a word line driver of the memory cell before an end of a specified end of period. By early disconnection, the local controls of the memory cell may provide additional time to settle after disconnection of the voltage without interfering with operations (e.g., read, write, activate) of the memory cell, since the internal timer may be programmed to be greater than or equal to a worst case scenario for the operations.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: July 30, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Gregg D. Wolff
  • Patent number: 10366734
    Abstract: A system and method for efficient power, performance and stability tradeoffs of memory accesses under a variety of conditions are described. A system management unit in a computing system interfaces with a memory and a processing unit, and uses boosting of word line voltage levels in the memory to assist write operations. The computing system supports selecting one of multiple word line boost values, each with an associated cross-over region. A cross-over region is a range of operating voltages for the memory used for determining whether to enable or disable boosting of word line voltage levels in the memory. The system management unit selects between enabling and disabling the boosting of word line voltage levels based on a target operational voltage for the memory and the cross-over region prior to updating the operating parameters of the memory to include the target operational voltage.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: July 30, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Alexander W. Schaefer, Ravi T. Jotwani, Samiul Haque Khan, David Hugh McIntyre, Stephen Victor Kosonocky, John J. Wuu, Russell Schreiber
  • Patent number: 10360970
    Abstract: An apparatus includes a plurality of termination points and a clock mesh network. The termination points may be configured to send/receive timing signals. Each of the termination points may comprise an inductor. The clock mesh network may be configured to provide a path to transmit the timing signals from a clock source to a plurality of components and implement a condition using the inductors. The inductors for each of the termination points may be implemented to meet the condition. Values for the inductors may be determined based on characteristics of the clock mesh network. The condition may prevent power loss.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: July 23, 2019
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventor: David Chang