Patents Examined by Mohammed A Bashar
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Patent number: 10748594Abstract: Methods, systems, and devices for enabling fast pulse operation are described. A threshold voltage of a selection component and a requisite duration for a voltage applied to a selection component to reach a threshold voltage in response to a voltage generated by an external source may be determined. The threshold voltage may correspond to a voltage at which the selection component is configured to release electric charge. A voltage may then be generated and applied to an access line that is in electronic communication with the selection component and a memory cell for at least the requisite duration. Electric charge may be stored at the selection component during the requisite duration and transferred to memory cell after the requisite duration.Type: GrantFiled: February 13, 2018Date of Patent: August 18, 2020Assignee: Micron Technology, Inc.Inventors: Gurtej S. Sandhu, Wayne I. Kinney
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Patent number: 10747468Abstract: A buffer circuit includes a primary interface, a secondary interface, and an encoder/decoder circuit. The primary interface is configured to communicate on an n-bit channel, wherein n parallel bits on the n-bit channel are coded using data bit inversion (DBI). The secondary interface is configured to communicate with a plurality of integrated circuit devices on a plurality of m-bit channels, each m-bit channel transmitting m parallel bits without using DBI. And the encoder/decoder circuit is configured to translate data words between the n-bit channel of the primary interface and the plurality of m-bit channels of the secondary interface.Type: GrantFiled: August 19, 2019Date of Patent: August 18, 2020Assignee: Rambus Inc.Inventor: Scott C. Best
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Patent number: 10748621Abstract: A memory device includes a memory cell array including a plurality of word lines, at least one select line provided above the plurality of word lines, and a channel region passing through the plurality of word lines and the at least one select line, the plurality of word lines and the channel region providing a plurality of memory cells, and a controller. The controller is to store data in a program memory cell among the plurality of memory cells by sequentially performing a first programming operation and a second programming operation, and to determine a program voltage input to a program word line connected to the program memory cell, in the first programming operation, based on information regarding the program memory cell.Type: GrantFiled: August 24, 2018Date of Patent: August 18, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Dong Hun Kwak, Sang Wan Nam, Chi Weon Yoon
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Patent number: 10741265Abstract: The present invention relates to a flash memory cell with only four terminals and decoder circuitry for operating an array of such flash memory cells. The invention allows for fewer terminals for each flash memory cell compared to the prior art, which results in a simplification of the decoder circuitry and overall die space required per flash memory cells. The invention also provides for the use of high voltages on one or more of the four terminals to allow for read, erase, and programming operations despite the lower number of terminals compared to prior art flash memory cells.Type: GrantFiled: March 16, 2018Date of Patent: August 11, 2020Assignee: SILICON STORAGE TECHNOLOGY, INC.Inventors: Hieu Van Tran, Anh Ly, Thuan Vu
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Patent number: 10714178Abstract: The disclosure provides a novel system of storing information using a charged polymer, e.g., DNA, the monomers of which correspond to a machine-readable code, e.g., a binary code, and which can be synthesized and/or read using a novel nanochip device comprising nanopores; novel methods and devices for synthesizing oligonucleotides in a nanochip format; novel methods for synthesizing DNA in the 3? to 5? direction using topoisomerase; novel methods and devices for reading the sequence of a charged polymer, e.g., DNA, by measuring capacitive variance as the polymer passes through the nanopore; and further provides compounds, compositions, methods and devices useful therein.Type: GrantFiled: July 17, 2019Date of Patent: July 14, 2020Assignee: IRIDIA, INC.Inventors: Paul F. Predki, Maja Cassidy
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Patent number: 10714493Abstract: Embodiments of 3D memory devices with a semiconductor plug protected by a dielectric layer and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack including a plurality of interleaved conductor layers and dielectric layers on the substrate, and a memory string extending vertically through the memory stack. The memory string includes a semiconductor plug in a lower portion of the memory string, a protective dielectric layer on the semiconductor plug, and a memory film above the protective dielectric layer and along a sidewall of the memory string.Type: GrantFiled: November 16, 2018Date of Patent: July 14, 2020Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Haohao Yang, Yong Zhang, EnBo Wang, Ruo Fang Zhang, Fushan Zhang, Qianbin Xu
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Patent number: 10714150Abstract: Embodiments of a system and method for providing a flexible memory system are generally described herein. In some embodiments, a substrate is provided, wherein a stack of memory is coupled to the substrate. The stack of memory includes a number of vaults. A controller is also coupled to the substrate and includes a number of vault interface blocks coupled to the number of vaults of the stack of memory, wherein the number of vault interface blocks is less than the number of vaults.Type: GrantFiled: February 19, 2019Date of Patent: July 14, 2020Assignee: Micron Technology, Inc.Inventors: Joe M. Jeddeloh, Brent Keeth
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Patent number: 10706944Abstract: A method of operating a memory controller includes classifying a plurality of memory cells in an erase state into a plurality of groups, based on erase state information about the plurality of memory cells in the erase state; setting at least one target program state for at least some memory cells from among memory cells included in at least one of the plurality of groups; and programming the at least some memory cells for which the at least one target program state has been set, to a program state other than the at least one target program state from among the plurality of program states.Type: GrantFiled: January 21, 2020Date of Patent: July 7, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Hye-Jeong So, Dong-Hwan Lee, Seong-Hyeog Choi, Eun-Chu Oh, Jun-Jin Kong, Hong-Rak Son, Pil-Sang Yoon
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Patent number: 10706897Abstract: Apparatuses and methods for read threshold voltage selection are provided. One example method can include setting a first soft read threshold voltage and a second soft read threshold voltage based on a difference between a first number of memory cells that are read as being programmed to a first state when read using a first threshold voltage and a second number of memory that are read as being programmed to the first state when read using another threshold voltage.Type: GrantFiled: July 2, 2019Date of Patent: July 7, 2020Assignee: Micron Technology, Inc.Inventor: Chandra C. Varanasi
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Patent number: 10705908Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit, an error log register and a control logic circuit. The memory cell array includes a plurality of memory bank arrays and each of the memory bank arrays includes a plurality of pages. The control logic circuit is configured to control the error correction circuit to perform an ECC decoding sequentially on some of the pages designated at least one access address for detecting at least one bit error, in response to a first command received from a memory controller. The control logic circuit performs an error logging operation to write page error information into the error log register and the page error information includes a number of error occurrence on each of the some pages determined from the detecting.Type: GrantFiled: June 22, 2018Date of Patent: July 7, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hoi-Ju Chung, Sang-Uhn Cha, Ho-Young Song, Hyun-Joong Kim
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Patent number: 10706941Abstract: Techniques are described for programming memory cells with reduced widening of the threshold voltage distributions. Bit line voltages are adjusted during verify tests for memory cells assigned to the upper data state in a pair of adjacent data states which are concurrently verified. An elevated bit line voltage is applied and then stepped up in successive program loops. A lower, fixed bit line voltage is used for verifying the lower data state in the pair of adjacent data states. In one option, the step size increases progressively over the program loops. In another option, the minimum level of the elevated bit line voltage is lower for higher data states. In another option, the minimum level of the elevated bit line voltage is set as a function of data states, program-erase cycles and/or temperature.Type: GrantFiled: April 1, 2019Date of Patent: July 7, 2020Assignee: SanDisk Technologies LLCInventors: Ching-Huang Lu, Vinh Diep, Zhengyi Zhang
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Patent number: 10692561Abstract: A semiconductor memory device includes a cell array that includes a plurality of DRAM cells to store data, and refresh control logic that refreshes the plurality of DRAM cells depending on access scenario information provided from an outside. The refresh control logic determines a refresh time of the plurality of DRAM cells with reference to the access scenario information and a retention characteristic of the plurality of DRAM cells and refreshes the plurality of DRAM cells depending on the determined refresh time.Type: GrantFiled: July 11, 2018Date of Patent: June 23, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Min-soo Jang, Eunsung Seo, Seungjun Bae
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Patent number: 10692560Abstract: A memory device is described. The memory device includes logic circuitry to perform calibrations of resistive network terminations and data drivers of the memory device while the memory device is within a self refresh mode.Type: GrantFiled: June 6, 2018Date of Patent: June 23, 2020Assignee: Intel CorporationInventors: Christopher E. Cox, Bill Nale
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Patent number: 10685952Abstract: A memory circuit includes a first memory cell and a second memory adjacent to the first memory cell. The first memory cell includes a first word line strapping line segment electrically coupled with a pass device of the first memory cell; and a second word line strapping line segment. The second memory cell includes a first word line strapping line segment; and a second word line strapping line segment electrically coupled with a pass device of the second memory cell. The first word line strapping line segment of the first memory cell and the first word line strapping line segment of the second memory cell are connected with each other at a first interconnection layer. The second word line strapping line segment of the first memory cell and the second word line strapping line segment of the second memory cell are connected with each other at the first interconnection layer.Type: GrantFiled: December 5, 2019Date of Patent: June 16, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Jhon Jhy Liaw
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Patent number: 10672442Abstract: Provided are a voltage control circuit including an assist circuit and a memory device including the voltage control circuit. The memory device includes: a volatile memory cell array, which is connected to a plurality of word lines and includes a memory cell including at least one transistor; and an assist circuit, which is connected to at least one of the plurality of word lines and adjusts a driving voltage level of each of the plurality of word lines, wherein the assist circuit includes a diode N-channel metal oxide semiconductor (NMOS) transistor having a gate and a drain connected to each other.Type: GrantFiled: August 29, 2019Date of Patent: June 2, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang-yeop Baeck, Siddharth Gupta, In-hak Lee, Jae-seung Choi, Tae-hyung Kim, Dae-young Moon, Dong-wook Seo
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Patent number: 10672475Abstract: Embodiments include nonvolatile a memory (NVM) device that can be configured for logic switching and/or digital computing. For example, embodiments of the NVM device can be configured as any one or combination of a memory cell, a D flip flop (DFF), a Backup and Restore circuit (B&R circuit), and/or a latch for a DFF. Any of the NVM devices can have a Fe field effect transistors (FeFET) configured to exploit the IDS?VG hysteresis of the steep switch at low voltage for logic memory synergy. The FeFET-based devices can be configured to include a wide hysteresis, a steep hysteresis edge, and high ratio between the two IDS states at VG=0.Type: GrantFiled: September 24, 2019Date of Patent: June 2, 2020Assignee: The Penn State Research FoundationInventors: Xueqing Li, Sumitha George, John Sampson, Sumeet Gupta, Suman Datta, Vijaykrishnan Narayanan, Kaisheng Ma
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Patent number: 10665306Abstract: Techniques are disclosed for reducing an injection type of program disturb in a memory device. In one aspect, a discharge operation is performed at the start of a program loop. This operation discharges residue electrons from the channel region on the source side of the selected word line, WLn, to the channel region on the drain side of WLn. As a result, in a subsequent channel pre-charge operation, the residue electrons can be more easily removed from the channel. The discharge operation involves applying a voltage pulse to WLn and a first set of drain-side word lines which is adjacent to WLn. The remaining unselected word lines may be held at ground during the voltage pulse.Type: GrantFiled: April 8, 2019Date of Patent: May 26, 2020Assignee: SanDisk Technologies LLCInventors: Hong-Yan Chen, Henry Chin
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Patent number: 10665302Abstract: An operating method of a nonvolatile memory device including a page buffer array in which a plurality of page buffers are arranged in a matrix form includes counting fail bits stored in the page buffers included in first columns determined based on an operation mode from among a plurality of columns of the page buffer array, and determining whether or not a program has passed with respect to memory cells to which the page buffer array is connected, based on a count result corresponding to a number of the fail bits and a reference count determined based on the operation mode.Type: GrantFiled: March 11, 2019Date of Patent: May 26, 2020Assignee: Samsung Electroncis Co., Ltd.Inventors: Bong-Soon Lim, Sang-Hyun Joo, Kee-Ho Jung
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Patent number: 10665276Abstract: A semiconductor device may include a first internal command generation circuit, a first DLL circuit, a second internal command generation circuit, and a second DLL circuit. The first internal command generation circuit may generate a first delay command in response to a first external command, a first latency, a first clock, a first delay control signal, and a second clock. The first DLL circuit may generate the first delay control signal and the first second clock in response to the first clock. The second internal command to generation circuit may generate a second delay command in response to a second external command, a second latency, the first clock, a second delay control signal, and a third clock. The second DLL circuit may generate the second delay control signal and the third clock in response to the first clock.Type: GrantFiled: December 14, 2018Date of Patent: May 26, 2020Assignee: SK hynix Inc.Inventors: Gyu Tae Park, Young Suk Seo
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Patent number: 10658015Abstract: A semiconductor device includes a shift register and a control signal generation circuit. The shift register generates shifted pulses, wherein a number of the shifted pulses is controlled according to a mode of a burst length. The control signal generation circuit generates a control signal for setting a burst operation period according to a period during which the shifted pulses are created. The burst operation period is a period during which a burst operation is performed.Type: GrantFiled: December 6, 2018Date of Patent: May 19, 2020Assignee: SK hynix Inc.Inventors: Geun Ho Choi, Min Su Park, Sun Myung Choi
