Abstract: A method of operating a memory controller includes classifying a plurality of memory cells in an erase state into a plurality of groups, based on erase state information about the plurality of memory cells in the erase state; setting at least one target program state for at least some memory cells from among memory cells included in at least one of the plurality of groups; and programming the at least some memory cells for which the at least one target program state has been set, to a program state other than the at least one target program state from among the plurality of program states.

Abstract: A non-volatile memory module includes an input/output buffer coupled to first and second signal transmission paths, and control circuitry coupled to the input/output buffer, the control circuitry being configured to receive a first signal on the first signal transmission path, receive a second signal on the second signal transmission path, determine a delay between the first signal and the second signal, generate a delay mismatch value based on the determined delay, and transmit the delay mismatch value on one or more signal transmission paths coupled to the input/output buffer.

Abstract: A data storage device includes a memory device and a controller. The memory device includes at least an MLC block. The MLC block includes a plurality of physical pages. The controller is coupled to the memory device. When the controller determines that a sudden power-off has occurred during a previous write operation for writing data onto the MLC block, the controller finds a predetermined page that has been attacked by the sudden power-off, double programs the predetermined page and a first page that is directly related to the predetermined page and dummy programs a plurality of second pages that are indirectly related to the predetermined page.

Abstract: A method is described. The method includes configuring first register space to establish ODT values of a data strobe signal trace of a DDR data bus. The method also includes configuring second register space to establish ODT values of a data signal trace of the DDR data bus. The ODT values for the data strobe signal trace are different than the ODT values for the data signal trace. The ODT values for the data strobe signal do not change when consecutive write operations of the DDR bus write to different ranks of a same DIMM.

Abstract: Some embodiments include an integrated assembly having a capacitor. The capacitor has a storage node configured as an upwardly-opening container shape. The container shape has a first side surface and a second side surface. The first and second side surfaces are along outer edges of the container shape and are in opposing relation to one another. The second side surface has a lower portion vertically overlapped by the first side surface, and has an upper portion which is not vertically overlapped by the first side surface. A middle-level lattice is adjacent to the first side surface and supports the first side surface. A higher-level lattice is adjacent to the second side surface and supports the second side surface. Some embodiments include integrated memory (e.g., DRAM).

Abstract: A matrix-vector multiplication device includes a memory crossbar array with row lines, column lines, and junctions. Each junction comprises a programmable resistive element and an access element. A signal generator is configured to apply programming signals to the resistive elements to program conductance values for the matrix-vector multiplication and a readout circuit is configured to apply read voltages to the row lines and to read out current values of the column lines. Control circuitry is configured to control the signal generator and the readout circuit and to select, via the access terminals, a plurality of resistive elements in parallel according to a predefined selection scheme which applies the signals and/or the read voltages in parallel to resistive elements which do not share the same row and column line and applies the programming signals and/or the read voltages to at most one resistive element per row line and column line.

Abstract: A memory circuit includes a first memory cell and a second memory adjacent to the first memory cell. The first memory cell includes a first word line strapping line segment electrically coupled with a pass device of the first memory cell; and a second word line strapping line segment. The second memory cell includes a first word line strapping line segment; and a second word line strapping line segment electrically coupled with a pass device of the second memory cell. The first word line strapping line segment of the first memory cell and the first word line strapping line segment of the second memory cell are connected with each other at a first interconnection layer. The second word line strapping line segment of the first memory cell and the second word line strapping line segment of the second memory cell are connected with each other at the first interconnection layer.

Abstract: Methods and apparatuses are provided for driver circuits without voltage level shifters. An example apparatus includes a semiconductor device including a row decoder circuit that includes a driver circuit and a switching circuit. The driver circuit is configured to receive an input signal having a first logical value, a first voltage signal, and a configurable power signal. The driver circuit is further configured to provide an output signal having the first logical value based on the first signal having the first logical value. A voltage level of the input signal is based on the first voltage signal and a voltage level the output signal is based on the configurable voltage signal. The switching circuit is configured to receive the first voltage signal and a second voltage signal and to provide the configurable voltage signal having a voltage level of one of the first voltage signal or the second voltage signal.

Abstract: A memory control circuit includes an input circuit that receives data to be written to a storage having multiple nonvolatile memory cells, and a control circuit, when a second number of bits that are included in a first bit string and having a first number of bits and have a second logical value different from a first logical value equal to initial values stored in the multiple nonvolatile memory cells is equal to or smaller than a first threshold, writes the first bit string and the first additional value to the storage, and that associates, when the second number of the bits is larger than a second threshold larger than the first threshold, a second bit string obtained by reversing logical values of all the bits of the first bit string with a second additional value and writes the second bit string and the second additional value to the storage.

Abstract: A novel semiconductor device or a highly reliable semiconductor device is provided. The on/off state of a transistor which functions as a switch for writing data is controlled using the potential of a potential hold portion. The potential of the potential hold portion is controlled using a plurality of capacitors, whereby both a positive potential and a negative potential can be held in the potential hold portion. Accordingly, deterioration of the transistor which functions as the switch for writing data can be prevented and the characteristics of the transistor can be maintained. Therefore, the highly reliable semiconductor device can be provided.

Abstract: Various embodiments comprise apparatuses such as those having a block of memory divided into sub-blocks that share a common data line. Each of the sub-blocks of the block of memory corresponds to a respective one of a number of segmented sources. Each of the segmented sources is electrically isolated from the other segmented sources of the block of memory. Additional apparatuses and methods of operation are described.

Abstract: The present disclosure includes apparatuses and methods for data movement. An example apparatus includes a memory device that includes a plurality of subarrays of memory cells and sensing circuitry coupled to the plurality of subarrays. The sensing circuitry includes a sense amplifier and a compute component. The memory device includes a latch selectably coupled to a column of the memory cells and configured to store a data value moved from the sensing circuitry. The memory device includes a controller configured to direct movement of the data value from the sensing circuitry to the latch.

Abstract: A system includes a memory device storing a set of start voltage values, wherein the set of start voltage values each represent voltage levels used to initially store charges in performing operations to corresponding one or more memory locations of the memory device; and a processing device, operatively coupled to the memory device, to: determine whether a quantity of start voltage values in the set of start voltage values stored in the memory device meets a threshold; modify the set of start voltage values stored in the memory device to remove one or more start voltage values from the set in response to a determination that the quantity of start voltage values in the set meets the threshold; and add a new start voltage value to the modified set of start voltage values.

Abstract: Methods and systems that may employ adjustments to the latencies in the input circuitry to reduce the latency during initialization period and to prevent undesired effects from metastability are provided. Disclosed systems may employ adjustable delays during a signal training process to cause adjustments in the timing of the host that will reduce latencies during write cycles. Certain systems may further reduce latencies by employing input logic circuitry that produces a valid, consistent signal from the bidirectional connection, such as a gate, and preventing metastability in input circuitry altogether. Such circuitry allows bypassing of initialization periods to stabilize the input, and allows further reduction of the initialization.

Abstract: Embodiments include nonvolatile a memory (NVM) device that can be configured for logic switching and/or digital computing. For example, embodiments of the NVM device can be configured as any one or combination of a memory cell, a D flip flop (DFF), a Backup and Restore circuit (B&R circuit), and/or a latch for a DFF. Any of the NVM devices can have a Fe field effect transistors (FeFET) configured to exploit the IDS-VG hysteresis of the steep switch at low voltage for logic memory synergy. The FeFET-based devices can be configured to include a wide hysteresis, a steep hysteresis edge, and high ratio between the two IDS states at VG=0.

Abstract: A magnetic memory element for Magnetic Random Access Memory. The magnetic memory element has improved reference layer magnetic pinning. The magnetic memory element has a magnetic free layer, a magnetic reference layer and a non-magnetic barrier layer located between the magnetic free layer and the magnetic reference layer. The magnetic reference layer has a magnetic moment that is pinned in a perpendicular orientation through exchange coupling with a synthetic antiferromagnetic structure that includes first and second magnetic structures and an antiferromagnetic exchange coupling structure located between the first and second magnetic structures. The antiferromagnetic exchange coupling structure includes a layer of Ru located between first and second layers of Pt. The Pt layers in the antiferromagnetic exchange coupling structure advantageously increases the magnetic proximity effect at both Ru interfaces, which extends the exchange coupling range of the antiferromagnetic exchange coupling layer.

Abstract: The reliability of a low-power SRAM device fabricated in a small process node can be improved by using an SRAM cell with circuitry that reduces or eliminates contention between pull-up and pull-down devices during write operations. In the first stage of a write operation, the node N that stores the SRAM cell's bit value may be decoupled from a power-supply rail (“Rail 1”) by deactivating one type of “pulling” device (e.g., the type of pulling device that can pull the voltage of node N toward the voltage of Rail 1). Using pulling device(s) of the opposite type, the voltage of node N may then be pulled toward the voltage of the other power-supply rail (“Rail 2”). In this manner, the new SRAM cell may reduce or eliminate contention between pull-up and pull-down devices at node N during the first stage of the write operation.

Abstract: The disclosure provides a novel system of storing information using a charged polymer, e.g., DNA, the monomers of which correspond to a machine-readable code, e.g., a binary code, and which can be synthesized and/or read using a novel nanochip device comprising nanopores; novel methods and devices for synthesizing oligonucleotides in a nanochip format; novel methods for synthesizing DNA in the 3? to 5? direction using topoisomerase; novel methods and devices for reading the sequence of a charged polymer, e.g., DNA, by measuring capacitive variance as the polymer passes through the nanopore; and further provides compounds, compositions, methods and devices useful therein.

Abstract: Memory programming methods and memory systems are described. One example memory programming method includes programming a plurality of main cells of a main memory and erasing a plurality of second main cells of the main memory. The memory programming method further includes first re-writing one-time programmed data within a plurality of first one-time programmed cells of a one-time programmed memory during the programming and second re-writing one-time programmed data within a plurality of second one-time programmed cells of a one-time programmed memory during the erasing. Additional method and apparatus are described.

Abstract: Provided are a voltage control circuit including an assist circuit and a memory device including the voltage control circuit. The memory device includes: a volatile memory cell array, which is connected to a plurality of word lines and includes a memory cell including at least one transistor; and an assist circuit, which is connected to at least one of the plurality of word lines and adjusts a driving voltage level of each of the plurality of word lines, wherein the assist circuit includes a diode N-channel metal oxide semiconductor (NMOS) transistor having a gate and a drain connected to each other.