Patents Examined by Mohammed A Bashar
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Patent number: 10658582Abstract: A vertical resistive unit is provided. The vertical resistive unit includes first and second resistive random access memory (ReRAM) cells. The first ReRAM cell includes first vertically aligned horizontal electrode layers and first vertical electrodes operably extending through the first vertically aligned horizontal electrode layers. The second ReRAM cell includes second vertically aligned horizontal electrode layers and second vertical electrodes operably extending through the second vertically aligned horizontal electrode layers. The first and second ReRAM cells are disposed to define an air gap between the first and second ReRAM cells.Type: GrantFiled: June 6, 2018Date of Patent: May 19, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Takashi Ando, Pouya Hashemi, Choonghyun Lee
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Patent number: 10658033Abstract: A non-volatile memory device is provided that uses one or more volatile elements. In some embodiments, the non-volatile memory device can include a resistive two-terminal selector that can be in a low resistive state or a high resistive state depending on the voltage being applied. A MOS (“metal-oxide-semiconductor”) transistor in addition to a capacitor or transistor acting as a capacitor can also be included. A first terminal of the capacitor can be connected to a voltage source, and the second terminal of the capacitor can be connected to the selector device. A floating gate of an NMOS transistor can be connected to the other side of the selector device, and a second NMOS transistor can be connected in series with the first NMOS transistor.Type: GrantFiled: February 18, 2019Date of Patent: May 19, 2020Assignee: CROSSBAR, INC.Inventors: Hagop Nazarian, Sung Hyun Jo
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Patent number: 10658055Abstract: According to one embodiment, a memory system includes a memory device and a controller. The controller is configured to make the memory device apply a first verify voltage to a first word line for determining whether writing of a first data value into a first cell transistor has been completed. The controller is configured to make the memory device apply a second verify voltage to a second word line for determining whether writing of the first data value into a second cell transistor has been completed. The second verify voltage is different from the first verify voltage.Type: GrantFiled: March 13, 2018Date of Patent: May 19, 2020Assignee: Toshiba Memory CorporationInventors: Kazutaka Takizawa, Yoshihisa Kojima, Masaaki Niijima
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Patent number: 10640822Abstract: The disclosure provides a novel system of storing information using a charged polymer, e.g., DNA, the monomers of which correspond to a machine-readable code, e.g., a binary code, and which can be synthesized and/or read using a novel nanochip device comprising nanopores; novel methods and devices for synthesizing oligonucleotides in a nanochip format; novel methods for synthesizing DNA in the 3? to 5? direction using topoisomerase; novel methods and devices for reading the sequence of a charged polymer, e.g., DNA, by measuring capacitive or impedance variance, e.g., via a change in a resonant frequency response, as the polymer passes through the nanopore; and further provides compounds, compositions, methods and devices useful therein.Type: GrantFiled: May 2, 2018Date of Patent: May 5, 2020Assignee: IRIDIA, INC.Inventors: Paul F. Predki, Maja Cassidy
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Patent number: 10643718Abstract: Program disturb is a condition that includes the unintended programming of a memory cell while performing a programming process for other memory cells. Such unintended programming can cause an error in the data being stored. In some cases, program disturb can result from electrons trapped in the channel being accelerated from one side of a selected word line to another side of the selected word line and redirected into the selected word line. To prevent such program disturb, it is proposed to open the channel from one side of a selected word line to the other side of the selected word line after a sensing operation for program verify and prior to a subsequent programming voltage being applied.Type: GrantFiled: June 7, 2018Date of Patent: May 5, 2020Assignee: SanDisk Technologies LLCInventors: Dengtao Zhao, Peng Zhang, Nan Lu, Deepanshu Dutta
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Patent number: 10635357Abstract: Improved methods and systems for accessing a memory in a computer are disclosed. In one embodiment, the true and complement portions of a differential write clock signal are employed as two single ended clock signals for independently controlling different memory chips in a memory system. For example, in a memory system having two memory chips, one memory chip is configured to use the true write clock signal and the other memory chip is configured to use the complement write clock signal. Employing the differential write clock signal as two single ended clock signals allows overlapping of write and read operations across multiple memory chips, reducing the time needed for accessing memory. Accordingly, the disclosed methods and systems provide a more efficient memory system that can be used to improve the operation of a computer.Type: GrantFiled: November 30, 2018Date of Patent: April 28, 2020Assignee: Nvidia CorporationInventor: Michael Halfen
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Patent number: 10628067Abstract: A memory system includes: a plurality of nonvolatile memory devices each including a plurality of memory blocks; and a controller configured to select an innocent open super block among super blocks formed across the nonvolatile memory devices when determining that sequential write operations are to be performed, and perform the sequential write operations on the innocent open super block.Type: GrantFiled: August 1, 2018Date of Patent: April 21, 2020Assignee: SK hynix Inc.Inventor: Jeen Park
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Patent number: 10629261Abstract: Various embodiments disclosed herein comprise methods and apparatuses for placing phase-change memory (PCM) cells of a memory array into a temperature regime where nucleation probability of the PCM cells is enhanced prior to applying a subsequent SET programming signal. In one embodiment, the method includes applying a nucleation signal to the PCM cells to form nucleation sites within the memory array where the nucleation signal has a non-zero rising-edge. A programming signal is subsequently applied to achieve a desired level of crystallinity within selected ones of the plurality of PCM cells. Additional methods and apparatuses are also described.Type: GrantFiled: April 1, 2019Date of Patent: April 21, 2020Assignee: Micron Technology, Inc.Inventors: Agostino Pirovano, Fabio Pellizzer, Anna Maria Conti, Davide Fugazza, Johannes A. Kalb
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Patent number: 10622079Abstract: According to one embodiment, a memory device comprises a first memory cell configured to store data, a first word line connected to the first memory cell, a first circuit configured to supply a voltage to the first word line, a second circuit configured to control the first circuit, and a sequencer configured to control the first circuit and the second circuit. The sequencer, when data is written to the first memory cell, determines whether a condition is satisfied or not. The sequencer causes the second circuit to generate a first voltage, when the sequencer determines that the condition is not satisfied, and causes the second circuit to generate a second voltage which is higher than the first voltage, when the sequencer determines that the condition is satisfied.Type: GrantFiled: July 31, 2019Date of Patent: April 14, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventor: Hiroki Date
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Patent number: 10622042Abstract: A semiconductor device may include a first internal command generation circuit, a first DLL circuit, a second internal command generation circuit, and a second DLL circuit. The first internal command generation circuit may generate a first delay command in response to a first external command, a first latency, a first clock, a first delay control signal, and a second clock. The first DLL circuit may generate the first delay control signal and the first second clock in response to the first clock. The second internal command to generation circuit may generate a second delay command in response to a second external command, a second latency, the first clock, a second delay control signal, and a third clock. The second DLL circuit may generate the second delay control signal and the third clock in response to the first clock.Type: GrantFiled: December 14, 2018Date of Patent: April 14, 2020Assignee: SK hynix Inc.Inventors: Gyu Tae Park, Young Suk Seo
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Patent number: 10614859Abstract: A memory device includes a first dynamic random access memory (DRAM) integrated circuit (IC) chip including first memory core circuitry, and first input/output (I/O) circuitry. A second DRAM IC chip is stacked vertically with the first DRAM IC chip. The second DRAM IC chip includes second memory core circuitry, and second I/O circuitry. Solely one of the first DRAM IC chip or the second DRAM IC chip includes a conductive path that electrically couples at least one of the first memory core circuitry or the second memory core circuitry to solely one of the first I/O circuitry or the second I/O circuitry, respectively.Type: GrantFiled: January 24, 2019Date of Patent: April 7, 2020Assignee: Rambus Inc.Inventor: Thomas Vogelsang
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Patent number: 10607689Abstract: Apparatuses and methods for providing driving signals in semiconductor devices are described. An example apparatus includes a plurality of memory cell mats including a plurality of word lines and a word line driver coupled to the plurality of word lines of the plurality of memory cell mats. The word line driver is configured, responsive to a row active command, to provide a first voltage to a selected word line of the plurality of the word lines of a selected memory cell mat of the plurality of memory cell mats, provide a second voltage different from the first voltage to each of unselected word lines of the plurality of the word lines of the selected memory cell mats of the plurality of memory cell mats, and provide no voltage to each of the plurality of word lines of each of unselected memory cell mats of the plurality of memory cell mats.Type: GrantFiled: May 17, 2019Date of Patent: March 31, 2020Assignee: Micron Technology, Inc.Inventors: Satoshi Yamanaka, Tetsuaki Okahiro
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Patent number: 10608013Abstract: A method for forming 3D memory device includes forming an alternating dielectric stack in a contact region on a substrate, forming a plurality of contact holes with various depths vertically extending in the alternating dielectric stack, forming a sacrificial-filling layer to fill the contact holes, forming a plurality of dummy channel holes penetrating the alternating dielectric stack in the contact region, filling the dummy channel holes with a dielectric material to form supporters, and replacing the sacrificial layers of the alternating dielectric stack and the sacrificial-filling layer with conductive layers so as to form a plurality of gate lines and contacts.Type: GrantFiled: October 25, 2018Date of Patent: March 31, 2020Assignee: Yangtze Memory Technologies Co., Ltd.Inventor: Li Hong Xiao
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Patent number: 10593399Abstract: Methods, systems, and devices for self-selecting memory with horizontal access lines are described. A memory array may include first and second access lines extending in different directions. For example, a first access line may extend in a first direction, and a second access line may extend in a second direction. At each intersection, a plurality of memory cells may exist, and each plurality of memory cells may be in contact with a self-selecting material (SSM). Further, a dielectric material may be positioned between a first plurality of memory cells and a second plurality of memory cells in at least one direction. each cell group (e.g., a first and second plurality of memory cells) may be in contact with one of the first access lines and second access lines, respectively.Type: GrantFiled: March 19, 2018Date of Patent: March 17, 2020Assignee: Micron Technology, Inc.Inventors: Lorenzo Fratin, Fabio Pellizzer, Agostino Pirovano, Russell L. Meyer
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Patent number: 10586574Abstract: Cache mode for word lines where the cache mode utilizes an internal timer for a memory cell to disable connection of a voltage to a transistor of a word line driver of the memory cell before an end of a specified end of period. By early disconnection, the local controls of the memory cell may provide additional time to settle after disconnection of the voltage without interfering with operations (e.g., read, write, activate) of the memory cell, since the internal timer may be programmed to be greater than or equal to a worst case scenario for the operations.Type: GrantFiled: May 31, 2019Date of Patent: March 10, 2020Assignee: Micron Technology, Inc.Inventor: Gregg D. Wolff
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Patent number: 10586608Abstract: A dynamic random access memory (DRAM) refresh method in which a to-be-refreshed area in a refresh block is specified in a refresh instruction is provided to refresh a specified location of a DRAM storage array. A memory controller sends a refresh instruction to a DRAM refresh apparatus. The refresh instruction includes an identifier of a to-be-refreshed block and refresh information indicating a to-be-refreshed area. The DRAM refresh apparatus generates addresses of to-be-refreshed bank rows in the to-be-refreshed block according to the identifier and the refresh information, and refresh locations corresponding to the addresses of the bank rows in the to-be-refreshed block. Therefore, a DRAM refresh time is shortened, refresh power consumption is reduced, a refresh operation is more flexible, and system resource consumption is reduced while data integrity is ensured.Type: GrantFiled: November 3, 2017Date of Patent: March 10, 2020Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Shihai Xiao, Yongbing Huang, Rui He
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Patent number: 10586591Abstract: A high speed thin film two terminal resistive memory article of manufacture comprises a chargeable and dischargeable variable resistance thin film battery having a plurality of layers operatively associated with one another, the plurality of layers comprising in sequence, a cathode-side conductive layer, a cathode layer comprised of a material that can take up cations and discharge cations in a charging and discharging process, an electrolyte layer comprising the cations, a barrier layer, an anode layer, and an optional anode-side conductive layer, the barrier layer comprised of a material that substantially prevents the cations from combining with the anode layer.Type: GrantFiled: January 8, 2018Date of Patent: March 10, 2020Assignee: International Business Machines CorporationInventors: Ning Li, Devendra Sadana
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Patent number: 10580474Abstract: A semiconductor device may include a refresh control circuit which may generate test addresses that are counted based on a refresh signal and a detection clock signal and may senses logic levels of internal data corresponding to the test addresses to generate a sense signal. The semiconductor device may include a memory circuit may include a plurality of word lines which are selected by the test addresses and may output the internal data stored in memory cells connected to the word lines. The semiconductor device may include an address storage circuit may divide each of the test addresses into a main group and a sub-group to store the main groups and the sub-groups of the test addresses. The address storage circuit may store the sub-groups which are inputted at a point of time that the sense signal is generated, regarding the stored main groups having the same level combination.Type: GrantFiled: November 13, 2017Date of Patent: March 3, 2020Assignee: SK hynix Inc.Inventors: Sang Ah Hyun, Yunyoung Lee, Seok Bo Shim, Sang Ho Lee
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Patent number: 10579307Abstract: Devices and techniques for correcting for power loss in NAND memory devices are disclosed herein. The NAND memory devices may comprise a number of physical pages. For example, a memory controller may detect a power loss indicator at the NAND flash memory. The memory controller may identify a last-written physical page and determine whether the last-written physical page comprises more than a threshold number of low-read-margin cells. If the last-written physical page comprises more than the threshold number of low-read-margin cells, the memory controller may provide a programming voltage to at least the low-read-margin cells.Type: GrantFiled: September 10, 2019Date of Patent: March 3, 2020Assignee: Micron Technology, Inc.Inventors: Michael G. Miller, Kishore Kumar Muchherla, Harish Reddy Singidi, Sampath Ratnam, Renato Padilla, Jr., Gary F. Besinga, Peter Sean Feeley
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Patent number: 10564869Abstract: A method of controlling memory devices of a memory controller, the memory devices including a plurality of memory dies, includes receiving at least one data operation request and a power budget from external of the memory controller; determining respective data operation times of the plurality of memory dies, wherein a power consumption due to at least one data operation in response to the at least one data operation request may be equal to or less than the power budget; and controlling the plurality of memory dies based on the data operation times.Type: GrantFiled: August 8, 2018Date of Patent: February 18, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Kui-Yon Mun, Young-Wook Kim, Wan-Soo Choi
