Patents Examined by Mohammed R Alam
  • Patent number: 10845406
    Abstract: The present disclosure provides a semiconductor device and a method of manufacturing the same, and relates to the field of semiconductor devices. The semiconductor device includes an active region, a test region and a passive region located outside the active region and the test region, wherein a standard device is formed in the active region, and a test device for testing performance parameters of the standard device is formed in the test region.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: November 24, 2020
    Assignee: DYNAX SEMICONDUCTOR, INC.
    Inventors: Naiqian Zhang, Jian Liu, Feihang Liu, Yi Pei
  • Patent number: 10825852
    Abstract: According to one embodiment, an edge of the second opening is recessed further than an edge of the first opening away from a center of the first opening. The recess has an opening and a concave surface and is disposed in a region inward from the edge of the second opening. The opening has a circular configuration. The concave surface has a curvature.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: November 3, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Yasushi Itabashi
  • Patent number: 10825722
    Abstract: A method of manufacturing a semiconductor structure includes forming a precursor structure on a substrate. The precursor structure includes a first conductive structure, a first spacer layer, and a spacer oxide layer sequentially on the substrate. The spacer oxide layer exposes a top surface of the first spacer layer. The spacer oxide layer is then recessed. A second spacer layer is formed to cover the spacer oxide layer and the first spacer layer. A portion of the second spacer layer and a portion of the spacer oxide layer are then etched to expose the lateral portion of the first spacer layer. The remaining spacer oxide layer is etched to form an air gap between the first spacer layer and the second spacer layer. A third spacer layer is formed on the lateral portion of the first spacer layer to seal the air gap.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: November 3, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Shih-Fan Kuan
  • Patent number: 10818861
    Abstract: A light-emitting layer, which is a stack of a first light-emitting layer and a second light-emitting layer, is provided between an anode and a cathode. The first light-emitting layer is formed on the anode side and contains a first light-emitting substance converting triplet excitation energy into light emission, a first organic compound having an electron-transport property, and a second organic compound having a hole-transport property. The second light-emitting layer contains a second light-emitting substance converting triplet excitation energy into light emission, the first organic compound, and a third organic compound having a hole-transport property. The second organic compound has a lower HOMO level than the third organic compound. The first light-emitting substance emits light with a wavelength shorter than that of light emitted from the second light-emitting substance. The first and the second organic compounds form an exciplex. The first and the third organic compounds form an exciplex.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: October 27, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoshi Seo, Hiromi Seo
  • Patent number: 10797183
    Abstract: A capacitor that includes a substrate; a capacitor formation region in which one or more trenches are formed; a dummy region located between the capacitor formation region and an end of the substrate; a first electrode formed inside the one or more trenches to cover the capacitor formation region, and a dielectric film; a second electrode that covers the capacitor formation region and has a different potential from the first electrode; and an extended portion that formed in the dummy region. Moreover, the extended portion forms a recess or a protrusion on the substrate in a path from the second electrode to the end portion of the substrate.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: October 6, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Masaki Takeuchi, Shigeki Nishiyama, Hiroshi Nakagawa, Satoru Goto, Yoshinari Nakamura
  • Patent number: 10797045
    Abstract: An accumulation layer has a function of reducing an ON voltage (Von), which is a voltage between the collector and the emitter when turning on the IGBT, by accumulating carrier. However, when turning off the IGBT, the carrier contributes to a turn-off loss (Eoff). A semiconductor device is provided, comprising: a semiconductor substrate, wherein the semiconductor substrate includes: trench portions, a mesa portion each provided between two adjacent trench portions, and a drift layer, wherein the trench portions include: a gate trench portion, and a dummy trench portion, wherein the mesa portion has: an emitter region, a contact region, and a accumulation layer, wherein the number of accumulation layers provided in a depth direction in the mesa portion adjacent to the gate trench portion is larger than that of the accumulation layers provided in the depth direction in the mesa portion between the two dummy trench portions.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: October 6, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tatsuya Naito
  • Patent number: 10797071
    Abstract: A semiconductor memory device includes a peripheral circuit structure including a peripheral circuit insulating layer, a middle connection structure on the peripheral circuit insulating layer, the middle connection structure including a middle connection insulating layer, and a bottom surface of the middle connection insulating layer is in contact with a top surface of the peripheral circuit insulating layer, stack structures on sides of the middle connection structure, and channel structures extending vertically through each of the stack structures, wherein at least one side surface of the middle connection insulating layer is an inclined surface, a lateral sectional area of the middle connection insulating layer decreasing in an upward direction oriented away from the peripheral circuit insulating layer.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: October 6, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jun Hyoung Kim, Kwang Soo Kim, Geun Won Lim
  • Patent number: 10784279
    Abstract: Embodiments of 3D memory devices with a dielectric etch stop layer and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a dielectric etch stop layer disposed on the substrate, a memory stack disposed on the dielectric etch stop layer and including a plurality of interleaved conductor layers and dielectric layers, and a plurality of memory strings each extending vertically through the memory stack and including a selective epitaxial growth (SEG) plug in a bottom portion of the memory string. The SEG plug is disposed on the substrate.
    Type: Grant
    Filed: November 17, 2018
    Date of Patent: September 22, 2020
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Fandong Liu, Wenyu Hua, Jia He, Linchen Wu, Yue Qiang Pu, Zhiliang Xia
  • Patent number: 10784273
    Abstract: A method used in forming a memory array comprises forming a substrate comprising a conductive tier, a first insulator tier above the conductive tier, a sacrificial material tier above the first insulator tier, and a second insulator tier above the sacrificial material tier. A stack comprising vertically-alternating insulative tiers and wordline tiers is formed above the second insulator tier. Channel material is formed through the insulative tiers and the wordline tier. Horizontally-elongated trenches are formed through the stack to the sacrificial material tier. Sacrificial material is etched through the horizontally-elongated trenches selectively relative to material of the first insulator tier and selectively relative to material of the second insulator tier. A laterally-outer sidewall of the channel material is exposed in the sacrificial material tier. A conductive structure is formed directly against the laterally-outer sidewall of the channel material in the sacrificial material tier.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: September 22, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Collin Howder, Gordon A. Haller
  • Patent number: 10784848
    Abstract: Van der Waals heterojunctions are extended to semiconducting p-type single-walled carbon nanotube (s-SWCNT) and n-type film that can be solution-processed with high spatial uniformity at the wafer scale. The resulting large-area, low-voltage p-n heterojunctions can exhibit anti-ambipolar transfer characteristics with high on/off ratios. The charge transport can be efficiently utilized in analog circuits such as frequency doublers and keying circuits that are widely used, for example, in telecommunication and wireless data transmission technologies.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: September 22, 2020
    Assignees: Northwestern University, Regent of the University of Minnesota
    Inventors: Deep M. Jariwala, Vinod K. Sangwan, Weichao Xu, Hyungil Kim, Tobin J. Marks, Mark C. Hersam
  • Patent number: 10777460
    Abstract: A processing method of a workpiece for processing the workpiece including a substrate and a film made on a back surface of the substrate is provided. The processing method includes a sheet sticking step of sticking a sheet to the film, a protective film forming step of forming a protective film that covers the front surface side of the substrate, a mask pattern forming step of removing a part corresponding to planned dividing lines in the protective film and forming a mask pattern on the front surface side, an etching step of carrying out dry etching for the substrate from the front surface side and forming etching grooves and a film dividing step of dividing the film along the etching grooves by pressing the workpiece by an edge of a tip part of a pressing member having the tip part in which the edge has a curved shape.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: September 15, 2020
    Assignee: DISCO CORPORATION
    Inventors: Yukiko Matsumoto, Meiyu Piao
  • Patent number: 10777720
    Abstract: A light emitting module includes a first light transmissive insulator, a conductive circuitry layer formed on a surface of the first light transmissive insulator, a second light transmissive insulator disposed so as to face the conductive circuitry layer, a light emitting element disposed between the first light transmissive insulator and the second light transmissive insulator, and connected to the conductive circuitry layer, and a third light transmissive insulator which is disposed between the first light transmissive insulator and the second light transmissive insulator, and which is thermosetting.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: September 15, 2020
    Assignee: Toshiba Hokuto Electronics Corporation
    Inventor: Keiichi Maki
  • Patent number: 10770295
    Abstract: An example embodiment includes a patterning method comprising: forming a layer stack comprising a target layer, a lower memorization layer and an upper memorization layer, forming above the upper memorization layer a first mask layer, patterning a set of upper trenches in the upper memorization layer, forming a first block pattern, the first block pattern comprising a set of first blocks, patterning a first set of lower trenches in the lower memorization layer, patterning the patterned upper memorization layer to form a second block pattern comprising a set of second blocks, forming above the patterned lower memorization layer and the second block pattern a second mask layer, patterning a second set of lower trenches in the patterned lower memorization layer, the patterning comprising using the second mask layer, the spacer layer and the second block pattern as an etch mask.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: September 8, 2020
    Assignee: IMEC VZW
    Inventors: Frederic Lazzarino, Victor M. Blanco
  • Patent number: 10756227
    Abstract: An electrical device includes a counterdoped heterojunction selected from a group consisting of a pn junction or a p-i-n junction. The counterdoped junction includes a first semiconductor doped with one or more n-type primary dopant species and a second semiconductor doped with one or more p-type primary dopant species. The device also includes a first counterdoped component selected from a group consisting of the first semiconductor and the second semiconductor. The first counterdoped component is counterdoped with one or more counterdopant species that have a polarity opposite to the polarity of the primary dopant included in the first counterdoped component. Additionally, a level of the n-type primary dopant, p-type primary dopant, and the one or more counterdopant is selected to the counterdoped heterojunction provides amplification by a phonon assisted mechanism and the amplification has an onset voltage less than 1 V.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: August 25, 2020
    Assignee: Quantum Semiconductor LLC
    Inventor: Carlos Jorge R. P. Augusto
  • Patent number: 10755972
    Abstract: A semiconductor device and method of manufacture comprise placing an etch stop layer of a material such as aluminum oxide over a conductive element, placing a dielectric layer over the etch stop layer, and placing a hardmask of a material such as titanium nitride over the dielectric layer. Openings are formed to the etch stop layer, the hardmask material is selectively removed, and the openings are then the material of the etch stop layer is then selectively removed to extend the openings through the etch stop layer.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: August 25, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Nai-Chia Chen, Chun-Li Chou, Yen-Chiu Kuo, Yu-Li Cheng, Chun-Hung Chao
  • Patent number: 10755933
    Abstract: Laser light of a short-wavelength laser is irradiated from a rear surface of an n?-type semiconductor substrate, activating a p+-type collector region and an n+-type cathode region. At this time, a surface layer at the rear surface of the n?-type semiconductor substrate is melted and recrystallized, eliminating amorphous parts. Thereafter, laser light of a long-wavelength laser is irradiated from the rear surface of the n?-type semiconductor substrate and an n-type FS region is activated. Substantially no amorphous parts exist in the surface layer at the rear surface of the n?-type semiconductor substrate. Therefore, decreases in the absorption rate and increases in the reflection rate of the laser light of the long-wavelength laser are suppressed and heat from the laser light of the long-wavelength laser is transmitted to the n-type FS region, enabling the n-type FS region to be assuredly activated by laser annealing using lower energy.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: August 25, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Hiroshi Takishita, Takashi Yoshimura
  • Patent number: 10748780
    Abstract: In a manufacturing method of a silicon carbide semiconductor device, a semiconductor substrate made of silicon carbide and on which a base layer is formed is prepared, a trench is provided in the base layer, a silicon carbide layer is epitaxially formed on a surface of the base layer while filling the trench with the silicon carbide layer, the sacrificial layer is planarized by reflow after forming the sacrificial layer, and the silicon carbide layer is etched back together with the planarized sacrificial layer by dry etching under an etching condition in which an etching selectivity of the silicon carbide layer to the sacrificial layer is 1.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: August 18, 2020
    Assignees: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Shigeyuki Takagi, Masaki Shimomura, Yuichi Takeuchi, Katsumi Suzuki, Sachiko Aoi
  • Patent number: 10741578
    Abstract: Embodiments of 3D memory devices having an inter-deck plug and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a first memory deck including interleaved conductor and dielectric layers above the substrate, a second memory deck including interleaved conductor and dielectric layers above the first memory deck, and a first and a second channel structure each extending vertically through the first or second memory deck. The first channel structure includes a first memory film and semiconductor channel along a sidewall of the first channel structure, and an inter-deck plug in an upper portion of the first channel structure and in contact with the first semiconductor channel. A lateral surface of the inter-deck plug is smooth. The second channel structure includes a second memory film and semiconductor channel along a sidewall of the second channel structure. The second semiconductor channel is in contact with the inter-deck plug.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: August 11, 2020
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Qianbin Xu, Haohao Yang, EnBo Wang, Yong Zhang, Jialan He
  • Patent number: 10741390
    Abstract: A forming method of an epitaxial layer, a forming method of a 3D NAND memory and an annealing apparatus are provided. In the forming method of the epitaxial layer, a first annealing process is performed for eliminating a stress generated in a stacked structure. When performing the first annealing process, a silicon-containing mixture is formed on a sidewall and a bottom surface of a trench. Thus, after performing the first annealing process, a second annealing process is performed for removing the silicon-containing mixture disposed at the sidewall and the bottom surface of the trench, such that when subsequently forming the epitaxial layer, a growth interface of the epitaxial layer is a pure substrate material interface, so as to prevent from be formed a void defect in the epitaxial layer formed in the trench.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: August 11, 2020
    Assignee: Yangtz Memory Technologies Co., Ltd.
    Inventors: Haifeng Guo, Xiaojin Wang, Hongbin Zhu, Lin Lai, Teng Cheng, Lihong Xiao
  • Patent number: 10734274
    Abstract: A process separates a main body of a semiconductor substrate from a functional layer. The method includes the steps of implanting ions into a semiconductor substrate through a top surface of the semiconductor substrate to form an ion damage layer underneath the top surface of the semiconductor substrate. After the ions are implanted into the semiconductor substrate, a functional layer is formed on the top surface of the semiconductor substrate. The main body of the semiconductor substrate is then separated from the functional layer. The method also includes forming the functional layer on the semiconductor substrate after ion implanting and then separating the functional layer from the main body of the substrate at the ion damage layer. This method avoids bonding in SOI and can thus reduce process steps and cost.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: August 4, 2020
    Inventor: Bing Hu