Patents Examined by Mohammed R Alam
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Patent number: 12224285Abstract: An integrated circuit includes a set of active regions, a first contact, a set of gates, a first and second conductive line and a first and second via. The set of active regions extends in a first direction, and is on a first level. The first contact extends in a second direction, is on a second level, and overlaps at least a first active region. The set of gates extends in the second direction, overlaps the set of active regions, and is on a third level. The first conductive line and the second conductive line extend in the first direction, overlap the first contact, and are on a fourth level. The first via electrically couples the first contact and the first conductive line together. The second via electrically couples the first contact and the second conductive line together.Type: GrantFiled: May 31, 2022Date of Patent: February 11, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chin-Wei Hsu, Shun Li Chen, Ting Yu Chen, Hui-Zhong Zhuang, Chih-Liang Chen
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Patent number: 12224288Abstract: An array base plate, a method for manufacturing same, and a display panel are disclosed. The array base plate includes: an active layer including a body portion, and a first conduction portion and a second conduction portion disposed on two sides of the active layer; an etching protective layer and an ohmic contact layer disposed in a same layer, where the etching protective layer is located on the body portion, and the ohmic contact layer is located on the first conduction portion and the second conduction portion; and a source and a drain separately disposed on the ohmic contact layer located on the first conduction portion and the second conduction portion.Type: GrantFiled: November 12, 2021Date of Patent: February 11, 2025Assignees: Huizhou China Star Optoelectronics Display Co., Ltd., TCL China Star Optoelectronics Technology Co., Ltd.Inventor: Jiahui Huang
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Patent number: 12224333Abstract: An HEMT with a stair-like compound layer as a drain includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer and the second III-V compound layer are different from each other. A source electrode, a gate electrode and a drain electrode are disposed on the second III-V compound layer. The gate electrode is disposed between the source electrode and the drain electrode. A first P-type III-V compound layer is disposed between the drain electrode and the second III-V compound layer. The first P-type III-V compound layer is stair-like.Type: GrantFiled: June 17, 2022Date of Patent: February 11, 2025Assignee: UNITED MICROELECTRONICS CORP.Inventor: Po-Yu Yang
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Patent number: 12225770Abstract: A light emitting display device includes: a light emitting element; a second transistor connected to a scan line; a first transistor which applies a current to the light emitting element; a capacitor connected to a gate electrode of the first transistor; and a third transistor connected to an output electrode of the first transistor and the gate electrode of the first transistor. Channels of the second transistor, the first transistor, and the third transistor are disposed in a polycrystalline semiconductor layer, and a width of a channel of the third transistor is in a range of about 1 ?m to about 2 ?m, and a length of the channel of the third transistor is in a range of about 1 ?m to about 2.5 ?m.Type: GrantFiled: November 30, 2023Date of Patent: February 11, 2025Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Keun Woo Kim, Tae Wook Kang, Han Bit Kim, Bum Mo Sung, Do Kyeong Lee, Jae Seob Lee
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Patent number: 12224297Abstract: A method of making a semiconductor structure includes forming a pixel array region on a substrate. The method further includes forming a first seal ring region on the substrate, wherein the first seal ring region surrounds the pixel array region, and the first seal ring region includes a first seal ring. The method further includes forming a first isolation feature in the first seal ring region, wherein forming the first isolation feature includes filling a first opening with a dielectric material, wherein the first isolation feature is a continuous structure surrounding the pixel array region. The method further includes forming a second isolation feature between the first isolation feature and the pixel array region, wherein forming the second isolation feature includes filling a second opening with the dielectric material.Type: GrantFiled: January 19, 2023Date of Patent: February 11, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yun-Wei Cheng, Chun-Wei Chia, Chun-Hao Chou, Kuo-Cheng Lee, Ying-Hao Chen
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Patent number: 12218212Abstract: A semiconductor device includes a gate stack including a gate insulating layer and a gate electrode on the gate insulating layer. The gate insulating layer includes a first dielectric layer and a second dielectric layer on the first dielectric layer, and a dielectric constant of the second dielectric layer is greater than a dielectric constant of the first dielectric layer. The semiconductor device also includes a first spacer on a side surface of the gate stack, and a second spacer on the first spacer, wherein the second spacer includes a protruding portion extending from a level lower than a lower surface of the first spacer towards the first dielectric layer, and a dielectric constant of the second spacer is greater than the dielectric constant of the first dielectric layer and less than a dielectric constant of the first spacer.Type: GrantFiled: October 27, 2023Date of Patent: February 4, 2025Assignee: Samsung Electronics Co., Ltd.Inventors: Doosan Back, Dongoh Kim, Gyuhyun Kil, Jung-Hoon Han
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Patent number: 12213306Abstract: A semiconductor device includes a bottom barrier layer disposed over a semiconductor substrate, and a conductive contact disposed over the bottom barrier layer. The semiconductor device also includes a top barrier layer disposed over the conductive contact. The bottom barrier layer, the conductive contact, and the top barrier layer form an I-shaped structure. The semiconductor device further includes an isolation layer disposed adjacent to the I-shaped structure and extending into the semiconductor substrate. An air gap is surrounded by the isolation layer.Type: GrantFiled: July 21, 2022Date of Patent: January 28, 2025Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Tse-Yao Huang
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Patent number: 12213372Abstract: The present disclosure relates to an OLED display panel and display device. The OLED display panel includes: a display area, a bending area and a bonding area for bonding a circuit board, wherein the display panel further includes: a base substrate; a first semiconductor pattern on the base substrate; a first insulating layer group on the first semiconductor pattern; a second semiconductor pattern on the first insulating layer group; a second insulating layer group on the second semiconductor pattern; first via holes in the first insulating layer group and the second insulating layer group; second via holes in the second insulating layer group, wherein the display panel further includes: a first groove located in the bending area and having a depth substantially identical to that of the first via holes; and a metal trace, connecting a trace in the display area to the circuit board.Type: GrantFiled: April 29, 2022Date of Patent: January 28, 2025Assignee: BOE TECHNOLOGY GROUP CO., LTD.Inventors: Wei Yang, Guangcai Yuan, Ce Ning, Xinhong Lu, Tianmin Zhou, Xin Yang
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Patent number: 12213307Abstract: A semiconductor device includes a bottom barrier layer disposed over a semiconductor substrate, and a conductive contact disposed over the bottom barrier layer. The semiconductor device also includes a top barrier layer disposed over the conductive contact. The bottom barrier layer, the conductive contact, and the top barrier layer form an I-shaped structure. The semiconductor device further includes an isolation layer disposed adjacent to the I-shaped structure and extending into the semiconductor substrate. An air gap is surrounded by the isolation layer.Type: GrantFiled: May 16, 2023Date of Patent: January 28, 2025Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Tse-Yao Huang
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Patent number: 12205999Abstract: Provided is a metal-oxide thin-film transistor. The metal-oxide thin-film transistor includes a gate, a gate insulation layer, a metal-oxide semiconductor layer, a source electrode, a drain electrode, and a passivation layer that are successively disposed on a base substrate; wherein the source electrode and the drain electrode are both in a laminated structure, wherein the laminated structure of the source electrode or the drain electrode at least includes a bulk metal layer and an electrode protection layer; wherein the electrode protection layer includes a metal or a metal alloy; the electrode protection layer is at least disposed between the metal-oxide semiconductor layer and the bulk metal layer; wherein a metal-oxide layer is disposed between the electrode protection layer and the bulk metal layer.Type: GrantFiled: August 31, 2021Date of Patent: January 21, 2025Assignees: FUZHOU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Bin Lin, Liangliang Li, Zheng Liu, Bo Hu, Rui Zhang, Xinlin Peng
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Patent number: 12191250Abstract: The present disclosure relates integrated chip structure. The integrated chip structure includes a lower insulating structure disposed over a lower dielectric structure surrounding one or more lower interconnects. A bottom electrode via surrounded by one or more interior sidewalls of the lower insulating structure. The bottom electrode via includes a barrier surrounding a conductive core. A bottom electrode is arranged on the bottom electrode via, a data storage structure is over the bottom electrode, and a top electrode is over the data storage structure. The barrier includes a sidewall disposed along the one or more interior sidewalls of the lower insulating structure and a horizontally covering segment protruding outward from the sidewall to above a top surface of the lower insulating structure.Type: GrantFiled: April 21, 2022Date of Patent: January 7, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Zhen Yu Guan, Sheng-Wen Fu, Hsun-Chung Kuang
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Patent number: 12191260Abstract: The present application discloses a display panel and a display apparatus. The display panel includes a substrate, a first shielding layer and a driving circuit layer. The first shielding layer is located on a side of the substrate, and the first shielding layer includes a plurality of first shielding units located in a first display region and a plurality of second shielding units located in a second display region. At least a portion of adjacent first shielding units are connected through first connecting parts, and a portion of adjacent second shielding units are connected through second connecting parts. The driving circuit layer is located on a side of the first shielding layer away from the substrate, the driving circuit layer includes a plurality of driving circuits, and each driving circuit includes a driving transistor.Type: GrantFiled: April 19, 2022Date of Patent: January 7, 2025Assignee: XIAMEN TIANMA DISPLAY TECHNOLOGY CO., LTD.Inventors: Yihua Zhu, Qingjun Lai, Jinjin Yang, Jiaxian Liu
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Patent number: 12185609Abstract: A display substrate, a display panel and a method for manufacturing the display substrate are provided. The display substrate comprises a backing substrate and a plurality of pixel areas formed on the backing substrate, wherein the display substrate further comprises a quantum dot layer, the quantum dot layer comprises a plurality of quantum dot units located in the plurality of pixel areas respectively, wherein the quantum dot units comprise a matrix layer and quantum dots dispersed in the matrix layer, the matrix layer comprises a central region and a peripheral region disposed around the central region, the peripheral region comprises a polymer of photocurable monomers, and the central region comprises unpolymerized photocurable monomers.Type: GrantFiled: December 1, 2021Date of Patent: December 31, 2024Assignees: Beijing BOE Technology Development Co., Ltd., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Wenhai Mei, Zhuo Li
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Patent number: 12168601Abstract: A microelectromechanical systems (MEMS) die comprises a first diaphragm having a first side and a second side, and a second diaphragm having a first side facing the first side of the first diaphragm. A first plurality of interconnect strips is disposed along at least the first side of the first diaphragm, a second plurality of interconnect strips is disposed along the first side of the first diaphragm, and a third plurality of interconnect strips is disposed along the first side of the second diaphragm. First, second, and third runner strips are disposed along the second side of the first diaphragm transverse to the first, second, and third plurality of interconnect strips, respectively. Each of the first, second, and third runner strips is electrically connected to at least a subset of the first, second, and third plurality of interconnect strips, respectively, via electrical connections disposed through the first diaphragm.Type: GrantFiled: April 7, 2022Date of Patent: December 17, 2024Assignee: Knowles Electronics, LLCInventors: Michael Pedersen, Peter V. Loeppert
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Patent number: 12167589Abstract: The present disclosure discloses a method of manufacturing a semiconductor structure and a semiconductor structure, and relates to the technical field of semiconductors. The method includes: providing a base, active regions arranged at intervals along a first direction being arranged in the base; forming, on the base, bit line structures arranged at intervals; forming a contact structure between two adjacent ones of the bit line structures; forming a barrier structure on the contact structure, the barrier structures being arranged in correspondence with and connected to the bit line structure, and a first recess being formed between any adjacent barrier structures; and forming a conductive structure in the first recess, the conductive structure including a protective layer and a conductive portion, and the protective layer wrapping a sidewall and a bottom wall of the conductive portion.Type: GrantFiled: June 1, 2022Date of Patent: December 10, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Guangji Li
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Patent number: 12167632Abstract: Disclosed are a display module and a display device capable of minimizing a pressed stain defect while reducing a bezel area. To this end, a thickness of a cushion portion of a cushion plate closer to a bent portion may be reduced, thereby reducing a bending radius of curvature such that the bezel area may be reduced. Further, placing a support layer having a strong supporting force formed of PET into the cushion plate such that the support layer is in contact with the heat-dissipation layer may allow minimizing an unevenness defect on the cushion plate even when a bent pad portion of a display panel presses the cushion portion. Thus, visibility of an internal pressed stain to a user may be minimized.Type: GrantFiled: November 17, 2021Date of Patent: December 10, 2024Assignee: LG Display Co., Ltd.Inventors: Jongseok Cha, Dongwon Jang, Buhui Lee, Junho Yun
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Patent number: 12166108Abstract: The present disclosure describes a structure with a conductive plate and a method for forming the structure. The structure includes a gate structure disposed on a diffusion region of a substrate, a protective layer in contact with the diffusion region and covering a sidewall of the gate structure and a portion of a top surface of the gate structure, and a first insulating layer in contact with the gate structure and the protective layer. The structure further includes a conductive plate in contact with the first insulating layer, where a first portion of the conductive plate laterally extends over a horizontal portion of the protective layer, and where a second portion of the conductive plate extends over a sidewall portion of the protective layer covering the sidewall of the gate structure. The structure further includes a second insulating layer in contact with the conductive plate.Type: GrantFiled: May 18, 2022Date of Patent: December 10, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chan-Yu Hung, Chia-Cheng Ho, Fei-Yun Chen, Yu-Chang Jong, Puo-Yu Chiang, Tun-Yi Ho
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Patent number: 12154832Abstract: According to an aspect of the present inventive concept there is provided a method for forming source/drain contacts, the method comprising: depositing a material layer over a first and second layer stack formed in a first and second device region of a substrate, respectively, each layer stack comprising a number of semiconductor channel layers and the layer stacks being separated by a trench filled with insulating material to form an insulating wall between the layer stacks and between the device regions; forming a contact partition trench in the material layer at a position above the insulating wall, and filling the contact partition trench with an insulating material to form a contact partition wall on top of the insulating wall; forming a first and a second source/drain contact trench on mutually opposite sides of the contact partition wall, the first source/drain contact trench being formed above a source/drain region in the first device region, and the second source/drain contact trench being formedType: GrantFiled: October 19, 2021Date of Patent: November 26, 2024Assignee: IMEC VZWInventors: Boon Teik Chan, Hans Mertens
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Patent number: 12156400Abstract: A semiconductor integrated circuit device includes a standard cell on a substrate, an one time programmable (OTP) memory structure at an edge portion of the standard cell, and a program transistor outside of the standard cell at a position adjacent to the edge portion of the standard cell at which the OTP memory structure is provided, the program transistor being electrically connected to the OTP memory structure. The OTP memory structure includes a first anti-fuse and a second anti-fuse. When a program voltage is applied to the program transistor and a bias power voltage is applied to the OTP memory structure, each of the first anti-fuse and the second anti-fuse becomes shorted and the bias power voltage is provided to the standard cell.Type: GrantFiled: May 10, 2022Date of Patent: November 26, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hoonsung Choi, Jiyoung Yun
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Patent number: 12145122Abstract: An apparatus for manufacturing a quantum dot is provided, the apparatus including a first supplying part that provides a cationic precursor, a second supplying part that provides an anionic precursor, a mixing part connected to the first supplying part and the second supplying part, and a reaction part including a reaction tube configured to receive a liquid mixture of the cationic precursor and the anionic precursor from the mixing part and a first microwave generator configured to provide a microwave that is transmitted through the reaction tube. Therefore, the apparatus may produce a quantum dot of multi-element compounds.Type: GrantFiled: October 12, 2020Date of Patent: November 19, 2024Assignee: Samsung Display Co., Ltd.Inventors: Taekjoon Lee, Baek Hee Lee, Junwoo Lee