Patents Examined by Mohammed R Alam
  • Patent number: 11569359
    Abstract: A semiconductor device includes a barrier layer, a dielectric layer, a first protection layer, a first spacer, and a gate. The dielectric layer is disposed on the barrier layer. The first protection layer is disposed on the barrier layer, in which the first protection layer extends from a first sidewall of the dielectric layer to a top surface of the barrier layer. The first spacer is disposed on and received by the first protection layer, in which a top end of the first protection layer comprises a first curved surface between the first spacer and the dielectric layer. The gate is disposed on the barrier layer, the dielectric layer, and the first spacer. The gate extends from a top surface of the dielectric layer and at least along the first curved surface of the first protection layer to make contact with the top surface of the barrier layer.
    Type: Grant
    Filed: November 10, 2021
    Date of Patent: January 31, 2023
    Assignee: INNOSCIENCE (ZHUHAI) TECHNOLOGY CO., LTD.
    Inventor: King Yuen Wong
  • Patent number: 11569378
    Abstract: A semiconductor device includes a first semiconductor structure. The first semiconductor structure includes a first semiconductor material having a band-gap. The first semiconductor structure has a first surface. An insulating layer has first and second opposing surfaces. The first surface of the insulating layer is on the first surface of the first semiconductor structure. A second semiconductor structure is on the second surface of the insulating layer and includes a second semiconductor material having a band-gap that is smaller than the band-gap of the first semiconductor material. A floating electrode couples the first semiconductor structure to the second semiconductor structure.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: January 31, 2023
    Assignee: Texas Instruments Incorporated
    Inventor: Christopher Boguslaw Kocon
  • Patent number: 11569358
    Abstract: A semiconductor device includes a barrier layer, a dielectric layer, a first spacer, a second spacer, and a gate. The dielectric layer is disposed on the barrier layer and defines a first recess. The first spacer is disposed on the barrier layer and within the first recess. The second spacer is disposed on the barrier layer and within the first recess. The first and second spacers are spaced apart from each other by a top surface of a portion of the barrier layer. The top surface of the portion of the barrier layer is recessed. The gate is disposed on the barrier layer, the dielectric layer, and the first and second spacers, in which the gate has a bottom portion located between the first and second spacers and making contact with the top surface of the portion of the barrier layer.
    Type: Grant
    Filed: November 10, 2021
    Date of Patent: January 31, 2023
    Assignee: INNOSCIENCE (ZHUHAI) TECHNOLOGY CO., LTD.
    Inventor: King Yuen Wong
  • Patent number: 11563100
    Abstract: Embodiments of the present disclosure provide a thin film transistor, a method for manufacturing a thin film transistor, an array substrate, a display panel, and a display device. The thin film transistor includes: a base substrate; an active layer, an insulating layer, and a source-drain layer sequentially stacked on the base substrate, wherein the source-drain layer is electrically connected to the active layer through a via hole penetrating the insulating layer; and a transition layer arranged between the source-drain layer and the active layer at a position of the via hole, wherein the transition layer covers a bottom of the via hole and covers at least part of a sidewall of the via hole, and the transition layer comprises elements of the active layer and elements of a part of the source-drain layer, the part of the source-drain layer being in contact with the transition layer.
    Type: Grant
    Filed: May 25, 2020
    Date of Patent: January 24, 2023
    Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Zheng Bao, Gong Chen, Yanxia Xin, Hongwei Hu, Yihao Wu, Yiyang Zhang, Guangzhou Zhao
  • Patent number: 11557611
    Abstract: Disclosed are a method and a device for manufacturing an array substrate, and an array substrate. The method includes: depositing and forming a gate insulation layer on a pre-formed base substrate and a pre-formed gate, the gate insulation layer covering the pre-formed gate; depositing and forming an amorphous silicon layer, a doped amorphous silicon layer including at least three doped layers, and a metal layer on the gate insulation layer in sequence, doping concentrations of the at least three doped layers of the doped amorphous silicon layer increasing from bottom to top; etching patterns of the amorphous silicon layer, the doped amorphous silicon layer and the metal layer to form the array substrate.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: January 17, 2023
    Assignee: HKC CORPORATION LIMITED
    Inventors: Qionghua Mo, En-tsung Cho
  • Patent number: 11552149
    Abstract: A light emitting display device includes: a light emitting element; a second transistor connected to a scan line; a first transistor which applies a current to the light emitting element; a capacitor connected to a gate electrode of the first transistor; and a third transistor connected to an output electrode of the first transistor and the gate electrode of the first transistor. Channels of the second transistor, the first transistor, and the third transistor are disposed in a polycrystalline semiconductor layer, and a width of a channel of the third transistor is in a range of about 1 ?m to about 2 ?m, and a length of the channel of the third transistor is in a range of about 1 ?m to about 2.5 ?m.
    Type: Grant
    Filed: October 2, 2020
    Date of Patent: January 10, 2023
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Keun Woo Kim, Tae Wook Kang, Han Bit Kim, Bum Mo Sung, Do Kyeong Lee, Jae Seob Lee
  • Patent number: 11552165
    Abstract: A semiconductor device includes a semiconductor substrate, a transistor section, a diode section, and a boundary section provided between the transistor section and the diode section in the semiconductor substrate. The transistor section has gate trench portions which are provided from an upper surface of the semiconductor substrate to a position deeper than that of an emitter region, and to each of which a gate potential is applied. An upper-surface-side lifetime reduction region is provided on the upper surface side of the semiconductor substrate in the diode section and a partial region of the boundary section, and is not provided in a region that is overlapped with the gate trench portion in the transistor section in a surface parallel to the upper surface of the semiconductor substrate.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: January 10, 2023
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Soichi Yoshida
  • Patent number: 11545570
    Abstract: The present disclosure generally to semiconductor devices, and more particularly to semiconductor devices having high-voltage transistors integrated on a semiconductor-on-insulator substrate and methods of forming the same. The present disclosure provides a semiconductor device including a semiconductor-on-insulator (SOI) substrate having a semiconductor layer, a bulk substrate and an insulating layer between the semiconductor layer and the bulk substrate, a source region and a drain region disposed on the bulk substrate, an isolation structure extending through the insulating layer and the semiconductor layer and terminates in the bulk substrate, and a gate structure between the source region and the drain region, the gate structure is disposed on the semiconductor layer.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: January 3, 2023
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Pinghui Li, Handoko Linewih, Darin Arthur Chan, Ruchil Kumar Jain
  • Patent number: 11545554
    Abstract: A semiconductor device includes a gate stack including a gate insulating layer and a gate electrode on the gate insulating layer. The gate insulating layer includes a first dielectric layer and a second dielectric layer on the first dielectric layer, and a dielectric constant of the second dielectric layer is greater than a dielectric constant of the first dielectric layer. The semiconductor device also includes a first spacer on a side surface of the gate stack, and a second spacer on the first spacer, wherein the second spacer includes a protruding portion extending from a level lower than a lower surface of the first spacer towards the first dielectric layer, and a dielectric constant of the second spacer is greater than the dielectric constant of the first dielectric layer and less than a dielectric constant of the first spacer.
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: January 3, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Doosan Back, Dongoh Kim, Gyuhyun Kil, Jung-Hoon Han
  • Patent number: 11545553
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, a first semiconductor layer, a second semiconductor layer, and a first insulating layer. A position of the third electrode in a first direction is between a position of the first electrode in the first direction and a position of the second electrode in the first direction. The first semiconductor layer includes Alx1Ga1-x1N and includes a first partial region, a second partial region, and a third partial region. The second semiconductor layer includes Alx2Ga1-x2N. A portion of the second semiconductor layer is between the third partial region and the third electrode in the second direction. The first insulating layer includes a first insulating region. The first insulating region is between the third electrode and the portion of the second semiconductor layer in the second direction.
    Type: Grant
    Filed: November 3, 2021
    Date of Patent: January 3, 2023
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Toshiki Hikosaka, Hiroshi Ono, Jumpei Tajima, Masahiko Kuraguchi, Shinya Nunoue
  • Patent number: 11538910
    Abstract: A semiconductor device is provided, which includes a substrate, a first and second doped wells, a drain and source regions, a gate structure, a field plate and a booster plate. The first and second doped wells are arranged in the substrate. The drain region is arranged in the first doped well and the source region is arranged in the second doped well. The gate structure is arranged over the substrate and between the source and drain regions. The field plate is arranged over the first doped well and the booster plate arranged between the field plate and the first doped well.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: December 27, 2022
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventor: Bong Woong Mun
  • Patent number: 11538930
    Abstract: A bidirectional blocking monolithic heterogeneous integrated Cascode-structure field effect transistor, which mainly solves a problem that the existing monolithic heterogeneous integrated Cascode-structure field effect transistor has no reverse blocking characteristic. The field effect transistor includes a substrate, a GaN buffer layer, an AlGaN barrier layer and a SiN isolation layer, wherein an isolation groove is etched in the middle of the SiN isolation layer, a Si active layer is printed on the SiN isolation layer on one side of the isolation groove so as to prepare a Si metal oxide semiconductor field effect transistor, and a GaN high-electron-mobility transistor is prepared on the other side of the isolation groove, and a drain electrode of the GaN high-electron-mobility transistor is in Schottky contact with the AlGaN barrier layer to form a bidirectional blocking monolithic heterogeneous integrated Cascode-structure field effect transistor.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: December 27, 2022
    Assignee: Xidian University
    Inventors: Chunfu Zhang, Weihang Zhang, Jiaqi Zhang, Guofang Yang, Yichang Wu, Dazheng Chen, Jincheng Zhang, Yue Hao
  • Patent number: 11527554
    Abstract: An array substrate, a manufacturing method thereof, and a display device are provided. The array substrate includes: a base substrate; a first thin film transistor located on the base substrate and including a first active layer; and a second thin film transistor located on the base substrate and including a second active layer; a matrix material of the first active layer is the same as that of the second active layer, and the first active layer and the second active layer satisfy at least one of the following conditions: a carrier mobility of the first active layer is greater than that of the second active layer, and a carrier concentration of the first active layer is greater than that of the second active layer. The array substrate is employed to compensate a difference in threshold voltage caused by a difference in channel width-to-length ratio of different thin film transistors.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: December 13, 2022
    Assignee: BEIJING BOE TECHNOLOGY DEVELOPMENT CO., LTD.
    Inventors: Libin Liu, Qian Yang
  • Patent number: 11527632
    Abstract: A gate electrode is formed on a semiconductor substrate between an n-type source region and an n-type drain region via a first insulating film. The first insulating film has second and third insulating films adjacent to each other in a plan view and, in a gate length direction of the gate electrode, the second insulating film is located on an n-type source region side, and the third insulating film is located on an n-type drain region side. The second insulating film is thinner than the third insulating film. The third insulating film is made of a laminated film having a first insulating film on the semiconductor substrate, a second insulating film on the first insulating film, and a third insulating film on the second insulating film, and each bandgap of the three insulating films is larger than that of the second insulating film.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: December 13, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yotaro Goto, Katsumi Eikyu, Yoshihiro Nomura
  • Patent number: 11527617
    Abstract: A semiconductor device includes a folded drain extended metal oxide semiconductor (DEMOS) transistor. The semiconductor device has a substrate including a semiconductor material with a corrugated top surface. The corrugated top surface has an upper portion, a lower portion, a first lateral portion extending from the upper portion to the lower portion, and a second lateral portion extending from the upper portion to the lower portion. The folded DEMOS transistor includes a body in the semiconductor material, a gate on a gate dielectric layer over the body, a drift region contacting the body, and a field plate on a field plate dielectric layer, all extending continuously along the upper portion, the first lateral portion, the second lateral portion, and the lower portion of the corrugated top surface. Methods of forming the folded DEMOS transistor are disclosed.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: December 13, 2022
    Assignee: Texas Instruments Incorporated
    Inventors: Sheldon Douglas Haynie, Alexei Sadovnikov
  • Patent number: 11509240
    Abstract: A switching device according to the present invention is a switching device for switching a load by on-off control of voltage, and includes an SiC semiconductor layer where a current path is formed by on-control of the voltage, a first electrode arranged to be in contact with the SiC semiconductor layer, and a second electrode arranged to be in contact with the SiC semiconductor layer for conducting with the first electrode due to the formation of the current path, while the first electrode has a variable resistance portion made of a material whose resistance value increases under a prescribed high-temperature condition for limiting current density of overcurrent to not more than a prescribed value when the overcurrent flows to the current path.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: November 22, 2022
    Assignee: ROHM CO., LTD.
    Inventors: Yuki Nakano, Hiroyuki Sakairi
  • Patent number: 11495675
    Abstract: The present disclosure provides a manufacture method of an LDMOS. The manufacture method includes: forming a drift region in a substrate; forming a gate structure on the substrate, the gate structure defining a source region and a drain region which are separated from each other, and the gate structure including a gate oxide layer and a gate conductor layer which are successively stacked on the substrate; forming a first doped region in the source region, wherein the first doped region is surrounded by the drift region; forming a first barrier layer with a first opening on the source region and in connect with sidewall of the gate structure; forming a first implantation region in the source region through self-aligned implantation on the basis of the first opening of the first barrier layer; and forming a second implantation region and a third implantation region respectively.
    Type: Grant
    Filed: July 14, 2021
    Date of Patent: November 8, 2022
    Assignee: JOULWATT TECHNOLOGY CO., LTD.
    Inventor: Guangtao Han
  • Patent number: 11482457
    Abstract: Techniques are described for forming strained fins for co-integrated n-MOS and p-MOS devices that include one or more defect trapping layers that prevent defects from migrating into channel regions of the various co-integrated n-MOS and p-MOS devices. A defect trapping layer can include one or more patterned dielectric layers that define aspect ratio trapping trenches. An alternative defect trapping layer can include a superlattice structure of alternating, epitaxially mismatched materials that provides an energetic barrier to the migration of defect. Regardless, the defect trapping layer can prevent dislocations, stacking faults, and other crystallographic defects present in a relaxed silicon germanium layer from migrating into strained n-MOS and p-MOS channel regions grown thereon.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: October 25, 2022
    Assignee: Intel Corporation
    Inventors: Karthik Jambunathan, Cory C. Bomberger, Anand S. Murthy
  • Patent number: 11482598
    Abstract: A device is described herein. The device comprises a unit cell of a silicon carbide (SiC) substrate. The unit cell comprises: a trench in a well region having a second conduction type. The well region is in contact with a region having a first conduction type to form a p-n junction. A width of the trench is less than 1.0 micrometers (?m). A width of the unit cell is one of less than and equal to 5.0 micrometers (?m). The device comprises a source region comprising the first conduction type. The device further comprises a metal oxide semiconductor field effect transistor component. The device described herein comprises a reduced unit cell pitch and reduced channel resistance without any compromise in channel length. The device comprises an ILD opening greater than or equal to width of the trench.
    Type: Grant
    Filed: October 5, 2021
    Date of Patent: October 25, 2022
    Assignee: GeneSiC Semiconductor Inc.
    Inventors: Siddarth Sundaresan, Ranbir Singh, Jaehoon Park
  • Patent number: 11482599
    Abstract: A device is described herein. The device comprises a unit cell of a silicon carbide (SiC) substrate. The unit cell comprises: a trench in a well region having a second conduction type. The well region is in contact with a region having a first conduction type to form a p-n junction. A width of the trench is less than 1.0 micrometers (?m). A width of the unit cell is one of less than and equal to 5.0 micrometers (?m). The device comprises a source region comprising the first conduction type. The device further comprises a metal oxide semiconductor field effect transistor component. The device described herein comprises a reduced unit cell pitch and reduced channel resistance without any compromise in channel length. The device comprises an ILD opening greater than or equal to width of the trench.
    Type: Grant
    Filed: March 4, 2022
    Date of Patent: October 25, 2022
    Assignee: GeneSiC Semiconductor Inc.
    Inventors: Siddarth Sundaresan, Ranbir Singh, Jaehoon Park