Abstract: An electrical device includes a counterdoped heterojunction selected from a group consisting of a pn junction or a p-i-n junction. The counterdoped junction includes a first semiconductor doped with one or more n-type primary dopant species and a second semiconductor doped with one or more p-type primary dopant species. The device also includes a first counterdoped component selected from a group consisting of the first semiconductor and the second semiconductor. The first counterdoped component is counterdoped with one or more counterdopant species that have a polarity opposite to the polarity of the primary dopant included in the first counterdoped component. Additionally, a level of the n-type primary dopant, p-type primary dopant, and the one or more counterdopant is selected to the counterdoped heterojunction provides amplification by a phonon assisted mechanism and the amplification has an onset voltage less than 1 V.

Abstract: An SOI lateral homogenization field high voltage power semiconductor device, and a manufacturing method and application thereof are provided. The device includes a type I conductive semiconductor substrate, a type II conductive drift region, a type I field clamped layer, type I and type II conductive well regions, the first dielectric oxide layer forming a field oxide layer, the second dielectric oxide layer forming a gate oxide layer, a type II conductive buried dielectric layer, a type II conductive source heavily doped region, a type II conductive drain heavily doped region. The first dielectric oxide layer and the floating field plate polysilicon electrodes form a vertical floating field plate distributed throughout the type II conductive drift region to form a vertical floating equipotential field plate array. When the device is in on-state, high doping concentration can be realized by the full-region depletion effect form the vertical field plate arrays.

Abstract: A display substrate comprises a pixel driving circuit and a bottom-emission light-emitting device that are disposed on a base and located in each sub-pixel in a display area. The light-emitting device includes a first electrode electrically connected to the pixel driving circuit. The pixel driving circuit includes a first storage capacitor and a second storage capacitor connected in parallel. The first storage capacitor includes a first storage electrode and a second storage electrode that are disposed oppositely, and the first electrode serves as the first storage electrode. The second storage capacitor includes the second storage electrode and a third storage electrode that are disposed oppositely. The second storage electrode is located between the first storage electrode and the third storage electrode. The first storage electrode is electrically connected to the third storage electrode. The first electrode, the second storage electrode, and the third storage electrode are all transparent electrodes.

Abstract: The embodiments of the present disclosure provide a memory and a manufacturing method of a memory. The memory includes first fins and second fins disposed on a substrate, a dielectric layer covering tops of the first fins and side wall surfaces exposed by an isolating structure, and work function layers disposed on a surface of the dielectric layer. In a direction parallel to an arrangement direction of the first fins and the second fins, the work function layers on the side walls where the adjacent first fins are opposite are provided with a first thickness, and the work function layers on the side walls where the first fins face towards the second fins are provided with a second thickness. The first thickness is greater than the second thickness.

Abstract: The present application provides a memory and a memory fabricating method. The memory includes a substrate, on which is disposed a separation layer, in which are arranged plural bitlines spaced apart from one another, the plural bitlines are arranged along a first direction, and each bitline is S-shaped. The method of fabricating the memory comprises the following steps: providing a substrate; forming on the substrate plural bitline grooves; forming in each bitline groove a first separation layer; forming bitlines on the first separation layer; forming a second separation layer on the bitlines; removing the substrate between adjacent separation walls, the separation wall including the first separation layer, the bitlines, and the second separation layer; and forming a third separation layer in a space between the adjacent separation walls, the third separation layer, the second separation layer, and the first separation layer together forming a separation layer.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device are provided. The semiconductor device includes a substrate and a conductive pad disposed on the substrate and having a first surface facing away from the substrate. The first surface of the conductive pad is recessed toward the substrate and defines a recessed portion. The semiconductor device also includes a capacitor structure at least partially-disposed within the recessed portion of the conductive pad and electrically connected with the substrate through the conductive pad.

Abstract: A thin film transistor and a manufacturing method therefor, an array substrate, and a display device. The thin film transistor includes an active layer, a gate insulating layer, and a gate electrode; the gate insulating layer is located on one side of the active layer; the gate electrode is located on one side of the gate insulating layer distant from the active layer; the gate electrode includes an opening a part of the active layer overlapped with the opening includes a first lightly doped region, a first heavily doped region, and a second lightly doped region that are sequentially arranged along a first direction parallel to a plane where the active layer is located.

Abstract: The application provides a method for manufacturing a semiconductor structure and the semiconductor structure, and relates to the technical field of semiconductors. The method for manufacturing the semiconductor structure includes: providing a base; sequentially stacking an initial conductive layer, an initial first dielectric layer, an initial first mask layer, an initial second dielectric layer, an initial second mask layer and a photoresist layer with a pattern on the base; and etching part of the initial second mask layer, part of the initial second dielectric layer and part of the initial first mask layer by taking the photoresist layer as a mask, so as to form a second dielectric layer with a trapezoidal structure which is of a structure with small top and large bottom.

Abstract: A light emitting display device includes: a light emitting element; a second transistor connected to a scan line; a first transistor which applies a current to the light emitting element; a capacitor connected to a gate electrode of the first transistor; and a third transistor connected to an output electrode of the first transistor and the gate electrode of the first transistor. Channels of the second transistor, the first transistor, and the third transistor are disposed in a polycrystalline semiconductor layer, and a width of a channel of the third transistor is in a range of about 1 ?m to about 2 ?m, and a length of the channel of the third transistor is in a range of about 1 ?m to about 2.5 ?m.

Abstract: A nanowire device includes one or more nanowire having a first end portion, a second end portion, and a body portion between the first end portion and the second end portion. A first conductive structure is in contact with the first end portion and a second conductive structure is in contact with the second end portion. The body portion of the nanowire has a first cross-sectional shape and the first end portion has a second cross-sectional shape different from the first cross-sectional shape. Integrated circuits including the nanowire device and a method of cleaning a semiconductor structure are also disclosed.

Abstract: A semiconductor device according to the embodiment includes: a first electrode; a second electrode; an oxide semiconductor layer provided between the first electrode and the second electrode; a gate electrode opposed to the oxide semiconductor layer; a gate insulating layer provided between the oxide semiconductor layer and the gate electrode; a first insulating layer provided between the gate electrode and the first electrode; and a second insulating layer provided between the gate electrode and the second electrode and having an oxygen atom concentration lower than an oxygen atom concentration of the first insulating layer.

Abstract: A semiconductor device includes a semiconductor substrate, an epitaxial layer disposed on the semiconductor substrate, a cell zone including multiple unit cells disposed in the epitaxial layer opposite to the semiconductor substrate, a transition zone having a doped region and surrounding the cell zone, a source electrode unit disposed on the epitaxial layer opposite to the semiconductor substrate, and multiple gate electrode units. Each unit cell includes a well region, a source region disposed in the well region, and a well contact region extending through the source region to contact the well region. A method for manufacturing the semiconductor device is also disclosed.

Abstract: A semiconductor structure includes: a substrate, a first conductive layer disposed on the substrate, a second conductive layer disposed on a surface of the first conductive layer away from the substrate, and third conductive layers covering side walls of the first conductive layer and in contact with the second conductive layer. Contact resistance between the third conductive layers and the second conductive layer is less than contact resistance between the first conductive layer and the second conductive layer.

Abstract: The present disclosure provides a method for manufacturing a memory, including: providing a substrate, and forming a sacrificial layer on the substrate; patterning the sacrificial layer, and forming a plurality of discrete pseudo bit line layers on the substrate; forming a support layer, the support layer filling areas between the adjacent pseudo bit line layers; removing the pseudo bit line layers to form bit line spaces between adjacent parts of the support layer; forming bit line structures, the bit line structures filling the bit line spaces, and the bit line structures including a bit line conductive layer and a bit line insulating layer sequentially stacked; and removing the support layer, and forming openings between the adjacent bit line structures.

Abstract: A method for manufacturing a memory includes: providing a substrate and multiple discrete pseudo bit line contact layers, a plurality of active areas being provided in the substrate, and each bit line contact layer being electrically connected to the active areas; forming pseudo bit line structures at tops of the pseudo bit line contact layers; forming sacrificial layers that fill regions between the adjacent pseudo bit line structures and are located on side walls of the pseudo bit line structures and the pseudo bit line contact layers; after forming the sacrificial layers, removing the pseudo bit line structures to form through holes exposing the pseudo bit line contact layers; removing the pseudo bit line contact layers to form through holes in the substrate; and forming bit line contact layers that fill the through holes in the substrate and are electrically connected to the active areas.

Abstract: The present disclosure discloses a semiconductor memory preparation method and a semiconductor memory, relating to the technical field of semiconductors. The method includes: providing a semiconductor substrate in which transistors are formed and have an array layout; forming a film stack structure on the semiconductor substrate; forming through holes penetrating the film stack structure to expose sources of the transistors; epitaxially growing a storage node contact layer on exposed surfaces of the sources of the transistors; and forming a bottom electrode of a capacitor on a surface of the storage node contact layer.

Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof, and relates to the technical field of semiconductors. The method of manufacturing the semiconductor structure includes: providing a substrate; forming, on the substrate, a first initial conductive layer, a sacrificial layer and a first mask layer with a pattern that are stacked sequentially, a thickness of the sacrificial layer being 10 nm-20 nm; and etching, with the first mask layer as a mask, the first initial conductive layer and the substrate to form a bit line (BL) contact region.

Abstract: A semiconductor structure includes a semiconductor substrate, a transistor, a plurality of isolation structures, and a conductive feature. The transistor is over the semiconductor substrate. The isolation structures are over the semiconductor substrate. The isolation structures define a semiconductor ring of the semiconductor substrate surrounding the transistor. The conductive feature extends vertically in the semiconductor substrate and surrounds the transistor and semiconductor ring. The conductive feature has a rounded corner facing the semiconductor ring from a top view.

Abstract: A photodetector array comprising at least one first sensor and at least one second sensor on the horizontal surface of the array substrate. The at least one first sensor is sensitive to radiation in a first wavelength range which comprises long-wavelength infrared wavelengths, and the at least one second sensor is sensitive to radiation in a second wavelength range which comprises wavelengths shorter than long-wavelength infrared. The array substrate comprises a vertical cavity on its horizontal surface, and the first sensor comprises a layer of pyroelectric material (65) which extends horizontally across the vertical cavity in the first area. A first part of a layer of two-dimensional layered material at least partly covers the layer of pyroelectric material (65), and a second part of the layer of two-dimensional layered material at least partly covers the foundation of the second sensor.

Abstract: The present invention provides a chemical sensor that can be manufactured at low cost and has high detection sensitivity.