Patents Examined by Mohammed Rehman
  • Patent number: 8607040
    Abstract: Methods and apparatuses for re-instantiating a firmware environment that includes one or more firmware functions available at pre-boot time when transitioning the computing device from a first, higher power consumption state to a second, lower power consumption state. The firmware environment determines whether a cryptographic signature on a firmware volume is verified; whether hardware resources of the computing device requested by a manifest of the firmware volume are available; and whether a firmware module of the firmware volume is compatible with installed firmware of the firmware environment. If so, the firmware environment reserves space in a memory to accommodate resources used by the firmware module, and executes the firmware module with the computing device in the second, lower power consumption state.
    Type: Grant
    Filed: November 16, 2010
    Date of Patent: December 10, 2013
    Assignee: Intel Corporation
    Inventors: Vincent J. Zimmer, Abdul M. Bailey, James W. Edwards, Rahul Khanna, Yu Fu Li, Di Tang
  • Patent number: 8589705
    Abstract: A host computer and a method for managing pulse-width modulation (PWM) include detecting a signal of a powerGD port. The management system further includes confirming a first state according to a first signal of the powerGD port. The management system further includes enabling the PWM port if the first state is in a power-on state, and disabling the PWM port if the first state is a power-off state.
    Type: Grant
    Filed: November 16, 2010
    Date of Patent: November 19, 2013
    Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.
    Inventors: Dong-Yan Dai, Jian Peng
  • Patent number: 8583945
    Abstract: A computer is disclosed with an operating system including a kernel and a task scheduler to schedule execution of one or more processes on the computer; a power estimator is coupled to the task scheduler to determine a required system power based on the number or type of processes scheduled for execution; and a variable load power supply including a plurality of power generators each having a predetermined power output and a power manager receiving instructions from the power estimator in the kernel, the power manager enabling a sufficient number of power generators to match the required power generated by the power estimator.
    Type: Grant
    Filed: June 11, 2010
    Date of Patent: November 12, 2013
    Assignee: Muse Green Investments LLC
    Inventor: Bao Tran
  • Patent number: 8578187
    Abstract: A portable power bank with card reading function includes a battery unit, a charging unit, a control unit, a voltage converting unit, a first card reading unit, and a connection interface unit. The battery unit is coupled with the charging unit and the voltage converting unit. The control unit is coupled with the charging unit, the voltage converting unit and the first card reading unit. The connection interface unit is coupled with the voltage converting unit and the control unit. The first card reading unit is configured for a first removable electronic card to insert thereinto. An electronic device is removably connected to the connection interface unit.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: November 5, 2013
    Assignee: Gigastone America Corp
    Inventor: John Wong
  • Patent number: 8578188
    Abstract: Methods, apparatus, and computer program products for implementing power management within Systems on Chips (SOCs). The method includes selecting an operating frequency for a chip from an operating frequency point set that provides a desired overall power dissipation value.
    Type: Grant
    Filed: October 2, 2012
    Date of Patent: November 5, 2013
    Assignee: Marvell International Ltd.
    Inventors: Yu Bai, Priya Vaidya, Premanand Sakarda
  • Patent number: 8578182
    Abstract: A power lock-up setting method and an electronic apparatus using the same are provided. The power lock-up setting method includes following steps. A trigger signal generated by a pressed power switch is received by a pin of a GPIO interface and transmitted to a control unit, such that the control unit starts the electronic apparatus, and a power-on-self-test of a logic processing unit is performed by a processing module. Whether the GPIO interface is set to a power lock-up state is determined by the logic processing unit. If so, a level of the pin is set to a disable level. An operating system is loaded by the processing module to perform an operating system booting process. Accordingly, when the electronic apparatus is under an operating environment of the operating system, the trigger signal is forbidden to be transmitted to the control unit when being generated again.
    Type: Grant
    Filed: June 14, 2010
    Date of Patent: November 5, 2013
    Assignee: Acer Incorporated
    Inventor: Jen-Te Chien
  • Patent number: 8572426
    Abstract: An apparatus includes a delay line having at least two parallel branches, where each branch includes multiple delay cells coupled in series. The delay line is configured to receive an input signal and to propagate the input signal in parallel through the delay cells in the branches. The apparatus also includes multiple sampling circuits configured to sample the input signal at different taps in the branches of the delay line and to output sampled values. The taps in a first of the branches are associated with different amounts of delay compared to the taps in a second of the branches. At least some of the delay cells in the branches of the delay line could have a minimum delay, and a difference in delay between at least one tap in the first branch and at least one tap in the second branch could be less than a smallest of the minimum delays.
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: October 29, 2013
    Assignee: National Semiconductor Corporation
    Inventors: Wai Cheong Chan, Matthew J. Schade
  • Patent number: 8560824
    Abstract: Methods and systems for executing a decompressed portion of an option memory in a shadow memory. An area of system memory is allocated and a portion of the option memory is decompressed using the allocated area. The decompressed portion is stored in the shadow memory so the decompressed portion can be executed in shadow memory.
    Type: Grant
    Filed: August 28, 2008
    Date of Patent: October 15, 2013
    Assignee: LSI Corporation
    Inventors: Jinwen Xie, Daniel G. Samuelrai, Bibhu Das, Anuj K. Jain, Audrius Stripeikis
  • Patent number: 8549337
    Abstract: A memory card control device includes an insertion unit to which a memory card is inserted, a memory card controller to control writing and reading of data to/from the memory card inserted in the insertion unit, an interface controller to send and receive the data written or read to/from the memory card to/from a host computer, a clock supplier to supply a clock signal to the memory card controller and the interface controller, a memory card detector to detect presence or absence of the memory card inserted in the insertion unit, and a low power consumption mode switching unit to switch the memory card controller and the interface controller to a low power consumption mode in response to the absence of the memory card detected by the memory card detector.
    Type: Grant
    Filed: November 13, 2008
    Date of Patent: October 1, 2013
    Assignee: Ricoh Company, Ltd.
    Inventor: Hirofumi Odaguchi
  • Patent number: 8543798
    Abstract: A system may include a printed circuit board, a first component located on the printed circuit board, the first component having a first unique identifier and a processor located on the printed circuit board, the processor including a one time programming section. The processor may acquire the first unique identifier from the first component and store the first unique identifier in the one time programming section during the first time initialization. Upon subsequent initializations, the processor may acquire the first unique identifier from the first component and compare the first unique identifier to the stored first unique identifier. The processor may allow the subsequent initializations to proceed if the first unique identifier matches the stored first unique. The processor may disallow the subsequent initializations from proceeding if the first unique identifier does not match the stored first unique identifier.
    Type: Grant
    Filed: August 14, 2012
    Date of Patent: September 24, 2013
    Assignee: Broadcom Corporation
    Inventors: Nanfang Hu, Xuezhang Dong, Yan Wang
  • Patent number: 8539259
    Abstract: A method of classification of power requirements in a power over Ethernet system, the method comprising: providing a first classification voltage for a first classification cycle time, the provided first classification voltage being within a classification voltage range defined by a lower classification voltage limit and upper classification voltage limit; measuring a first current flow responsive to the provided first classification voltage; subsequent to the first classification cycle time, providing a voltage outside of the classification voltage range for a classification indexing time; subsequent to the classification indexing time, providing a second classification voltage for a second classification cycle time, the provided second classification voltage being within the classification voltage range; measuring a second current flow responsive to the provided second classification voltage; determining a classification responsive to the measured first current flow and the measured second current flow; and
    Type: Grant
    Filed: February 28, 2010
    Date of Patent: September 17, 2013
    Assignee: Nevermore Solutions LLC
    Inventors: Yair Darshan, Eli Ohana
  • Patent number: 8539268
    Abstract: An apparatus and a method for controlling power consumption in a system having a plurality of modems are provided. In the method, whether an interrupt is generated in each modem is detected. An amount of current consumption of the system at a processing point of the generated interrupt is determined. The amount of current consumption of the system is compared with a threshold, so that the processing point of the generated interrupt is controlled.
    Type: Grant
    Filed: November 12, 2009
    Date of Patent: September 17, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: In-Chun Lim, Byung-Tae Kang, Jin-Woo Roh
  • Patent number: 8527787
    Abstract: A system and method for changing computing environments for a mobile platform device. The mobile platform includes a sensory and location determination engine coupled to a policy engine. The sensory and location determination engine determines a current location of the mobile platform device and the policy engine determines what applications to launch, what applications not to launch, and what core usage to invoke for the determined location of the mobile platform device.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: September 3, 2013
    Assignee: Intel Corporation
    Inventors: Burges M. Karkaria, Vincent J. Zimmer, Jim S. Baca
  • Patent number: 8522002
    Abstract: In one embodiment, a system, comprises a first computer system comprising at least a first diskless server, at least a first RAID controller coupled to the first diskless server, at least a first storage pool coupled to the RAID controller, and a remote management server coupled to the RAID controller via a an out-of-band communication link. The remote management server comprises a boot management module which, when executed, initiates a command to instruct the RAID controller to create at least a first logical volume in a memory module coupled to the RAID controller, transmits the command to the RAID controller via the out-of-band communication link, and transmits a boot image from the remote management server to the RAID controller via the out-of-band communication link. The RAID controller creates the first logical volume for the boot image in response to the command, and stores the boot image in the first logical volume.
    Type: Grant
    Filed: January 28, 2008
    Date of Patent: August 27, 2013
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Mark R. Watkins, Bradley G. Culter
  • Patent number: 8522054
    Abstract: A stand-by mode management module applied in a computer system having a BIOS (basic input/output system), a graphic module and a display module is provided. The computer system is operated in a working state and at least one stand-by state. The module includes a timer and an interrupt generation unit. The timer starts a count period when detecting that the computer system is idle. The interrupt generation unit generates an interrupt request to the BIOS to request the computer system to prepare to enter to a specific state when the count period is reached. When the specific state is entered, the computer system enters the stand-by state, a PLL (phase lock loop) of the display module keeps turning on, and PLLs other than the PLL of the display module are turned off and the graphic module acquires a frame stored in a fixed area of a storing unit and displays the acquired frame on the display module.
    Type: Grant
    Filed: November 17, 2009
    Date of Patent: August 27, 2013
    Assignee: Via Technologies, Inc.
    Inventors: Shuang-Shuang Qin, Cheng-Wei Huang
  • Patent number: 8516281
    Abstract: An access instruction associated with accessing a target location in a disk is obtained. A number of units until the target location is accessed is calculated. It is determined whether there is time for the group of logic to transition from a lower power state to an operational state; the determination is based at least in part on the number of units between a current location of a read head associated with the hard disk system and the target location which is different from the current location of the read head and a warm up time associated with the group of logic. If it is determined there is time, the group of logic is put into the lower power state.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: August 20, 2013
    Assignee: SK hynix memory solutions inc.
    Inventors: Kwok W. Yeung, Kin Ming Chan
  • Patent number: 8499178
    Abstract: An information handling system having plural processing modules, such as an information handling system blade chassis having plural information handling system blades, allocates power by determining an actual load sharing power loss associated with plural power supplies and applying the actual load sharing power loss to determine how much power to allocate to the information handling system modules. A chassis manager determines actual load sharing power loss by retrieving power information from plural power supplies. The actual load sharing power loss replaces a worst-case load sharing power loss assumed value to increase the amount power available for allocation to the information handling system modules.
    Type: Grant
    Filed: January 30, 2012
    Date of Patent: July 30, 2013
    Assignee: Dell Products L.P.
    Inventors: Timothy M. Lambert, Jaydev Reddy, Ashish Munjal
  • Patent number: 8458498
    Abstract: A processing platform and a method of controlling power consumption of a central processing unit of the processing platform are presented. By operating the method the processing platform is able to set an upper performance state limit and a lower performance state limit. The upper performance state limit is based on a central processing unit activity rate value and the lower performance state limit is based on a minimum require of the operating system to perform operating system tasks. The performance state values are varying within a range of the lower and upper limits according to a power management policy.
    Type: Grant
    Filed: December 23, 2008
    Date of Patent: June 4, 2013
    Assignee: Intel Corporation
    Inventors: Efraim Rotem, Barnes Cooper, Guy Therien, Eliezer Weissmann, Anil Aggarwal
  • Patent number: 8429394
    Abstract: A reconfigurable computing system for enabling high performance computing includes a host platform running an operating system (OS), a reconfigurable processing kernel module, a plurality of drivers interacting with the OS, one or more reconfigurable hardware modules, and a software stack interacting with the OS and providing access to the reconfigurable hardware. The reconfigurable processing kernel module manages reconfigurable processes and coordinates data transfer to and from host. In addition, the reconfigurable processing kernel modifies the OS to utilize the software stack, thereby enabling the use of reconfigurable hardware modules through the use of hardware specific driver instructions.
    Type: Grant
    Filed: March 12, 2009
    Date of Patent: April 23, 2013
    Assignee: Stone Ridge Technology
    Inventors: Vincent D. Natoli, David A. Richie
  • Patent number: 8386808
    Abstract: According to some embodiments, a power budget allocation engine of a multi-component computer system may receive a power budget allocation adjustment request signal from a first component. Based on the received budget allocation adjustment request signal (and, in some embodiments, a component preference), the power budget allocation engine may determine whether to adjust a power budget allocation signal provided to the first component.
    Type: Grant
    Filed: December 22, 2008
    Date of Patent: February 26, 2013
    Assignee: Intel Corporation
    Inventors: Guy Therien, Murali Ramadoss, Gregory D. Kaine, Eric C. Samson, Venkatesh Ramani