Abstract: An information device has a storage medium storing information items which includes a first program provided on a first partition, a second program and data provided on a second partition to restore the first program on the first partition to a predetermined state, a boot block which causes system activation from one of the first partition and the second partition, and an active-partition switching program which indicates, to the boot block, one of the first and second partitions. An input/output system activates the active-partition switching program when a specific operation is performed. The active-partition stitching program indicates to the boot block that system activation is to be executed from the second partition.
Abstract: In one embodiment, a system includes a power management controller that controls a duty cycle of a processor to manage power. By frequently powering up and powering down the processor during a period of time, the power consumption of the processor may be controlled while providing the perception that the processor is continuously available. Before powering the processor up, the power management control may determine whether or not there is work for the processor to perform. If there is no work to perform, the power management control may delay powering the processor up until there is work to perform, saving additional power. This additional power savings may be tracked, and may serve as a “credit” for the processor when subsequently powered up again.
Abstract: Embodiments of the claimed subject matter are directed to methods and a system that allows the reduction of costs attributed to executing applications on a multi-platform system (such as a mainframe) by migrating certain processes operating on one platform to another platform in the system. In one embodiment, the reduction of cost is achieved by a method for migrating an application executing in a partition operating a proprietary operating system to a second partition operating an alternate operating system and leveraging special purpose processors unavailable to the proprietary operating system, which can be much less costly to purchase and/or rent and license.
Abstract: Apparatus and method for clock edge synchronization among a plurality of devices. One of the plurality of devices is designated as a master device and one or more remaining devices as slave devices. The master device is configured for providing one or more gated master output clock signals based on a synchronization input signal and an input clock signal. The master device may be further configured to generate one or more gated master clock outputs to drive one or more slave devices, or to provide one or more slave synchronous master clock outputs. The one or more slave devices are configured for producing one or more slave output clock signals, based on the synchronization input signal and corresponding one or more gated master output clock signals. The one or more slave output clock signals are clock edge synchronized.
Type:
Grant
Filed:
February 10, 2011
Date of Patent:
August 26, 2014
Assignee:
Linear Technology Corporation
Inventors:
Leslie Catherine Muscha, Doug Allen LaPorte
Abstract: Methods and apparatus relating squelch filtration to limit false wakeups are described. In one embodiment, a squelch logic generates a wakeup event for an agent based on occurrence of a number of pulses (originating from another agent) during a time period. Other embodiments are also disclosed.
Type:
Grant
Filed:
June 30, 2009
Date of Patent:
August 19, 2014
Assignee:
Intel Corporation
Inventors:
Sin S. Tan, Srikanth T. Srinivasan, Bruce A Tennant, Dmitry Petrov
Abstract: Provided is a multiprocessor system and a compiler used in the system for automatically extracting tasks having parallelism from an input program to be processed, performing scheduling to efficiently operate processor units by arranging the tasks according to characteristics of the processor units, and generating codes for optimizing a system frequency and a power supply voltage by estimating a processing amount of the processor units.
Abstract: Methods and apparatuses for re-instantiating a firmware environment that includes one or more firmware functions available at pre-boot time when transitioning the computing device from a wake state to a sleep state. A network event received by the computing device while in a sleep state may be handled by the firmware environment independent of the operating system and without returning the entire computing device to the wake state.
Abstract: Systems, methods and media for allocating processing functions between a primary processor and a secondary processor are disclosed. In one embodiment, a primary processor performs routine processing duties, including execution of application program code, while the secondary processor is in a sleep state. When the load on the primary processor is deemed to be excessive, the secondary processor is awakened from a sleep state and assigned to perform processing functions that would otherwise need to be performed by the primary processor. If temperatures in the system rise above a threshold, the secondary processor is returned to the sleep state.
Type:
Grant
Filed:
July 13, 2006
Date of Patent:
August 12, 2014
Assignee:
International Business Machines Corporation
Abstract: One embodiment, having a corresponding method, features an integrated circuit comprising: a power supply terminal configured to receive electrical power; a core circuit powered by the electrical power, wherein the core circuit comprises a volatile memory configured to store data; a clock source configured to provide a clock signal at a selected frequency, wherein the selected frequency is one of a plurality of possible frequencies of the clock signal, and a processor configured to operate according to the clock signal; and a security circuit configured to reset the core circuit based on the selected frequency of the to clock signal and a voltage of the power supply terminal, wherein resetting the core circuit clears the data from the volatile memory.
Abstract: An operating system (OS) processing method for a host computer includes the following steps: when the host computer is booting, a boot loader is read from a boot reading device according to a boot priority order of the host computer. A signature detecting program included in the boot loader is executed to detect data stored in a specified address of a master boot record (MBR) of the host computer. When it is determined that the present version signature of the host computer does not match the preset version signature according to the data stored in the specified address, an OS image is read from the boot reading device, an OS is installed on the host computer according to the OS image. The data stored in the specified address of the MBR is amended according to an image version signature of the installed OS.
Type:
Grant
Filed:
December 13, 2011
Date of Patent:
July 22, 2014
Assignee:
Institute for Information Industry
Inventors:
Yen-Wen Huang, Chung-Ting Kao, Hui-Kuang Chung, Han-Chao Lee
Abstract: An interchangeable lens that can be detachably fitted to a camera body includes: a clock signal reception unit that receives a clock signal outputted from the camera body; a control command reception unit that receives a control command and data signal from the camera body, the control command and data signal being in synchrony with the clock signal, specifying a control command for the interchangeable lens and including type data specifying a type of the control command; a response generation unit that generates a response data signal including the type data on the basis of the control command and data signal; and a response transmission unit that transmits the response data signal to the camera body in synchrony with the clock signal received by the clock signal reception unit when a control command and data signal is received from the camera body in a next communication cycle.
Abstract: Provided is a computer system in which power consumption of the system can be reduced and which can smoothly supply data for a request from a client and avoid increase in a failure rate. In the computer system, by maintaining a power activation threshold for activating a stopping server blade and load balance threshold for assigning the request to a server blade, a server blade whose power is activated but to which the request from the client is not assigned is previously arranged. Priorities of the server blades are maintained, and are periodically changed or are changed in accordance with operation information such as total operation time and the number of times of activation/stop. Further, by maintaining the power activation threshold and a power stop threshold, possibilities of the unbalance among the activated/stopped server blades and frequent control of the activation/stop only in a part of server blades are avoided.
Abstract: The disclosed embodiments provide a system that facilitates synchronization between a first component and a second component connected to the first component via an interface in a computer system. During an active state of the interface, the system uses a local time base in the second component to generate a local clock signal that tracks a host clock signal from the first component. Next, during an inactive state of the interface, the system uses the local time base to maintain the local clock signal at the second component. Finally, during a subsequent active state of the interface after the inactive state, the system adjusts the local clock signal to remove clock drift between the local clock signal and the host clock signal.
Type:
Grant
Filed:
April 27, 2011
Date of Patent:
June 3, 2014
Assignee:
Apple Inc.
Inventors:
William P. Cornelius, William O. Ferry, Girault W. Jones
Abstract: Embodiments of the present invention provide a method that comprises, within a sample window, determining an active time of a central processing unit (CPU) at an operating frequency. If there are any different operating frequencies within the sample window, the method further comprises determining active times of the CPU at the different operating frequencies within the sample window and, based upon the active times for the operating frequencies within the sample window, calculating a millions of instructions per second (MIPS) value for the sample window. The method further comprises performing a comparison of the MIPS value to a threshold value and, based upon the comparison of the MIPS value to the threshold value, setting an operating frequency of the CPU for a next sample window.
Abstract: The described implementations relate to predictive computing device energy management. One implementation measures resource usage of a computing device that employs a power policy. This implementation also estimates resource usage of the computing device having at least one different power policy without actually running the at least one different power policy on the computing device.
Abstract: A method and apparatus are provided for reducing the energy consumption of an electronic terminal. The method implements a step of modifying the timeout-before-standby duration for said terminal after an action performed by and/or on said terminal at a current instant, depending on the membership of the current instant in a given temporal category, from among at least two predefined temporal categories.
Type:
Grant
Filed:
March 1, 2011
Date of Patent:
May 20, 2014
Assignee:
Compagnie Industrielle et Financiere d'Ingenierie “Ingenico ”
Inventors:
David Naccache, Eric Brier, Patrice Le Marre, Jean-Louis Sarradin, Jean-Sébastien Coron, Jean-Marie Aubanel
Abstract: A configurator is provided with the ability to enable a customer to configure a system based upon selection of components to reside within the system. Based upon selected components, the customer is presented with systems in which the selected components can reside.
Abstract: Without disposing any dedicated management module, it is possible to monitor sensors of shared sections shared among computer modules. A computer system includes a state machine for monitoring a power state of each computer module and a state of a baseboard management controller of the computer module, shared modules of shared sections shared among the computer modules, and switches corresponding to the shared modules for selecting one of the baseboard management controllers to establish connections between the baseboard management controllers and the shared modules. At occurrence of an abnormality in the power state or the baseboard management controller of any one of the computer modules, the state machine dynamically conducts a switching operation to designate one of the baseboard management controllers to monitor sensors of the shared modules.
Abstract: A circuit comprising a single-wire serial interface (SWSI), a delay module coupled to the SWSI and operable to introduce a delay during a data transmission, the delay being dependent on a local clock (LC) associated with the circuit, wherein the delay enables the circuit to synchronize the data transmission with a device coupled to the SWSI based on the LC.
Abstract: An apparatus is provided for generating a timing signal having an input for receiving a first signal indicating successive time intervals, means for receiving a second signal indicating successive time intervals, and a generator adapted to generate a timing signal based on the second signal and on a relationship between one or more time intervals of the first signal and one or more time intervals of the second signal. This arrangement enables a timing signal to be generated using a time signal produced by a source or device and to be based on a time signal produced by another source or device.
Type:
Grant
Filed:
March 9, 2010
Date of Patent:
May 6, 2014
Assignee:
Allen-Vanguard Corporation
Inventors:
Trevor Noel Yensen, Ryan Shawn Halpin, Jeffrey Lariviere