Abstract: An overclocking control method cooperates with an overclocking application of a computer system when the overclocking application is started. The overclocking control method includes the steps as follows. A BIOS enters an overclocking mode according to an executing state of the overclocking application. The BIOS receives a first triggering signal outputted from a south bridge chip, and the first triggering signal is generated by the south bridge chip according to a first button of the computer system. The BIOS selects a piece of corresponding overclocking information from a look-up table and loads the overclocking information into a register of the BIOS according to the first triggering signal to control the overclocking of the computer system.

Abstract: A method, system and computer-usable medium are disclosed for managing power consumption in information processing systems. Processing resources are successively folded, allowing them to be placed into deeper and deeper power saving states while maintaining the ability to respond to new processing loads without exposing the latency of the deeper power saving states as they are unfolded. Before a deeper power saving state can be used, there must be sufficient processing resources in the prior power saving state to mask the latency of bringing a processing resource out of the deeper power saving state.

Abstract: A storage system comprises multiple physical storage devices, and a power supply for the multiple physical storage devices. Each physical storage device requires an input of a first voltage and an input of a second voltage that is a lower voltage than the first voltage. The power supply comprises a first power supply circuit that is made redundant and a second power supply circuit that is made redundant. Each first power supply circuit outputs a first voltage, which is input to the respective physical storage devices. Each second power supply circuit outputs a second voltage to a storage device group (two or more physical storage devices of the multiple physical storage devices) corresponding to this second power supply circuit. Each second power supply circuit is isolated from a circuit board comprising the first power supply circuit.

Abstract: A method of booting a computing device includes, responsive to said computing device powering on, loading a first lightweight operating system on said computing device and executing an instant-on application through said lightweight operating system. The method further includes, during execution of said instant-on application, loading a hypervisor on said computing device and migrating said instant-on application to a first virtual machine executing a second lightweight operating system implemented by said hypervisor. The method further includes loading a full-feature operating system on a second virtual machine implemented by said hypervisor.

Abstract: A method and apparatus for optimizing a startup sequence to improve system boot time is described. In one embodiment, a method for configuring a startup sequence stored in memory, using one or more processors, to improve system boot time including accessing necessity indicia associated with a plurality of startup programs, wherein the necessity indicia comprising at least one of global reputation data or local interaction information, identifying at least one startup program to disable or postpone based on the necessity indicia and modifying at least one startup sequence to disable or delay execution of the at least one identified startup program.

Abstract: An information device has a storage medium storing information items which includes a first program provided on a first partition, a second program and data provided on a second partition to restore the first program on the first partition to a predetermined state, a boot block which causes system activation from one of the first partition and the second partition, and an active-partition switching program which indicates, to the boot block, one of the first and second partitions. An input/output system activates the active-partition switching program when a specific operation is performed. The active-partition switching program indicates to the boot block that system activation is to be executed from the second partition.

Abstract: The inter-clock domain data transfer FIFO circuit provides a circuit that transfers data between two clock domains of unrelated frequencies. The gate count is kept relatively low, thereby allowing data transfer between the two clock domains at one data item per cycle of the lower of the two frequencies. Depending on the frequency difference between the data producer and consumer, the initial latency could be as low as a fraction of a cycle and no more than two cycles of the consumer's clock. The operation of the data transfer FIFO circuit has been verified using gate-level simulations for several ratios of clock frequencies.

Abstract: A method and system for sharing platform data are described. The method for sharing platform data includes during a boot sequence of system firmware, accessing a first data structure tag associated with a resource accessible by the operating system. Also during the boot sequence of the system firmware, the method includes determining a memory address corresponding to platform specific data associated with the resource. During a boot time sequence of the system firmware, run time code is parsed. The method includes accessing a second tag that is visible to the operating system and associating it with the location of the platform specific data. This allows for the platform specific data to be consumed by an operating system during runtime in accordance with the industry common interfaces defined in ACPI.

Abstract: A method for managing power consumption in a data storage system is provided. The method comprises receiving a first input/output (I/O) request identifying an I/O operation to be performed by a storage device; delaying scheduling of the first I/O request to manage amount of power consumed by servicing the first I/O request; and forwarding the first I/O request to a storage controller associated with the storage device. The storage controller schedules the first I/O request using a scheduling mechanism, and the storage device services the first I/O request according to the scheduling mechanism.

Abstract: A method, system, and computer program for using an array of networked 3D voltage regulation modules (VRMs) to optimize power usage by components on a voltage island in real time is presented. The networked VRM devices work in parallel to supply adequate power to connected voltage islands, and to supplement other VRMs in the system that may require additional power in the case of a critical event.

Abstract: This invention manages a power consumption of a system including a computer and a storage in combination with a workload of a business application. More specifically, a power consumption per transaction processing count is employed as an index that an application user utilizes as a guide for adjusting a power consumption amount. Further, the invention provides means that adjusts a power consumption per workload based on a trade off between power consumption and system performance. When adjusting the power consumption, the system configuration is modified so as to increase or decrease computer resources such as a disk or a server that the application utilizes.

Abstract: Circuits and methods for providing control of a power up sequence for supplying a gated power supply to a circuit portion. A power switch fabric is provided having more than two chains with more than two bits of control. The chains include power switches that are sequentially enabled in response to control signal to supply a virtual power supply to a gated circuit to support power gating. The power switches may include daughter switches and mother switches, where the mother switches are enabled later in time than the daughter switches. The enable signals to allow the virtual power supply to begin powering up may be timed to control the ramp up time, in rush current and peak current during the power up sequence of the virtual power supply. Methods for providing timing for the daughter and mother switches and enables to multiple chains in a power switch fabric are disclosed.

Abstract: Methods and devices for initial bootstrap of a user terminal are provided. The user terminal transmits at least one first message to an initial bootstrap server. The first message includes device management capability information for the user terminal. The initial bootstrap server selects a device management protocol to be used by the user terminal and sends the selected device management protocol to the user terminal in at least one second message.

Abstract: A computer system for automatically overclocking includes an overclocking element, a detecting circuit and a basic input/output system (BIOS). The overclocking element has a signal standard. The detecting circuit is used for acquiring an I/O signal of the overclocking element. The BIOS is used for comparing the signal standard with the I/O signal to obtain a comparing result. The BIOS is further used for adjusting a reference signal according to the comparing result. The reference signal is an input signal of the overclocking element.

Abstract: According to one embodiment, an electronic device includes: a switch which switches between connection and disconnection of a sideband signal transmitted by a device attached to the electronic device; a power switch circuit which switches between supply and interrupt of power to the device; a nonvolatile memory which holds a setting; and a control section which controls the switch and the power switch circuit based on the setting.

Abstract: Within a system comprising a programmable integrated circuit (IC), a method can include storing a first configuration within the system in a read-only memory that is independent of the programmable IC. The programmable IC, being loaded with the first configuration, comprises a circuit that accesses a data source external to the system over a communication link. A second configuration can be downloaded by the programmable IC from the data source. The second configuration can be stored within a random access memory within the system that is independent of the programmable IC. Responsive to a reconfiguration event, the programmable IC can be loaded with the second configuration from the random access memory.

Abstract: The invention provides a method, apparatus and system for reducing power consumption involving data storage devices. One embodiment involves storing data in a first memory; in response to the first memory exceeding a first threshold, migrating the data from the first memory to a second memory; in response to the second memory exceeding a second threshold, then activating a third memory if the third memory is in active; and in response to the second memory exceeding a third threshold greater than the second threshold, migrating the data from the second memory to a third memory; wherein the second memory is sized and configured to store data targeted for the third memory to intelligently maintain a portion of the third memory in an inactive state.

Abstract: In a method for adjusting power-saving strategy of a peripheral device controller in communication with a CPU, whether the CPU is in a working state while the peripheral device enters a power-saving mode is first determined. Then, interrupt the CPU at relatively short intervals during the power-saving mode if the CPU is in the working state; and interrupt the CPU at relatively long intervals during the power-saving mode if the CPU is not in the working state.

Abstract: Methods, apparatus, and computer program products for implementing power management within Systems on Chips (SOCs). The method includes selecting an operating frequency for a chip from an operating frequency point set that provides a desired overall power dissipation value.

Abstract: A system and method for using a link energy signal in physical layer devices (PHYs) having a silent channel/interface in energy efficient Ethernet (EEE). LPI modes in EEE suffer deficiencies in cable unplug detection due to the latency in refresh cycles. LPI modes in EEE also suffer from potential frequency drift, which leads to high bit error rate (BER) when coming out of LPI mode. A link energy signal transmitted during LPI modes enables real-time detection of cable unplug and the frequency lock to be maintained.