Abstract: A device may detect a semiconductor wafer to be transferred from a source wafer carrier to a target wafer carrier, and may cause a light source to illuminate the semiconductor wafer. The device may cause a camera to capture images of the semiconductor wafer after the light source illuminates the semiconductor wafer, and may perform image recognition of the images of the semiconductor wafer to determine whether an edge of the semiconductor wafer is damaged. The device may cause the semiconductor wafer to be provided to the source wafer carrier when the edge of the semiconductor wafer is determined to be damaged, and may cause the semiconductor wafer to be provided to the target wafer carrier when the edge of the semiconductor wafer is determined to be undamaged.

Abstract: A lower nanosheet stack including alternating layers of a first work function metal and a semiconductor channel material, an upper nanosheet stack including alternating layers of a second work function metal and the semiconductor channel material, one or more dielectric layers between the lower nanosheet stack and the upper nanosheet stack, each separated by an inner spacer. An embodiment where the one or more partial dielectric layers each include an opening. Forming an upper nanosheet stack vertically aligned above an intermediate stack, vertically aligned above a lower nanosheet stack, the upper nanosheet stack, the lower nanosheet stack each including alternating layers of a first sacrificial material and a semiconductor channel material, the intermediate stack including one or more alternating layers of the sacrificial material and a second sacrificial material, recessing the second sacrificial material; and forming second inner spacers where the second sacrificial material was recessed.

Abstract: A transportation method for transporting an object including a plurality of Fabry-Perot interference filters, the transportation method including a first step of accommodating the object in an accommodating container, wherein the Fabry-Perot interference filter includes a substrate, a first mirror portion and a second mirror portion provided on the substrate to face each other via a gap and in which a distance from each other is variable, and in the first step, the object is accommodated and supported in the accommodating container in a state where the plurality of Fabry-Perot interference filters is two-dimensionally arranged.

Abstract: A method for adjusting a height of an edge ring arranged around an outer portion of a substrate support includes receiving at least one input indicative of one or more erosion rates of the edge ring. The at least one input includes a plurality of erosion rates for respective usage periods of a substrate processing system. The method further includes determining at least one erosion rate of the edge ring using the plurality of erosion rates for the respective usage periods, monitoring an overall usage of the edge ring and storing the overall usage of the edge ring in a memory, calculating an amount of erosion of the edge ring based on the determined at least one erosion rate and the overall usage of the edge ring, and adjusting the height of the edge ring based on the calculated amount of erosion to compensate for the calculated amount of erosion.

Abstract: An inverter cell having a logical function and a filler cell having no logical function are placed adjacent to each other. Nanowires of the filler cell are placed at the same positions as nanowires of the inverter cell in the Y direction. A p-type dummy transistor and n-type dummy transistor of the filler cell are respectively placed at the same levels as a p-type transistor and n-type transistor of the inverter cell in the Z direction.

Abstract: A ruthenium film forming method includes: causing chlorine to be adsorbed to an upper portion of a recess at a higher density than to a lower portion of the recess by supplying a chlorine-containing gas to a substrate including an insulating film and having the recess; and forming a ruthenium film in the recess by supplying a Ru-containing precursor to the recess to which the chlorine is adsorbed.

Abstract: A second substrate including a pixel circuit that outputs a pixel signal on a basis of electric charges outputted from the sensor pixel and a third substrate including a processing circuit that performs signal processing on the pixel signal are provided. The first substrate, the second substrate, and the third substrate are stacked in this order. A semiconductor layer including the pixel circuit is divided by an insulating layer. The insulating layer divides the semiconductor layer to allow a center position of a continuous region of the semiconductor layer or a center position of a region that divides the semiconductor layer to correspond to a position of an optical center of the sensor pixel, in at least one direction on a plane of the sensor pixel perpendicular to an optical axis direction.

Abstract: A memory device having an error detection function and being capable of storing a large amount of data per unit area is provided. A driver circuit of the memory device is formed using a transistor formed on a semiconductor substrate, and a memory cell of the memory device is formed using a thin film transistor. A plurality of layers each of which includes a memory cell using the thin film transistor can be stacked over the semiconductor substrate, so that the amount of data that can be stored per unit area can be increased. Part of a peripheral circuit including the memory device can be formed using a thin film transistor, and thus, an error detection circuit is formed using the thin film transistor and stacked over the semiconductor substrate.

Abstract: A substrate includes a support structure comprising a polycrystalline ceramic core, a first adhesion layer encapsulating the polycrystalline ceramic core, a barrier layer encapsulating the first adhesion layer, a second adhesion layer coupled to the barrier layer, and a conductive layer coupled to the second adhesion layer. The substrate also includes a bonding layer coupled to the support structure, a substantially single crystal silicon layer coupled to the bonding layer, and an epitaxial semiconductor layer coupled to the substantially single crystal silicon layer.

Abstract: Various embodiments of the present disclosure are directed towards a method for non-destructive inspection of cell etch redeposition. In some embodiments of the method, a grayscale image of a plurality of cells on a wafer is captured. The grayscale image provides a top down view of the cells and, in some embodiments, is captured in situ after etching to form the cells. The cells are identified in the grayscale image to determine non-region of interest (non-ROI) pixels corresponding to the cells. The non-ROI pixels are subtracted from the grayscale image to determine ROI pixels. The ROI pixels are remaining pixels after the subtracting and correspond to material on sidewalls of, and in recesses between, the cells. An amount of etch redeposition on the sidewalls and in the recesses is then scored based on gray levels of the ROI pixels. Further, the wafer is processed based on the score.

Abstract: An apparatus configured to join electronic components to an electronic substrate includes a chamber housing including a tunnel extending through multiple processing zones, a conveyor configured to transport electronic substrates in the tunnel through the multiple processing zones, and a heat detection system including at least one temperature sensor coupled to the chamber housing. The at least one temperature sensor is configured to detect temperatures of the electronic substrates passing proximate to the at least one temperature sensor. The apparatus further includes a controller coupled to the multiple processing zones, the conveyor and the heat detection system. The controller is configured to receive temperature data from the heat detection system.

Abstract: A light-emitting device is provided. The light-emitting device includes a light-emitting diode, a reflective structure, and a package structure. The reflective structure includes a bottom surface and a lateral part. The light-emitting diode is disposed on the bottom surface. The lateral part is disposed surrounding the bottom surface and disposed on the bottom surface. The package structure is configured to package the light-emitting diode and the reflective structure. The package structure includes a first package part and a second package part. The first package part has a phosphorescent powder. An interface is between the first package part and the second package part. The interface is disposed below a top surface of the lateral part.

Abstract: A package structure is provided. The package structure includes a leadframe, a GaN power device, and an electrostatic discharge protection component. The leadframe includes a gate pad, a source pad, and a drain pad, which are disposed on the leadframe. The GaN power device has a gate end. The GaN power device is disposed on the source pad of the leadframe. The electrostatic discharge protection component includes a first pad. The first pad is disposed on the electrostatic discharge protection component. The electrostatic discharge protection component is disposed on the source pad of the leadframe. The gate end of the GaN power device is electrically connected to the first pad of the electrostatic discharge protection component. The first pad of the electrostatic discharge protection component is electrically connected to the gate pad of the leadframe.

Abstract: Provided is a semiconductor device includes a substrate, an isolation structure, an alignment mark, and a dielectric layer. The substrate includes a first region and a second region. The isolation structure is disposed in the substrate in the first region, wherein the isolation structure extends from a first surface of the substrate toward a second surface of the substrate. The alignment mark is disposed in the substrate in the second region. The alignment mark extends from the first surface of the substrate toward the second surface of the substrate and at the same level as the isolation structure. The dielectric layer is buried in the substrate in the second region and overlapping the alignment mark.

Abstract: A process recipe associated with a substrate at a manufacturing system is identified. A first set of measurements for the substrate is obtained from a substrate measurement subsystem. A second set of measurements for the substrate is obtained from one or more sensors of a chamber of the manufacturing system. A determination is made based on the obtained first set of measurements and the obtained second set of measurements of whether to modify the process recipe by at least one of modifying an operation of the process recipe or generating an instruction to prevent completion of execution of one or more operations of the process recipe.

Abstract: Structures for a photonics chip that include a fully-depleted silicon-on-insulator field-effect transistor and related methods. A first device region of a substrate includes a first device layer, a first portion of a second device layer, and a buried insulator layer separating the first device layer from the first portion of the second device layer. A second device region of the substrate includes a second portion of the second device layer. The first device layer, which has a thickness in a range of about 4 to about 20 nanometers, transitions in elevation to the second portion of the second device layer with a step height equal to a sum of the thicknesses of the first device layer and the buried insulator layer. A field-effect transistor includes a gate electrode on the top surface of the first device layer. An optical component includes the second portion of the second device layer.

Abstract: Embodiments of the present disclosure generally relate to methods and apparatus for backside stress engineering of substrates to combat film stresses and bowing issues. In one embodiment, a method of depositing a film layer on a backside of a substrate is provided. The method includes flipping a substrate at a factory interface so that the backside of the substrate is facing up, and transferring the flipped substrate from the factory interface to a physical vapor deposition chamber to deposit a film layer on the backside of the substrate. In another embodiment, an apparatus for depositing a backside film layer on a backside of a substrate, which includes a substrate supporting surface configured to support the substrate at or near the periphery of the substrate supporting surface without contacting an active region on a front side of the substrate.

Abstract: A magnetic tunnel junction is disclosed wherein the reference layer and free layer each comprise one layer having a boron content from 25 to 50 atomic %, and an adjoining second layer with a boron content from 1 to 20 atomic %. One of the first and second layers in each of the free layer and reference layer contacts the tunnel barrier. Each boron containing layer has a thickness of 1 to 10 Angstroms and may include one or more B layers and one or more Co, Fe, CoFe, or CoFeB layers. As a result, migration of non-magnetic metals along crystalline boundaries to the tunnel barrier is prevented, and the MTJ has a low defect count of around 10 ppm while maintaining an acceptable TMR ratio following annealing to temperatures of about 400° C. The boron containing layers are selected from CoB, FeB, CoFeB and alloys thereof including CoFeNiB.

Abstract: The collapsed pattern recovering method is a method for recovering a collapsed pattern which is a pattern formed on a front surface of a substrate, and the method includes a reactive gas supplying step which supplies to the front surface of the substrate a reactive gas that can react with a product existing on the front surface. The reactive gas supplying step includes a hydrogen fluoride vapor supplying step which supplies vapor that contains hydrogen fluoride to the front surface of the substrate. The collapsed pattern recovering method further includes a substrate heating step which heats the substrate in parallel with the hydrogen fluoride vapor supplying step.

Abstract: A workpiece processing method for processing a workpiece using a processing apparatus including a chuck table, a processing unit, a moving mechanism for moving the chuck table and the processing unit relative to each other, and an imaging unit for imaging the workpiece, where the chuck table includes a holding member formed by a transparent body and a supporting member supporting a part of the holding member and connected to an angle control mechanism. The method includes a tape affixing step, a holding step of holding the workpiece by the chuck table via the tape, and an identifying step of imaging the top surface side of the workpiece through the transparent holding member by the imaging unit positioned in a region that is on a lower side of the holding member and is not superimposed on the supporting member, and identifying a region to be processed in the workpiece.