Patents Examined by Mohammed Shamsuzzaman
  • Patent number: 10444396
    Abstract: Various embodiments include systems and methods of operation with respect to well logging. The systems and methods can include a number of transmitter sensors and a number of receiving sensors arranged to operate as a system including one or more multi-pole sensors. Such systems may be controlled to generate deep high-order azimuthal sensitivity. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: December 31, 2012
    Date of Patent: October 15, 2019
    Assignee: Halliburton Energy Services, Inc.
    Inventor: Burkay Donderici
  • Patent number: 10436939
    Abstract: The disclosed embodiments include a method, apparatus, and computer program product for generating hybrid computational meshes around complex and discrete fractures for the purpose of reservoir simulation. For example, one disclosed embodiment includes a method that comprises receiving a set of 3D fracture surfaces with geometry that has been discretized in a 2D manifold by a collection of polygons. The method defines a family of non-intersecting 2D slicing surfaces for slicing the set of 3D fracture surfaces. The method then uses the intersection of the 2D slicing surface with the 2D manifolds defining the fracture surfaces to create a set of 2D fractures on each slicing surface. Following a series of steps, the method generates three-dimensional shells connecting a set of stadia corresponding to each fracture on each 2D slicing surface to a corresponding set of stadia on a neighboring 2D slicing surface for creating a three-dimensional model.
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: October 8, 2019
    Assignee: Landmark Graphics Corporation
    Inventors: Steven Bryan Ward, Michael Loyd Brewer
  • Patent number: 10431551
    Abstract: Systems and methods for visual identification of semiconductor dies are described. In some embodiments, a method may include: receiving a semiconductor wafer having a plurality of dies and printing a unique visual identification mark on each of the plurality of dies. In other embodiments, a method may include receiving an electronic device comprising a die and a package surrounding at least a portion of the die and reading, from the electronic device, a unique visual identification mark that encodes a Cartesian coordinate of the die relative to a reference point on a semiconductor wafer.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: October 1, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kenneth Michael Butler, Kalyan Chakravarthy Cherukuri, Stephanie Watts Butler, Venkataramanan Kalyanaraman, Hubert Joseph Payne, Yazdi Dinshaw Contractor
  • Patent number: 10418530
    Abstract: An optoelectronic semiconductor chip having a semiconductor body (1) that is suitable for emitting electromagnetic radiation in a first wavelength range from a radiation exit face (3) is specified. Furthermore, the semiconductor chip comprises a ceramic or monocrystalline conversion platelet (6) that is suitable for converting electromagnetic radiation in the first wavelength range into electromagnetic radiation in a second wavelength range, which is different from the first wavelength range, and a wavelength-converting joining layer (7) that connects the conversion platelet (6) to the radiation exit face (3), wherein the wavelength-converting joining layer (7) has luminescent material particles (4) that are suitable for converting radiation in the first wavelength range into radiation in a third wavelength range, which is different from the first wavelength range and the second wavelength range. The wavelength-converting joining layer (7) furthermore has a thickness of no more than 30 micrometers.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: September 17, 2019
    Assignee: OSRAM OPTO SEMICONDUCTORS GMBH
    Inventors: Reiner Windisch, Joerg Erich Sorg, Ralph Wirth
  • Patent number: 10411111
    Abstract: A method for fabricating a high-voltage insulated gate type bipolar semiconductor device by comparing to a reference structure of the same includes determining a width S of a mesa region in which the gate insulating film and the MOS transistor are formed, and a trench depth DT, based on a scaling ratio K, in comparison with a second width and a second trench depth of the reference structure, and setting a cell width 2W of the high-voltage insulated gate type bipolar semiconductor device to be equal in length to a second length of the reference structure, the scaling ratio K being defined as K=Y/X, where X indicates a size of a target portion to be miniaturized in the high-voltage insulated gate type bipolar semiconductor device, and Y indicates a size of a target portion to be miniaturized in the reference structure.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: September 10, 2019
    Assignee: KYUSHU INSTITUTE OF TECHNOLOGY
    Inventors: Ichiro Omura, Masahiro Tanaka, Masanori Tsukuda, Yamato Miki
  • Patent number: 10410854
    Abstract: The present disclosure generally relates to methods for cleaning the backside of a wafer. A wet cleaning method may be used by stripping off the uppermost spacer layers on the backside of the wafer using a cleaning solution. In one embodiment, hydrogen fluoride (HF) solution may be employed to remove the nitride/oxide spacer layer. In another embodiment, a dry cleaning method may be employed to etch the wafer at the bevel region. Residues are completely removed from the wafer backside. This method improves the yield and storage life of the semiconductor wafers.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: September 10, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Honghui Mou, Xiaodong Li, Yun Ling Tan, Alex See, Liang Li
  • Patent number: 10411014
    Abstract: Disclosed are a semiconductor device capable of reducing parasitic capacitance between adjacent conductive structures and a method for fabricating the same. The semiconductor device includes a plurality of bit line structures each comprising a first contact plug formed over a substrate and a bit line formed over the first contact plug. A spacer structure having air gaps is formed on sidewalls of the first contact plug and on sidewalls of the bit line. An plug isolation layer is formed between the plurality of bit line structures. The isolation layer includes an opening. A second contact plug is formed in the opening and a memory element is formed over the second contact plug.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: September 10, 2019
    Assignee: SK hynix Inc.
    Inventors: Chang-Youn Hwang, Noh-Jung Kwak, Hong-Gu Yi, Yun-Je Choi, Se-Han Kwon, Ki-Soo Choi, Seung-Bum Kim, Do-Hyung Kim, Doo-Sung Jung, Dae-Sik Park
  • Patent number: 10401804
    Abstract: CAD modeling method, system, and apparatus provide an on-demand mate controller for controlling settings of mating relationships in a CAD model. The names of mates of a CAD model assembly are auto-populated into an ordered list in the mate controller. The mate controller enables user interactive re-ordering of the listed names. With the mate controller, a user may temporarily unlock a mate, visually position assembly components, and relock the mate resulting in refined mate settings and degrees of freedom of assembly components. The mate controller enables a user to interactively change order of positions of the model assembly which in turn affects order of position changes in motion studies of the model assembly. The mate controller saves per position data of the model assembly including mate values and component degrees of freedom. The saved per position data can be readily used to create animations.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: September 3, 2019
    Assignee: Dassault Systemes SolidWorks Corporation
    Inventors: Donald Van Zile, III, Zheng Ye, Adrian Ilie
  • Patent number: 10403789
    Abstract: This disclosure discloses a light-emitting element having a light-emitting unit, a transparent layer and a wavelength conversion layer formed on the transparent layer. The transparent layer covers the light-emitting unit. The wavelength conversion layer includes a phosphor layer having a phosphor and a stress release layer without the phosphor.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: September 3, 2019
    Assignee: Epistar Corporation
    Inventors: Ching-Tai Cheng, Ju-lien Kuo, Min-Hsun Hsieh, Shau-Yi Chen, Shih-An Liao, Jhih-Hao Chen
  • Patent number: 10403571
    Abstract: A plurality of lands is formed apart from each other on a surface of a package substrate. Another plurality of lands is formed apart from each other on a surface of a printed wiring board. The surface of the package substrate and the surface of the printed wiring board face each other. The plurality of lands and another plurality of lands are bonded to each other with solder having a height of 30% or less of a diameter of a solder bonding portion at the corresponding land. A ratio of a solder bonded area of at least each of lands, among another plurality of the lands, of which distance value to a corresponding one of the lands is larger than an average distance value between the lands and another lands, to a solder bonded area of the corresponding one of the lands is 56% or more and 81% or less.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: September 3, 2019
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Kunihiko Minegishi
  • Patent number: 10403703
    Abstract: A display device having a reduced frame width and a shape that is not significantly different from the shape of a display region is provided even in the case where the display region is non-rectangular. The display device includes a display region and a terminal electrode. The terminal electrode overlaps with the display region and is electrically connected to an external electrode through the non-display side of the display region.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: September 3, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 10396185
    Abstract: A method of forming a finFET transistor device includes forming a crystalline, compressive strained silicon germanium (cSiGe) layer over a substrate; masking a first region of the cSiGe layer so as to expose a second region of the cSiGe layer; subjecting the exposed second region of the cSiGe layer to an implant process so as to amorphize a bottom portion thereof and transform the cSiGe layer in the second region to a relaxed SiGe (rSiGe) layer; performing an annealing process so as to recrystallize the rSiGe layer; epitaxially growing a tensile strained silicon layer on the rSiGe layer; and patterning fin structures in the tensile strained silicon layer and in the first region of the cSiGe layer.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: August 27, 2019
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, STMICROELECTRONICS, INC
    Inventors: Bruce B. Doris, Hong He, Nicolas J. Loubet, Junli Wang
  • Patent number: 10396261
    Abstract: A method of manufacturing a light emitting device includes: providing a substantially flat plate-shaped base member which in plan view includes at least one first portion having an upper surface, and a second portion surrounding the at least one first portion and having inner lateral surfaces; mounting at least one light emitting element on the at least one first portion; shifting a relative positional relationship between the at least one first portion and the second portion in an upper-lower direction to form at least one recess defined by an upper surface of the at least one first portion that serves as a bottom surface of the at least one recess and at least portions of the inner lateral surfaces of the second portion that serve as lateral surfaces of the at least one recess; and bonding the at least one first portion and the second portion with each other.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: August 27, 2019
    Assignee: Nichia Corporation
    Inventor: Tsuzuki Takahashi
  • Patent number: 10396213
    Abstract: An active device array substrate includes a substrate, first and second active devices, a gate insulation layer and an insulation barrier layer. The first and second active devices respectively includes first and second gate electrodes, first and second semiconductor blocks, first and second source electrodes, and first and second drain electrodes. A film layer of the second source electrode and the second drain electrode is the same with that of the first source electrode or the first drain electrode. The gate insulation layer is located between the first gate electrode and the first semiconductor block and between the second gate electrode and the second semiconductor block. The insulation barrier layer is disposed on the gate insulation layer, and covers the first semiconductor block. The insulation barrier layer has a first through hole for one of the first source electrode and the first drain electrode contacting the first semiconductor block.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: August 27, 2019
    Assignee: Chunghwa Picture Tubes, LTD.
    Inventors: Chin-Hai Huang, Ya-Ju Lu, Shang-Jung Yang, Yen-Yu Huang
  • Patent number: 10379024
    Abstract: A method for determining a distribution of events, a method for determining a distribution of particle sizes in a sample of air, and an apparatus for performing the same are provided. The method includes obtaining a measured ensemble property distribution function for one or more events, generating one or more theoretical ensemble property distribution functions based on Poisson statistics using one or more model parameters, and determining an event parameter property distribution function by fitting one or more of the theoretical ensemble property distribution functions to the measured ensemble property distribution function using a forward inversion algorithm.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: August 13, 2019
    Assignee: University Corporation for Atmospheric Research
    Inventor: Matthew Hayman
  • Patent number: 10381306
    Abstract: A semiconductor memory device and a manufacturing method thereof are provided in the present invention. An under-cut structure is formed at an edge of a bit line contact opening in the process of forming the bit line contact opening for avoiding short problems caused by alignment shifting, and the process window of the process of forming the bit line contact opening may be improved accordingly.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: August 13, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Shih-Fang Tzou, Fu-Che Lee, Chien-Cheng Tsai, Feng-Ming Huang
  • Patent number: 10381336
    Abstract: Proximity coupling interconnect packaging systems and methods. A semiconductor package assembly comprises a substrate, a first semiconductor die disposed adjacent the substrate, and a second semiconductor die stacked over the first semiconductor die. There is at least one proximity coupling interconnect between the first semiconductor die and the second semiconductor die, the proximity coupling interconnect comprising a first conductive pad on the first coupling face on the first semiconductor die and a second conductive pad on a second coupling face of the second semiconductor die, the second conductive pad spaced apart from the first conductive pad by a gap distance and aligned with the first conductive pad. An electrical connector is positioned laterally apart from the proximity coupling interconnect and extends between the second semiconductor die and the substrate, the position of the electrical connector defining the alignment of the first conductive pad and the second conductive pad.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: August 13, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Rich Fogal, Owen R. Fay
  • Patent number: 10373965
    Abstract: An anti-fuse device includes: a well region disposed in a semiconductor substrate; a gate electrode disposed on a gate insulating film on the semiconductor substrate; and a first well bias tap region disposed below the gate insulating film and the gate electrode in the well region, wherein the well bias tap region is doped with dopants of a same conductivity type as the well region.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: August 6, 2019
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Young Chul Seo, Duk Ju Jeong
  • Patent number: 10374016
    Abstract: An organic photoelectronic device includes a first electrode and a second electrode facing each other and a light-absorption layer between the first electrode and the second electrode and including a first region closest to the first electrode, the first region having a first composition ratio (p1/n1) of a p-type semiconductor relative to an n-type semiconductor, a second region closest to the second electrode, the second region having a second composition ratio (p2/n2) of the p-type semiconductor relative to the n-type semiconductor, and a third region between the first region and the second region in a thickness direction, the third region having a third composition ratio (p3/n3) of the p-type semiconductor relative to the n-type semiconductor that is greater or less than the first composition ratio (p1/n1) and the second composition ratio (p2/n2).
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: August 6, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Gae Hwang Lee, Sung Young Yun, Yong Wan Jin
  • Patent number: 10373947
    Abstract: A bidirectional transient voltage suppressor (TVS) circuit for data pins of electronic devices includes two sets of steering diodes and a diode triggered clamp device in some embodiment. In other embodiments, a bidirectional transient voltage suppressor (TVS) circuit for data pins of electronic devices includes two sets of steering diodes with a clamp device merged with a steering diode in each set. The TVS circuit is constructed to realize low capacitance at the protected nodes and improved clamping voltage for robust protection against surge evens. In some embodiments, the TVS circuit realizes low capacitance at the protected nodes by fully or almost completely depleting the P-N junction connected to the protected nodes in the operating voltage range. In this manner, the TVS circuit does not present undesirable parasitic capacitance to the data pins being protected, especially when the data pins are applied in high speed applications.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: August 6, 2019
    Assignee: Alpha and Omega Semiconductor (Cayman) Ltd.
    Inventors: Shekar Mallikarjunaswamy, Ning Shi