Patents Examined by Mohammed Shamsuzzaman
  • Patent number: 11718904
    Abstract: A mask arrangement for masking a substrate in a processing chamber is provided. The mask arrangement includes a mask frame having one or more frame elements and is configured to support a mask device, wherein the mask device is connectable to the mask frame; and at least one actuator connectable to at least one frame element of the one or more frame elements, wherein the at least one actuator is configured to apply a force to the at least one frame element.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: August 8, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Stefan Bangert, Tommaso Vercesi, Daniele Gislon, Oliver Heimel, Andreas Lopp, Dieter Haas
  • Patent number: 11721743
    Abstract: A method of fabricating a high electron mobility transistor is disclosed. The method comprises using an ion implantation process to amorphize a portion of the barrier layer to a specific depth. The etch rate of this amorphized portion is much faster than that of the rest of the barrier layer. In this way, the depth of the recessed regions into which the source and drain contacts are disposed is more tightly controlled. Further, the etching process may be a wet or dry etch process. The roughness of the recessed region may also be improved using this approach.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: August 8, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Qintao Zhang, Wei Zou, Samphy Hong
  • Patent number: 11721640
    Abstract: An integrated circuit chip includes an SOI substrate having a structure in which a bulk substrate, a buried insulating film, and a semiconductor body layer are sequentially stacked, a conductive ion implantation region formed at a position adjacent to the buried insulating film in the bulk substrate, an integrated circuit portion formed on an active surface of the semiconductor body layer, and a penetrating electrode portion arranged at a position spaced apart from the integrated circuit portion in a horizontal direction, the penetrating electrode portion penetrating the semiconductor body layer and the buried insulating layer in a vertical direction, and the penetrating electrode portion connected to the conductive ion implantation region. An integrated circuit package and a display device include the integrated circuit chip.
    Type: Grant
    Filed: December 7, 2021
    Date of Patent: August 8, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-gu Kang, Young-mok Kim, Woon-bae Kim, Dae-cheol Seong, Yune-seok Chung
  • Patent number: 11715651
    Abstract: A substrate treatment apparatus includes a substrate support unit, a chemical supply unit supplying a chemical solution onto an upper surface of a substrate supported on the substrate support unit, a laser irradiation unit applying a laser pulse to the substrate to heat the substrate, and a controller controlling the laser irradiation unit to emit the laser pulse such that the substrate is repeatedly heated and cooled to maintain a preset temperature.
    Type: Grant
    Filed: October 24, 2020
    Date of Patent: August 1, 2023
    Assignee: SEMES CO., LTD.
    Inventors: Young Dae Chung, Won Geun Kim, Jee Young Lee, Ji Hoon Jeong, Tae Shin Kim, Jung Suk Goh, Cheng Bin Cui, Ye Rim Yeon
  • Patent number: 11711916
    Abstract: A method of forming a semiconductor memory device includes the following steps. First of all, a substrate is provided, and a plurality of gates is formed in the substrate, along a first direction. Next, a semiconductor layer is formed on the substrate, covering the gates, and a plug is then in the semiconductor layer, between two of the gates. Then, a deposition process is performed to from a stacked structure on the semiconductor layer. Finally, the stacked structure is patterned to form a plurality of bit lines, with one of the bit lines directly in contact with the plug.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: July 25, 2023
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Yi-Wei Chen, Hsu-Yang Wang, Chun-Chieh Chiu, Shih-Fang Tzou
  • Patent number: 11710741
    Abstract: Semiconductor devices are provided. The semiconductor devices may include a first wire pattern extending in a first direction on a substrate and a second wire pattern on the first wire pattern. The second wire pattern may be spaced apart from the first wire pattern and extends in the first direction. The semiconductor devices may also include a first gate structure at least partially surrounding the first wire pattern and the second wire pattern, a second gate structure spaced apart from the first gate structure in the first direction, a first source/drain region between the first gate structure and the second gate structure, a first spacer between a bottom surface of the first source/drain region and the substrate, a first source/drain contact on the first source/drain region, and a second spacer between the first source/drain contact and the first gate structure.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: July 25, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang Woo Noh, Myung Gil Kang, Geum Jong Bae, Dong Il Bae, Jung Gil Yang, Sang Hoon Lee
  • Patent number: 11710649
    Abstract: An apparatus includes a first and second stages. The first and second stages respectively hold a first and second substrates. The second stage being opposed to the first stage. A stress application portion applies a stress to the first substrate based on a first magnification value. A calculator calculates the first magnification value based on a flatness of the first substrate and a first equation. The first equation represents a relation between flatness of a third substrate, a second magnification value, and an amount of pattern misalignment between the third substrate and a fourth substrate bonded to the third substrate. A controller controls the stress application portion to apply a stress to the first substrate on the first stage based on the first magnification value while the first and second substrates are bonded to each other.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: July 25, 2023
    Assignee: Kioxia Corporation
    Inventor: Yoshio Mizuta
  • Patent number: 11701739
    Abstract: A method for separating integrated circuit dies from a wafer includes making at least two cutting passes with a laser along a first die street of an integrated circuit die, the first die street extending along a first axis on the wafer. The method also includes making at least two cutting passes with the laser along a second die street of the integrated circuit die, the second die street extending along a second axis on the wafer that is generally perpendicular to the first axis. In one process, three cutting passes are made with the laser alternatingly along the first and second die streets to separate the integrated die circuit along the first and second axes. In another process, two cutting passes are made with the laser along the first die street in opposite directions, and two cutting passes are then made with the laser along the second die street in opposite directions.
    Type: Grant
    Filed: April 2, 2020
    Date of Patent: July 18, 2023
    Assignee: Skyworks Solutions, Inc.
    Inventors: Juan Arturo Jerez, Miguel Camargo Soto, Luis Enrique Velazquez Cardenas
  • Patent number: 11705440
    Abstract: A micro LED display panel includes a driving substrate and a plurality of micro light emitting diodes (LEDs). The driving substrate has a plurality of pixel regions. Each of the pixel regions includes a plurality of sub-pixel regions. The micro LEDs are located on the driving substrate. At least one of the sub-pixel regions is provided with two micro LEDs of the micro LEDs electrically connected in series, and a dominant wavelength of the two micro LEDs is within a wavelength range of a specific color light. In a repaired sub-pixel region of the sub-pixel regions, only one of the two micro LEDs emits light. In a normal sub-pixel region of the sub-pixel regions, both of the two micro LEDs emit light.
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: July 18, 2023
    Assignee: PlayNitride Inc.
    Inventors: Kuan-Yung Liao, Ching-Liang Lin, Yun-Li Li, Yu-Chu Li
  • Patent number: 11699602
    Abstract: Exemplary substrate support assemblies may include a platen characterized by a first surface configured to support a semiconductor substrate. The assemblies may include a first stem section coupled with a second surface of the platen opposite the first surface of the platen. The assemblies may include a second stem section coupled with the first stem section. The second stem section may include a housing and a rod holder disposed within the housing. The second stem section may include a connector seated within the rod holder at a first end of the connector. The second stem section may include a heater rod disposed within the first end of the connector and a heater extension rod coupled with the connector at a second end of the connector. The second stem section may include an RF rod and an RF strap coupling the RF rod with an RF extension rod.
    Type: Grant
    Filed: July 7, 2020
    Date of Patent: July 11, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Jian Li, Edward P. Hammond, Viren Kalsekar, Vidyadharan Srinivasa Murthy Bangalore, Juan Carlos Rocha-Alvarez
  • Patent number: 11688616
    Abstract: A method for determining whether to modify a manufacturing process recipe is provided. A substrate to be processed at a manufacturing system according to the first process recipe is identified. An instruction to transfer the substrate to a substrate measurement subsystem to obtain a first set of measurements for the substrate is generated. The first set of measurements for the substrate is received from the substrate measurement subsystem. An instruction to transfer the substrate from the substrate measurement subsystem to a processing chamber is generated. A second set of measurements for the substrate is received from one or more sensors of the processing chamber. A first mapping between the first set of measurements and the second set of measurements for the substrate is generated. The first set of measurements mapped to the second set of measurements for the substrate is stored.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: June 27, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Upendra V. Ummethala, Blake Erickson, Prashanth Kumar, Michael Kutney, Steven Trey Tindel, Zhaozhao Zhu
  • Patent number: 11680320
    Abstract: A ruthenium film forming method includes: causing chlorine to be adsorbed to an upper portion of a recess at a higher density than to a lower portion of the recess by supplying a chlorine-containing gas to a substrate including an insulating film and having the recess; and forming a ruthenium film in the recess by supplying a Ru-containing precursor to the recess to which the chlorine is adsorbed.
    Type: Grant
    Filed: July 7, 2020
    Date of Patent: June 20, 2023
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Tadahiro Ishizaka
  • Patent number: 11675339
    Abstract: Systems and methods are described to improve efficiency in the manufacturing of a product for a manufacturer. The system includes a manufacturing route. The manufacturing route specifies at least two dimensions, where a first dimension of the at least two dimensions is a client machine and a second dimension of the at least two dimensions is a process associated with the client machine. A data stream is responsive to the plurality of dimensions. A database is configured to receive the data stream. A processor is configured to provide data from the data stream that indicates a symptom of a problem which can occur within the manufacturing route.
    Type: Grant
    Filed: January 25, 2021
    Date of Patent: June 13, 2023
    Assignee: SCHEMAPORT, LLC
    Inventor: Steven Clair Hugh
  • Patent number: 11672115
    Abstract: Aspects of the disclosure provide a semiconductor device including a string of transistors stacked in a vertical direction over a substrate of the semiconductor device having a channel structure extending in the vertical direction. The string of transistors includes a first substring arranged along a first portion of the channel structure, a second substring arranged along a second portion of the channel structure, and a third substring arranged along a third portion of the channel structure. The second substring is between the first and the third substrings. Gate structures of transistors in the first substring are separated by first insulating layers. Gate structures of transistors in the second substring are separated by second insulating layers. Gate structures of transistors in the third substring are separated by third insulating layers. A volumetric mass density of the second insulating layers is lower than a volumetric mass density of the third insulating layers.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: June 6, 2023
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Qiguang Wang, Gonglian Wu
  • Patent number: 11664267
    Abstract: A substrate support assembly arranged in a chamber includes: a support plate including a first surface on which a substrate is seated; a driver configured to tilt the support plate such that the first surface is inclined with respect to a reference surface by a lower inclination angle; and a controller configured to control the driver such that the lower inclination angle is adjusted based on an upper inclination angle formed by the inclination of the gas supplier coupled to the upper surface of the chamber with respect to the reference surface.
    Type: Grant
    Filed: July 7, 2020
    Date of Patent: May 30, 2023
    Assignee: ASM IP Holding B.V.
    Inventors: JaeMin Roh, Julll Lee, GunYong Park
  • Patent number: 11664203
    Abstract: An electrostatic-chuck heater is a Johnsen-Rahbek electrostatic-chuck heater and is used in a process of forming a conductive film on a wafer. The electrostatic-chuck heater includes a disc-shaped ceramic base including an electrostatic electrode and a heating resistor, and a hollow shaft attached to a side of the ceramic base that is opposite a wafer-mounting surface. A protruding ring is provided on the wafer-mounting surface and having an outside diameter smaller than a diameter of the wafer. A through-hole extends in a peripheral wall of the hollow shaft from a lower end through to an area of the wafer-mounting surface that is on an inner side with respect to the protruding ring. The through-hole allows gas to be supplied from the lower end of the hollow shaft into a below-wafer space enclosed by the wafer-mounting surface, the protruding ring, and the wafer mounted on the wafer-mounting surface.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: May 30, 2023
    Assignee: NGK INSULATORS, LTD.
    Inventors: Yutaka Unno, Reo Watanabe
  • Patent number: 11664212
    Abstract: The inventive concept provides a substrate treating apparatus. In an embodiment, the substrate treating apparatus includes a housing having a treatment space for treating a substrate in an interior thereof, a support unit that supports the substrate in the treatment space, a nozzle that supplies a liquid to the substrate positioned on the support unit, a liquid supply unit that supplies the liquid to the nozzle, and a controller that controls the liquid unit, the liquid supply unit includes a tank having an interior space for storing the liquid, and a first circulation line that circulates the liquid stored in the interior space and in which a first heater is installed, and the controller controls the first heater such that the first heater heats the liquid to a first temperature, at which particles in the interior of the liquid are not eluted.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: May 30, 2023
    Assignee: SEMES CO., LTD.
    Inventors: Yong Hoon Hong, Sul Lee, Myung A Jeon, Moonsik Choi, Young Su Kim
  • Patent number: 11658048
    Abstract: An apparatus and a method for performing liquid treatment for a substrate are provided. The apparatus for treating the substrate includes a treating container having a treatment space inside the treating container, a substrate support unit to support a substrate in the treatment space, and a liquid supply unit to supply treatment liquid to the substrate supported by the substrate support unit. The liquid supply unit includes a nozzle, a supply line to supply the treatment liquid to the nozzle and having a first valve mounted in the supply line, and a discharge line branching from a branch point which is a point downstream of the first valve in the supply line to discharge the treatment liquid from the supply line, and having a second valve mounted in the discharge line. A valve is absent in an area between the branch point and the nozzle, in the supply line.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: May 23, 2023
    Assignee: Semes Co., Ltd.
    Inventors: Seong Soo Lee, Buyoung Jung, Gi Hun Choi, Myung A Jeon, Soo Young Park
  • Patent number: 11643597
    Abstract: Disclosed are a semiconductor nanocrystal particle including indium (In), zinc (Zn), and phosphorus (P), wherein a mole ratio of the zinc relative to the indium is greater than or equal to about 25:1, and the semiconductor nanocrystal particle includes a core including a first semiconductor material including indium, zinc, and phosphorus and a shell disposed on the core and including a second semiconductor material including zinc and sulfur, a method of producing the same, and an electronic device including the same. The semiconductor nanocrystal particle emits blue light having a maximum peak emission at a wavelength of less than or equal to about 470 nanometers.
    Type: Grant
    Filed: March 17, 2021
    Date of Patent: May 9, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tae Hyung Kim, Hyun A Kang, Eun Joo Jang, Dae Young Chung
  • Patent number: 11641752
    Abstract: An organic photoelectronic device includes a first electrode and a second electrode facing each other and a light-absorption layer between the first electrode and the second electrode and including a first region closest to the first electrode, the first region having a first composition ratio (p1/n1) of a p-type semiconductor relative to an n-type semiconductor, a second region closest to the second electrode, the second region having a second composition ratio (p2/n2) of the p-type semiconductor relative to the n-type semiconductor, and a third region between the first region and the second region in a thickness direction, the third region having a third composition ratio (p3/n3) of the p-type semiconductor relative to the n-type semiconductor that is greater or less than the first composition ratio (p1/n1) and the second composition ratio (p2/n2).
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: May 2, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Gae Hwang Lee, Sung Young Yun, Yong Wan Jin