Patents Examined by Mohammed Shamsuzzaman
  • Patent number: 11810806
    Abstract: A tray module capable of discharging static electricity to safely transfer display device members (e.g., components) includes: a tray configured to accommodate at least two members of a display device, at least two conductive protection films alternatingly stacked with the members of the display device, and a conductive pattern on the tray to provide a discharge path with the conductive protection films to ground.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: November 7, 2023
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jahuem Koo, Sungjin Joo, Nampyo Hong
  • Patent number: 11810914
    Abstract: Provided is a semiconductor device having transistor and diode sections. The semiconductor device comprises: a gate metal layer provided above the upper surface of a semiconductor substrate; an emitter electrode provided above the upper surface of the semiconductor substrate; a first conductivity-type emitter region provided on the semiconductor substrate upper surface side in the transistor section; a gate trench section, which is provided on the semiconductor substrate upper surface side in the transistor section, is electrically connected to the gate metal layer, and is in contact with the emitter region; an emitter trench section, which is provided on the semiconductor substrate upper surface side in the diode section, and is electrically connected to the emitter electrode; and a dummy trench section, which is provided on the semiconductor substrate upper surface side, is electrically connected to the gate metal layer, and is not in contact with the emitter region.
    Type: Grant
    Filed: January 17, 2022
    Date of Patent: November 7, 2023
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Tomoyuki Obata, Soichi Yoshida, Tetsutaro Imagawa, Seiji Momota
  • Patent number: 11804395
    Abstract: A substrate processing method includes: carrying out a substrate from a substrate transfer container by a substrate transfer device; placing the substrate in a first position of a substrate holder; moving the substrate holder into a reaction container and processing the substrate in the reaction chamber; obtaining a film thickness measurement result of the substrate processed in the reaction container; creating a model from the film thickness measurement result; determining a second position where the substrate is placed in the substrate holder and a transfer position setting value obtained from the model; adjusting the first position of the substrate to the second position; calculating an eccentricity state of the substrate from a newly obtained film thickness measurement result; calculating an optimization such that the eccentricity state is minimized; and determining a third position to which a new substrate is placed from the transfer position setting value.
    Type: Grant
    Filed: March 2, 2022
    Date of Patent: October 31, 2023
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Youngtai Kang, Yuichi Takenaga
  • Patent number: 11791192
    Abstract: A workpiece holder includes a chuck body and a seal ring. The chuck body includes a receiving surface configured to receive a workpiece and at least one vacuum port configured to apply a vacuum seal. The seal ring surrounds a side surface of the chuck body. A top surface of the seal ring is higher than the receiving surface of the chuck body, and the workpiece leans against the seal ring when the vacuum seal is applied between the workpiece and the chuck body.
    Type: Grant
    Filed: September 3, 2020
    Date of Patent: October 17, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Shiuan Wong, Chih-Chiang Tsao, Chao-Wei Chiu, Hao-Jan Pei, Wei-Yu Chen, Hsiu-Jen Lin, Ching-Hua Hsieh, Chia-Shen Cheng
  • Patent number: 11784063
    Abstract: The present invention provides a packaging method and a packaging device for selectively encapsulating a packaging structure. The method includes: providing a substrate; mounting components on the substrate, the components including a component that needs to be encapsulated and a component that does not need to be encapsulated; forming a protective structure in an area of the component that does not need to be encapsulated so as to form a protective area for isolating the component that does not need to be encapsulated and an encapsulating area located outside the protective area; filling the encapsulating area with an injection molding material; and removing the protective structure. According to the present invention, any part of the packaging structure may be selectively encapsulated by self-adjustment as required. The operation is simple, and the process flow is simplified.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: October 10, 2023
    Assignee: JIANGSU CHANGJIANG ELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Jie Wang
  • Patent number: 11785783
    Abstract: Disclosed are a spin logic device based on spin-charge conversion and a spin logic array using the same. A reconfigurable spin logic array according to an exemplary embodiment of the present invention may include: an input terminal receiving at least three current signals; a plurality of wires transmitting the current signal in connection with the input terminal and including a horizontal wire and a vertical wire which cross each other; a first gate array in which at least one first majority gate connected to the input terminal through the wires and implemented based on the spin logic device is arranged; and a second gate array in which at least one second majority gate connected to the first gate array through the wires and implemented based on the spin logic device is arranged.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: October 10, 2023
    Assignees: INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY, INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY ERICA CAMPUS
    Inventors: Jongill Hong, Saeroonter Oh
  • Patent number: 11784256
    Abstract: A semiconductor device may include first and second channel patterns on a substrate, first and second source/drain patterns in contact respectively with the first and second channel patterns, and first and second gate electrodes respectively overlapping the first and second channel patterns. The first gate electrode may include a first segment between first and second semiconductor patterns of the first channel pattern. The first segment may include a first convex portion protruding toward the first source/drain pattern. The second gate electrode may include a second segment between third and fourth semiconductor patterns of the second channel pattern. The second segment may include a concave portion recessed toward a center of the second segment.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: October 10, 2023
    Inventors: Soojin Jeong, Dong Il Bae, Geumjong Bae, Seungmin Song, Junggil Yang
  • Patent number: 11778880
    Abstract: A display substrate and a fabrication method thereof, a display panel and a display device are provided. The display substrate includes pixels. Each of the pixels includes sub-pixels that emit light of different colors, each of the sub-pixels includes a light emitting element, and at least one of the sub-pixels further includes a color filter. The color filter of the at least one of the sub-pixels covers a portion of a light emitting region of the light emitting element of the at least one of the sub-pixels, and a color of the color filter of the at least one of the sub-pixels is the same as a color of light emitted by the light emitting element of the at least one of the sub-pixels.
    Type: Grant
    Filed: May 4, 2021
    Date of Patent: October 3, 2023
    Assignees: Hefei Xinsheng Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Zhidong Yuan, Pan Xu, Can Yuan, Meng Li
  • Patent number: 11776808
    Abstract: A method for planarizing a substrate includes: receiving a substrate having microfabricated structures that differ in height across the working surface of the substrate that define a non-planar topography, depositing a first layer that includes a solubility-shifting agent on the working surface of the substrate by spin-on deposition in a non-planar fashion, exposing the first layer to a first pattern of actinic radiation based on the topography, developing the first layer using a predetermined solvent, and depositing a second layer over the working surface of the substrate that has a greater planarity as compared to the first layer prior to developing the first layer. The first pattern of radiation changes a solubility of the first layer such that upper regions of the non-planar topography of the first layer are soluble to the predetermined solvent.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: October 3, 2023
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Anthony R. Schepis, Anton deVilliers
  • Patent number: 11769678
    Abstract: A lithography includes a storage tank that stores process chemical fluid, an anti-collision frame, and an integrated sensor assembly. The storage tank includes a dispensing port positioned at a lowest part of the storage tank in a gravity direction. The anti-collision frame is coupled to the storage tank. An integrated sensor assembly is disposed on at least one of the anti-collision frame and the storage tank to measure a variation in fluid quality in response to fluid quality measurement of fluid.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: September 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tzu-Yang Lin, Cheng-Han Wu, Chen-Yu Liu, Kuo-Shu Tseng, Shang-Sheng Li, Chen Yi Hsu, Yu-Cheng Chang
  • Patent number: 11769727
    Abstract: A semiconductor memory device and a manufacturing method thereof are provided in the present invention. An under-cut structure is formed at an edge of a bit line contact opening in the process of forming the bit line contact opening for avoiding short problems caused by alignment shifting, and the process window of the process of forming the bit line contact opening may be improved accordingly.
    Type: Grant
    Filed: September 6, 2021
    Date of Patent: September 26, 2023
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Shih-Fang Tzou, Fu-Che Lee, Chien-Cheng Tsai, Feng-Ming Huang
  • Patent number: 11762125
    Abstract: A method for determining national crop yields during the growing season is provided. In an embodiment, a server computer system receives agricultural data records for a particular year that represent covariate data values related to plants at a specific geo-location at a specific time. The system aggregates the records to create geo-specific time series for a geo-location over a specified time. The system creates aggregated time series from a subset of the geo-specific time series. The system selects a representative feature from the aggregated time series and creates a covariate matrix for each specific geographic area in computer memory. The system determines a specific crop yield for a specific year using linear regression to calculate the specific crop yield from the covariate matrix. The system determines a forecasted crop yield for the specific year using a sum of the specific crop yields for the specific year, as adjusted.
    Type: Grant
    Filed: March 11, 2022
    Date of Patent: September 19, 2023
    Assignee: CLIMATE LLC
    Inventors: Lijuan Xu, Ying Xu
  • Patent number: 11749569
    Abstract: Various embodiments of the present disclosure are directed towards a method for non-destructive inspection of cell etch redeposition. In some embodiments of the method, a grayscale image of a plurality of cells on a wafer is captured. The grayscale image provides a top down view of the cells and, in some embodiments, is captured in situ after etching to form the cells. The cells are identified in the grayscale image to determine non-region of interest (non-ROI) pixels corresponding to the cells. The non-ROI pixels are subtracted from the grayscale image to determine ROI pixels. The ROI pixels are remaining pixels after the subtracting and correspond to material on sidewalls of, and in recesses between, the cells. An amount of etch redeposition on the sidewalls and in the recesses is then scored based on gray levels of the ROI pixels. Further, the wafer is processed based on the score.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: September 5, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: I-Che Lee, Huai-Ying Huang, Yi Chien Lee
  • Patent number: 11749542
    Abstract: Embodiments of the present disclosure relate to apparatus, systems and methods for substrate processing. A detachable substrate support is disposed within a processing volume of a processing chamber and the substrate support includes a substrate interfacing surface and a back surface. The pedestal hub has a supporting surface removably coupled to the substrate support. A hub volume of the pedestal hub includes temperature measuring assembly disposed therein positioned to receive electromagnetic energy emitted from the back surface of the substrate support. The temperature measuring assembly measures an intensity of the electromagnetic energy entering the assembly and generates intensity signals. An apparent temperature of the substrate is determined based on the intensity signals.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: September 5, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Bhaskar Prasad, Kirankumar Neelasandra Savandaiah, Thomas Brezoczky, Srinivasa Rao Yedla
  • Patent number: 11749146
    Abstract: A chip-on-film package includes a base substrate on which a first pad region, a second pad region, and a third region located between the first pad region and the second pad region are defined, a dummy pad disposed on the first pad region, input pads disposed on the first pad region, output pads disposed on the second region, a first detection line disposed on the base substrate, and a second detection line disposed on the base substrate. The first detection line is connected to a first input pad and a second input pad via the second pad region to form a first loop between the first input pad and the second input pad, and the second detection line is connected to the dummy pad and the first detection line via the third region to form a second loop between the dummy pad and the first input pad.
    Type: Grant
    Filed: July 5, 2021
    Date of Patent: September 5, 2023
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Hee-Kwon Lee, Seungkyun Hong
  • Patent number: 11751382
    Abstract: Methods of forming a DRAM bit line to improve line edge roughness (LER) and lower resistance are described. The method comprises implanting an inert species into a bit line metal layer having a first grain size on a substrate to form an amorphized bit line metal layer having a second grain size smaller than the first grain size. A film stack is then deposited on the amorphized bit line metal layer. The film stack and amorphized bit line metal layer are etched to form a patterned film stack on the substrate. The patterned film stack on the substrate is thermally annealed.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: September 5, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Lequn Liu, Priyadarshi Panda, Jonathan C. Shaw
  • Patent number: 11737356
    Abstract: An organic electroluminescence device includes a first electrode, a second electrode facing the first electrode, and a plurality of organic layers between the first electrode and the second electrode, wherein at least one of the plurality of organic layers includes an amine compound, the amine compound includes a central nitrogen atom, a carbazole group substituted to the central nitrogen atom, and a dibenzoselenophene group substituted to the central nitrogen atom, and a nitrogen atom of the carbazole group is substituted with a substituted or unsubstituted aryl group or a substituted or unsubstituted heteroaryl group. The organic electroluminescence device thereby has high efficiency and long-life.
    Type: Grant
    Filed: August 19, 2020
    Date of Patent: August 22, 2023
    Assignee: Samsung Display Co., Ltd.
    Inventors: Dongjun Kim, Minji Kim, Eunjae Jeong, Sohee Jo, Sanghyun Han
  • Patent number: 11728447
    Abstract: In a semiconductor device, a first package is provided with a first substrate under which a semiconductor chip configured to output a signal and a first wiring electrically connected to the semiconductor chip are arranged. A second package is provided with a second substrate above which a processing circuit configured to process the output signal, a second wiring electrically connected to the processing circuit, and an encapsulant configured to seal the processing circuit are arranged, the semiconductor chip and the encapsulant being arranged to face each other in a non-contact manner. A connection portion electrically connects the first wiring and the second wiring.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: August 15, 2023
    Assignee: SONY GROUP CORPORATION
    Inventor: Makoto Murai
  • Patent number: 11718904
    Abstract: A mask arrangement for masking a substrate in a processing chamber is provided. The mask arrangement includes a mask frame having one or more frame elements and is configured to support a mask device, wherein the mask device is connectable to the mask frame; and at least one actuator connectable to at least one frame element of the one or more frame elements, wherein the at least one actuator is configured to apply a force to the at least one frame element.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: August 8, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Stefan Bangert, Tommaso Vercesi, Daniele Gislon, Oliver Heimel, Andreas Lopp, Dieter Haas
  • Patent number: 11721743
    Abstract: A method of fabricating a high electron mobility transistor is disclosed. The method comprises using an ion implantation process to amorphize a portion of the barrier layer to a specific depth. The etch rate of this amorphized portion is much faster than that of the rest of the barrier layer. In this way, the depth of the recessed regions into which the source and drain contacts are disposed is more tightly controlled. Further, the etching process may be a wet or dry etch process. The roughness of the recessed region may also be improved using this approach.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: August 8, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Qintao Zhang, Wei Zou, Samphy Hong