Abstract: A method of planarizing a substrate comprises dispensing formable material onto a substrate, contacting, at a planarizing station at a first location, a superstrate held by a superstrate chuck with the formable material on the substrate, thereby forming a multilayer structure including the superstrate, a film of the formable material, and the substrate, releasing the superstrate from the superstrate chuck, moving the multilayer structure from the first location to a curing station located at a second location away from the first location, the curing station including an array of light-emitting diodes, and curing the film of the multilayer structure by exposing the film to light emitted from the array of light-emitting diodes.

Abstract: A light-emitting element containing a fluorescent material and having high emission efficiency is provided. The light-emitting element contains the fluorescent material and a host material. The host material contains a first organic compound and a second organic compound. The first organic compound and the second organic compound can form an exciplex. The minimum value of a distance between centroids of the fluorescent material and at least one of the first organic compound and the second organic compound is 0.7 nm or more and 5 nm or less.

Abstract: A plasma discharge detection system detects undesirable plasma discharge events within a semiconductor process chamber. The plasma discharge detection system includes one or more cameras positioned around the semiconductor process chamber. The cameras capture images from within the semiconductor process chamber. The plasma discharge detection system includes a control system that receives the images from the cameras. The control system analyzes the images and detects plasma discharge within the semiconductor process chamber based on the images. The control system can adjust a semiconductor process in real time responsive to detecting the plasma discharge.

Abstract: A light-emitting element containing a fluorescent material and having high emission efficiency is provided. The light-emitting element contains the fluorescent material and a host material. The host material contains a first organic compound and a second organic compound. The first organic compound and the second organic compound can form an exciplex. The proportion of a delayed fluorescence component in light emitted from the exciplex is higher than or equal to 5%, and the delayed fluorescence component contains a delayed fluorescence component whose fluorescence lifetime is 10 ns or longer and 50 ?s or shorter.

Abstract: A display device including a display area and a non-display area, the display device including a plurality of data wires disposed in the display area and in the non-display area, a plurality of connecting wires disposed in the display area and connected to the data wires, a plurality of dummy patterns disposed in the display area in the same layer as the connecting wires, and shielding patterns disposed on the connecting wires. First gaps are defined between the connecting wires and the dummy patterns, and the shielding patterns overlap with the first gaps.

Abstract: A semiconductor package includes a base structure having a base pad, a first semiconductor chip on the base structure, and having a first connection pad bonded to the base pad, a first bonding structure including an base insulation layer of a base structure and a first lower insulation layer of the first semiconductor chip bonded to the base insulation layer, a second semiconductor chip on the first semiconductor chip, and having a second connection pad connected to the first through-electrode, and a second bonding structure including a first upper insulation layer of the first semiconductor chip, and a second lower insulation layer of the second semiconductor chip bonded to the first upper insulation layer, and the first upper insulation layer has a dummy insulation portion extending onto the base structure around the first semiconductor chip.

Abstract: Exemplary substrate processing systems may include a body that defines processing and transfer regions. The systems may include a liner atop the body. The systems may include a faceplate atop the liner. The systems may include a support within the body. The support may be vertically translatable between process and transfer positions. The support may include a plate having a heater. The support may include a shaft coupled with the plate. The support may include a bowl about the shaft below the plate. The bowl may be in alignment with the liner. The support may include springs that push the bowl upward as the support translates to the process position. The support may include straps that couple the plate and bowl. The support may include a hard stop. The bowl may contact the liner in the process position and may be spaced apart from the liner in the transfer position.

Abstract: An object of the present invention is to provide a holding jig that is used for applying a liquid bath treatment to a planar workpiece, has good cleaning capabilities, and avoids intimate contact of the planar workpiece with a rear member of the holding jig so that the planar workpiece can be easily detached from the holding jig after cleaning. A holding jig is used for applying a liquid bath treatment to a planar workpiece. The holding jig comprises a rear member, and a front member that faces the rear member and has an opening portion. The planar workpiece is disposed between the rear member and the front member, and the rear member has a plurality of projections formed on the surface of the rear member facing the front member.

Abstract: Aspects of the disclosure provide a method to manufacture a semiconductor device. The method includes filling a sacrificial layer in a first via of a first stack. An initial top CD is larger than an initial bottom CD of the first via. A second stack is formed along a vertical direction over the first stack. A third stack is formed along the vertical direction over the second stack. The first stack, the second stack, and the third stack include alternating insulating layers and gate layers. The insulating layers of the second stack etch at a faster rate than the insulating layers of the third stack and the gate layers of the second stack etch at a faster rate than the gate layers of the third stack. A first via, a second via, and a third via are formed in the first stack, the second stack, and the third stack, respectively.

Abstract: A light-emitting unit (140) is formed over a first surface (102) of a substrate (100). A first terminal (112) and a second terminal (132) are formed on the first surface (102) of the substrate (100), and are electrically connected to the light-emitting unit (140). A sealing layer (200) is formed over the first surface (102) of the substrate (100), and seals the light-emitting unit (140). In addition, the sealing layer (200) does not cover the first terminal (112) and the second terminal (132). A cover layer (210) is formed over the sealing layer (200), and is formed of a material different from that of the cover layer (210). In at least a portion of a region located next to the first terminal (112) and a region located next to the second terminal (132), a portion of an end of the cover layer (210) protrudes from the sealing layer (200).

Abstract: A dual side cooling power module includes: a lower substrate including a recessed portion on at least one surface thereof, a semiconductor chip formed in the recessed portion, lead frames formed at both ends of the lower substrate, and an upper substrate formed on the semiconductor chip, a portion of the lead frames, and the lower substrate.

Abstract: The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The method of manufacturing a semiconductor structure includes: providing a base; forming a plurality of first trenches arranged in parallel at intervals and extending along a first direction, and an initial active region between two adjacent ones of the first trenches, wherein the initial active region includes a first initial source-drain region close to a bottom of the first trench, a second initial source-drain region away from the bottom of the first trench, and an initial channel region located between the first initial source-drain region and the second initial source-drain region; forming a protective dielectric layer, wherein the protective dielectric layer covers a sidewall of the second initial source-drain region and a sidewall of the initial channel region; thinning the first initial source-drain region.

Abstract: A method for operating a conveying system is provided. An overhead hoist transport (OHT) vehicle is provided, wherein the OHT vehicle includes a gripping member configured to grip and hold a carrier, and a receiver configured to receive a signal. The signal is transmitted to the receiver of the OHT vehicle. The OHT vehicle is moved toward the carrier, and the carrier is gripped by the gripping member of the OHT vehicle. A lifting force is determined based on a weight of a carrier, a number of workpieces in the carrier, or a vertical distance between the OHT vehicle and the carrier, and the lifting force is applied to the carrier.

Abstract: Methods, systems, and apparatus for conducting chucking operations are disclosed that use an adjusted chucking voltage if a process shift occurs. In one implementation, a method includes conducting a first processing operation on a substrate in a processing chamber. The first processing operation includes applying a chucking voltage to an electrostatic chuck (ESC) in the processing chamber while the substrate is supported on the ESC. The method includes determining that a process shift has occurred. The determining that the process shift has occurred includes one or more of: determining that a center of the substrate has moved by a post-processing shift relative to a pre-processing location of the center prior to the first processing operation, or determining that a defect count of a backside surface of the substrate exceeds a defect threshold. The method includes determining an adjusted chucking voltage based on the occurrence of the process shift.

Abstract: Described herein is a technique capable of improving the controllability of a thickness of a film formed on a large surface area substrate having a surface area greater than a surface area of a bare substrate and improving the thickness uniformity between films formed on a plurality of large surface area substrates accommodated in a substrate loading region by reducing the influence of the surface area of the large surface area substrate and the number of the large surface area substrates due to a loading effect even when the plurality of large surface area substrates are batch-processed using a batch type processing furnace.

Abstract: A control device for a substrate processing apparatus stores a plurality of records each including a recipe for a substrate etching processing and a control value for a control target, the control value being an actual output value for the control target in the substrate etching processing; acquires a recipe at a start of the substrate etching processing when an abnormality occurs in the temperature sensor or in the concentration sensor; reads a record from among the plurality of records having a recipe identical to the recipe acquired at the start of the substrate etching processing; and executes the substrate etching processing based on the control value of the record read by the processor.

Abstract: A semiconductor device includes a first active region, a second active region, a first gate line disposed to overlap the first and second active regions, a second gate line disposed to overlap the first and second active regions, a first metal line electrically connecting the first and second gate lines and providing a first signal to both the first and second gate lines, a first contact structure electrically connected to part of the first active region between the first and second gate lines, a second contact structure electrically connected to part of the second active region between the first and second gate lines, and a second metal line electrically connected to the first and second contact structures and transmitting a second signal, wherein an overlapped region that is overlapped by the second metal line does not include a break region.

Abstract: In a semiconductor device, on a heat dissipation portion of a lead frame opposite to a mounting portion on which a semiconductor element is mounted, a thin molding portion having a thickness of about 0.02 mm to 0.3 mm is formed by a second molding resin which is a high-heat-dissipation resin. A scale-like portion on which scale-shaped projections are consecutively formed is provided over both sides across a resin boundary portion of the heat dissipation portion. The scale-like portion reaches abutting surfaces of an upper die and a lower die of a mold used in a molding process. Thus, the same void inhibition effect as with an air vent is obtained.

Abstract: A method can include obtaining characteristic data for a wafer. The characteristic data can correspond to the wafer in a processed state and can include a set of stress values of the wafer. The wafer can include a front side, a back side opposite the front side, and a set of regions. The set of stress values can include a first stress value corresponding to a first region. In the processed state, one or more front-side processes can be completed on the front side of the wafer. The method can include determining that the first stress value exceeds a stress threshold and generating a compensation map. The compensation map can identify one or more regions for forming one or more trenches. The method can include initiating, based on the compensation map, a formation of a first trench on the back side of the wafer in the first region.

Abstract: A light emitting device including a cell area, a peripheral area surrounding the cell area, a light source disposed in the cell area and including at least one light emitting layer, a first light shielding layer disposed in the cell area and the peripheral area, a portion of the first light shielding layer overlapping with the light source, and a rough structure disposed in the cell area and overlapping with the light source.