Patents Examined by Moin M Rahman
  • Patent number: 10937879
    Abstract: A semiconductor device includes a semiconductor substrate, a control gate, a select gate, a charge trapping structure, and a dielectric structure. The semiconductor substrate has a drain region, a source region, and a channel region between the drain region and the source region. The control gate is over the channel region of the semiconductor substrate. The select gate is over the channel region of the semiconductor substrate and separated from the control gate. The charge trapping structure is between the control gate and the semiconductor substrate. The dielectric structure is between the select gate and the semiconductor substrate. The dielectric structure has a first part and a second part, the first part is between the charge trapping structure and the second part, and the second part is thicker than the first part.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: March 2, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Han Lin, Wei-Cheng Wu, Te-Hsin Chiu
  • Patent number: 10930769
    Abstract: In a method of manufacturing a negative capacitance structure, a dielectric layer is formed over a substrate. A first metallic layer is formed over the dielectric layer. After the first metallic layer is formed, an annealing operation is performed, followed by a cooling operation. A second metallic layer is formed. After the cooling operation, the dielectric layer becomes a ferroelectric dielectric layer including an orthorhombic crystal phase.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: February 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Chieh Lu, Cheng-Yi Peng, Chien-Hsing Lee, Ling-Yen Yeh, Chih-Sheng Chang, Carlos H. Diaz
  • Patent number: 10923534
    Abstract: Provided is a rectifying element that prevents erroneous writing and an erroneous operation and that is substituted for a select transistor; a rewritable semiconductor device that uses a nonvolatile switch including the rectifying element and having excellent reliability, a small area, and low power consumption has a stacked structure of a first electrode 11, a first buffer layer 14, a rectifying layer 13, a second buffer layer 15, and a second electrode 12; and the rectifying layer 13 comprises a first silicon nitride layer 16 having a high nitrogen content (50 atm % or more) and second silicon nitride layers 17A and 17B having a lower nitrogen content than the first silicon nitride layer 16 (50 atm % or less), wherein the second silicon nitride layers 17A and 17B are in contact with the first and second buffer layers (14, 15), respectively, and the first silicon nitride layer 16 is sandwiched between the second silicon nitride layers 17A and 17B.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: February 16, 2021
    Assignee: NEC CORPORATION
    Inventors: Naoki Banno, Munehiro Tada, Noriyuki Iguchi
  • Patent number: 10923351
    Abstract: A coating method of coating a substrate with a chemical includes a solvent supplying step and a chemical supplying step. In the solvent supplying step, a solvent is supplied to the substrate. After the solvent supplying step, the chemical is supplied to the substrate in the chemical supplying step. The solvent supplying step includes a first step. The first step causes the substrate to rotate at a first rotation speed, causes a solvent nozzle to move between a central position above a center portion of the substrate and a peripheral position above a peripheral portion of the substrate, and causes the solvent nozzle to dispense the solvent.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: February 16, 2021
    Inventors: Shogo Yoshida, Hiroyuki Ogura, Ryuichi Yoshida
  • Patent number: 10923344
    Abstract: A method for forming a forming a semiconductor structure is disclosed. The method may include: forming a silicon oxide layer on a surface of a substrate, depositing a silicon germanium (Si1-xGex) seed layer directly on the silicon oxide layer, and depositing a germanium (Ge) layer directly on the silicon germanium (Si1-xGex) seed layer. Semiconductor structures including a germanium (Ge) layer deposited on silicon oxide utilizing an intermediate silicon germanium (Si1-xGex) seed layer are also disclosed.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: February 16, 2021
    Assignee: ASM IP Holding B.V.
    Inventors: David Kohen, Harald Benjamin Profijt, Andrew Kretzschmar
  • Patent number: 10910435
    Abstract: A method of forming an electrical device that includes forming an amorphous semiconductor material on a metal surface of a memory device, in which the memory device is vertically stacked atop a first transistor. The amorphous semiconductor material is annealed with a laser anneal having a nanosecond duration to convert the amorphous semiconductor material into a crystalline semiconductor material. A second transistor is formed from the semiconductor material. The second transistor vertically stacked on the memory device.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: February 2, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Alexander Reznicek, Bahman Hekmatshoartabari, Oleg Gluschenkov, Yasir Sulehria
  • Patent number: 10903623
    Abstract: The present disclosure provides a method and structure for producing large area gallium and nitrogen engineered substrate members configured for the epitaxial growth of layer structures suitable for the fabrication of high performance semiconductor devices. In a specific embodiment the engineered substrates are used to manufacture gallium and nitrogen containing devices based on an epitaxial transfer process wherein as-grown epitaxial layers are transferred from the engineered substrate to a carrier wafer for processing. In a preferred embodiment, the gallium and nitrogen containing devices are laser diode devices operating in the 390 nm to 425 nm range, the 425 nm to 485 nm range, the 485 nm to 550 nm range, or greater than 550 nm.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: January 26, 2021
    Assignee: Soraa Laser Diode, Inc.
    Inventors: Melvin McLaurin, James W. Raring
  • Patent number: 10892351
    Abstract: A semiconductor device includes a first semiconductor region of first conductivity type, a second semiconductor region of second conductivity type, a third semiconductor region of second conductivity type, a first electrode, a fourth semiconductor region of second conductivity type, a fifth semiconductor region of first conductivity type, a gate electrode, a sixth semiconductor region of second conductivity type, and second and third electrodes. The second and third semiconductor regions are formed below the first semiconductor region. A second conductivity type carrier concentration of the third semiconductor region is lower than that of the second semiconductor region. The gate electrode faces the fourth semiconductor region. The sixth semiconductor region is formed above the first semiconductor region and is located above the third semiconductor region.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: January 12, 2021
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Tomohiro Tamaki
  • Patent number: 10886430
    Abstract: A method of manufacturing a light-emitting device includes: arranging a plurality of light-emitting elements each having an upper surface; disposing a first reflective member between the plurality of light-emitting elements such that the upper surface of each of the plurality of light-emitting elements are exposed and such that lateral surfaces of the light-emitting elements are covered with the first reflective member; disposing a light-transmissive member over the upper surface of each of the plurality of light-emitting elements and the first reflective member; forming a plurality of grooves surrounding one or two or more light-emitting elements by removing a portion of the light-transmissive member and a portion of the first reflective member; disposing a second reflective member to fill the plurality of grooves; and cutting the second reflective member to perform singulation.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: January 5, 2021
    Assignee: NICHIA CORPORATION
    Inventor: Tomoki Takamatsu
  • Patent number: 10886362
    Abstract: A tri-layer dielectric stack is provided for a metal-insulator-metal capacitor (MIMCAP). Also, a metal-insulator-metal capacitor (MIMCAP) is provided having three or more electrodes. The tri-layer dielectric stack includes a first layer formed from a first metal oxide electrical insulator. The tri-layer dielectric stack further includes a second layer, disposed over the first layer, formed from ZrO2. The tri-layer dielectric stack also includes a third layer, disposed over the second layer, formed from a second metal oxide electrical insulator.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: January 5, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Eduard A. Cartier, Hemanth Jagannathan, Paul C. Jamison
  • Patent number: 10886316
    Abstract: A linear image sensor includes first and second sensor chips, first and second substrates, a common support substrate, a support portion, a dam portion, and a sealing portion. The first sensor chip is mounted to partially protrude on one end side of the first substrate. The second sensor chip is mounted to partially protrude on one end side of the second substrate. The first and second substrates are mounted on the common support substrate. The support portion is provided in a gap between the end faces of the first and second substrates. The dam portion is provided annularly to surround the sensor chips. The sealing portion seals the sensor chips, in a region surrounded by the dam portion.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: January 5, 2021
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Norihiro Muramatsu, Katsunori Nozawa
  • Patent number: 10886243
    Abstract: A method for preparing fan-out antenna packaging structure, includes: providing a carrier and a release layer structure; forming a single-layer antenna structure and a redistribution layer on an upper surface of the release layer; disposing a semiconductor chip electrically connected with the redistribution layer; forming a leading-out conducting wire on the redistribution layer at least on one side of the semiconductor chip; forming a plastic packaging layer wrapping the chip and the leading-out conducting wire; removing part of the plastic packaging layer to expose the chip and the leading-out conducting wire; forming an under-bump metal layer and a solder ball bump on an upper surface of the plastic packaging layer; removing the carrier and the release layer to expose the single-layer antenna structure; soldering a substrate on the solder ball bump; and forming a layer of cooling fins on a second surface of the semiconductor chip.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: January 5, 2021
    Assignee: SJ Semiconductor (Jiangyin) Corporation
    Inventors: Yenheng Chen, Chengchung Lin, Chengtar Wu, Jangshen Lin
  • Patent number: 10879334
    Abstract: A flexible display device is disclosed, which may prevent a crack from being generated even though a bending area is folded and prevents a gate driving circuit from being damaged and prevents a gate shift clock line from being shorted even though the crack is generated. The flexible display device comprises a substrate including a display area for displaying an image, a non-display area surrounding the display area, and a bending area. A pixel for displaying an image, an inorganic film for covering the pixel and a first organic film for covering the inorganic film are arranged on an area corresponding to the display area of the bending area, and the first organic film is arranged on an area corresponding to the non-display area of the bending area.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: December 29, 2020
    Assignee: LG Display Co., Ltd.
    Inventors: MinJic Lee, Yeseul Han, JeongOk Jo
  • Patent number: 10879171
    Abstract: One illustrative integrated circuit product disclosed herein includes a vertically oriented semiconductor (VOS) structure positioned above a semiconductor substrate, a conductive silicide vertically oriented e-fuse positioned along at least a portion of a vertical height of the VOS structure wherein the conductive silicide vertically oriented e-fuse comprises a metal silicide material that extends through at least a portion of an entire lateral width of the VOS structure, and a conductive metal silicide region in the semiconductor substrate that is conductively coupled to the conductive silicide vertically oriented e-fuse.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: December 29, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Chun Yu Wong, Kwan-Yong Lim, Seong Yeol Mun, Jagar Singh, Hui Zang
  • Patent number: 10876204
    Abstract: A substrate processing apparatus includes a processing container configured to accommodate and process a substrate, an exhaust pipe connected to the processing container, an evacuation part configured to evacuate an interior of the processing container via the exhaust pipe, an exhaust pipe coating gas nozzle provided in the vicinity of the exhaust pipe inside the processing container and configured to supply at least one of a silicon-containing gas and an oxidizing gas into the exhaust pipe via the processing container, and a heating part configured to heat the processing container.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: December 29, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Katsutoshi Ishii
  • Patent number: 10879429
    Abstract: A light emitting device includes: a light emitting element having an emission peak wavelength in a range of 430 nm to 470 nm; and a fluorescent member including a fluorescent material that is excited by light from the light emitting element for light emission, wherein a mixture of light from the light emitting element and light from the fluorescent material has a correlated color temperature in a range of 1500 K to 11000 K, as measured according to JIS Z8725, the color deviation duv that is a deviation from the black body radiation track on the CIE1931 chromaticity diagram of the mixture of light and is measured according to JIS Z8725 falls within a range of more than 0 to 0.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: December 29, 2020
    Assignee: NICHIA CORPORATION
    Inventors: Kenji Asai, Kazushige Fujio
  • Patent number: 10872945
    Abstract: A display device includes pixels, scan lines, and data lines. A first driving gate electrode is disposed at a first pixel of the display device. A second driving gate electrode is disposed at a second pixel of the display device. A first driving voltage line includes a first extending part that overlaps a first driving gate electrode. A second driving voltage line includes a second extending part that overlaps a second driving gate electrode. A first pixel electrode of the first pixel overlaps the second driving gate electrode. The second extending part includes a first recess portion. A center line of the first recess portion is offset in a direction away from the first pixel electrode with respect to a center line of the second driving gate electrode.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: December 22, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Jun Won Choi
  • Patent number: 10872799
    Abstract: A load port including: a tabular portion which constitutes a part of a wall surface of a wafer carrying chamber and has an opening through which the wafer carrying chamber is opened; a mounting table on which a wafer storage container is mounted; a door section which can open and close the opening; a sucking tool which can suck and hold a lid; a latch which can fix and unfix a container main body and lid; and a latch driving mechanism storage section which stores a latch driving mechanism therein, load port being configured to enable setting an air pressure in latch driving mechanism storage section to be equal to the air pressure in a clean room or lower than the air pressure in clean room. Consequently, it is possible to provide the load port and a method for carrying wafers which can prevent dust from adhering to the wafers.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: December 22, 2020
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Yuji Okubo, Seiji Satoh, Toshihiro Suzuki
  • Patent number: 10872970
    Abstract: Source and drain formation techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, wherein the fin structure include a channel region disposed between a source region and a drain region; forming a gate structure over the channel region of the fin structure; forming a solid phase diffusion (SPD) layer over the source region and the drain region of the fin structure; and performing a microwave annealing (MWA) process to diffuse a dopant from the SPD layer into the source region and the drain region of fin structure. In some implementations, the SPD layer is disposed over the fin structure, such that the dopant diffuses laterally and vertically into the source region and the drain region to form heavily doped source/drain features.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: December 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun Hsiung Tsai, Kuo-Feng Yu, Ziwei Fang
  • Patent number: 10867866
    Abstract: In a method of manufacturing a semiconductor device, a fin structure having a bottom portion, an intermediate portion disposed over the bottom portion and an upper portion disposed over the intermediate portion is formed. The intermediate portion is removed at a source/drain region of the fin structure, thereby forming a space between the bottom portion and the upper portion. An insulating layer is formed in the space. A source/drain contact layer is formed over the upper portion. The source/drain contact layer is separated by the insulating layer from the bottom portion of the fin structure.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Mark Van Dal, Gerben Doornbos