Abstract: Interconnect structures, packaged semiconductor devices, and methods of packaging semiconductor devices are disclosed. In some embodiments, an interconnect structure includes a polymer material and a post passivation interconnect (PPI) pad disposed over the polymer material. A PPI line is disposed within an opening in the polymer material, the PPI line being coupled to the PPI pad.

Abstract: A display device includes a plate-like substrate having a first surface and a second surface, pixel units on the first surface, and a power supply voltage feeder on the second surface. The power supply voltage feeder outputs first and second power supply voltages applicable to the pixel units. The second power supply voltage is lower in potential than the first power supply voltage. The display device includes a first wiring conductor electrically connecting the power supply voltage feeder and the pixel units and a second wiring conductor electrically connecting the power supply voltage feeder and the pixel units. At least one of the first or second wiring conductor includes a planar conductive portion covering the first surface. The planar conductive portion includes connectors connected to the power supply voltage feeder on at least two sides of the substrate.

Abstract: A high electron mobility transistor (HEMT) includes a substrate, a P-type III-V composition layer, a gate electrode and a carbon containing layer. The P-type III-V composition layer is disposed on the substrate, and the gate electrode is disposed on the P-type III-V composition layer. The carbon containing layer is disposed under the P-type III-V composition layer to function like an out diffusion barrier for preventing from the dopant within the P-type III-V composition layer diffusing into the stacked layers underneath during the annealing process.

Abstract: The invention relates to a front-side imager comprising in succession: —a semiconductor carrier substrate, a first electrically insulating separating layer, and a single-crystal semiconductor layer, called the active layer, comprising a matrix array of photodiodes, wherein the imager further comprises between the carrier substrate and the first electrically insulating layer: —a second electrically insulating separating layer, and —a second semiconductor or electrically conductive layer, called the intermediate layer, arranged between the second separating layer and the first separating layer, the second separating layer being thicker than the first separating layer.

Abstract: According to one embodiment, a display panel includes a substrate, a first insulating layer, a second insulating layer, and pixels including subpixels of colors. Each of the subpixels includes a drive transistor, a conductive layer, a pixel electrode receiving a signal having a controlled current value from the drive transistor via the conductive layer, and a light-emitting element. Each of the pixels has a mounting electrode overlaid on the conductive layer in each of the subpixels. In a first pixel of the pixels, the mounting electrode is in an electrically floating state.

Abstract: A method for manufacturing a semiconductor device and a semiconductor device, the method including forming an active pattern on a substrate such that the active pattern includes sacrificial patterns and semiconductor patterns alternately and repeatedly stacked on the substrate; and forming first spacer patterns at both sides of each of the sacrificial patterns by performing an oxidation process, wherein the first spacer patterns correspond to oxidized portions of each of the sacrificial patterns, wherein the sacrificial patterns include a first semiconductor material containing impurities, wherein the semiconductor patterns include a second semiconductor material different from the first semiconductor material, and wherein the impurities include an element different from semiconductor elements of the first semiconductor material and the second semiconductor material.

Abstract: The present application discloses a method for fabricating semiconductor device with a graphene-based element. The method includes providing a substrate; forming a stacked gate structure over the substrate; forming first spacers on sidewalls of the gate stack structure, wherein the first spacers comprise graphene; forming sacrificial spacers on sidewall of the first spacers; and forming second spacers on sidewall of the sacrificial spacers.

Abstract: An apparatus comprises a stack comprising an alternating sequence of dielectric structures and conductive structures, a first channel material extending vertically through the stack, and a second channel material adjacent the first channel material and extending vertically through the stack. The first channel material has a first band gap and the second channel material has a second band gap that is relatively larger than the first band gap. The apparatus further comprises a conductive plug structure adjacent to each of the first channel material and the second channel material, and a conductive line structure adjacent to the conductive plug structure. Methods of forming the apparatus, memory devices, and electronic systems are also described.

Abstract: An organic light-emitting device includes an anode electrode and a cathode electrode that are arranged facing each other; a light-emitting layer arranged between the anode electrode and the cathode electrode; and a hole transport layer arranged between the anode electrode and the light-emitting layer, and including one or more layers. A layer, of the one or more layers of the hole transport layer, contacting the light-emitting layer has a HOMO energy level 12bH that is higher than a HOMO energy level 13H of the light-emitting layer. A difference ?E1 between the HOMO energy level 12bH of the layer contacting the light-emitting layer of the hole transport layer and the HOMO energy level 13H of the light-emitting layer is 0.32 eV or less.

Abstract: A transistor including an oxide semiconductor layer can have stable electrical characteristics. In addition, a highly reliable semiconductor device including the transistor is provided. A semiconductor device includes a multi-layer film including an oxide layer and an oxide semiconductor layer, a gate insulating film in contact with the multi-layer film, and a gate electrode overlapping with the multi-layer film with the gate insulating film provided therebetween. In the semiconductor device, the oxide semiconductor layer contains indium, the oxide semiconductor layer is in contact with the oxide layer, and the oxide layer contains indium and has a larger energy gap than the oxide semiconductor layer.

Abstract: Apparatus and method relating generally to electronics are disclosed. In one such an apparatus, a film assembly has an upper surface and a lower surface opposite the upper surface. A dielectric film of the film assembly has a structured profile along the upper surface or the lower surface for having alternating ridges and grooves in a corrugated section in an at rest state of the film assembly. Conductive traces of the film assembly conform to the upper surface or the lower surface in or on the dielectric film in the corrugated section.

Abstract: A method for manufacturing a merged PiN Schottky (MPS) diode may include steps of providing a substrate having a first conductivity type; forming an epitaxial layer with the first conductivity type on top of the substrate; forming a plurality of regions with a second conductivity type under a top surface of the epitaxial layer; forming a plasma spreading layer; depositing and patterning a first Ohmic contact metal on the regions with the second conductivity type; depositing a Schottky contact metal on top of the entire epitaxial layer; and forming a second Ohmic contact metal on a backside of the substrate. In another embodiment, the step of forming a plurality of regions with a second conductivity type may include steps of depositing and patterning a mask layer on the epitaxial layer, implanting P-type dopant into the epitaxial layer, and removing the mask layer.

Abstract: A semiconductor package includes: a lead frame that includes a first surface and a second surface opposite to the first surface, where the lead frame includes a first lead that extends in a first direction, and a plurality of second leads that are spaced apart from the first lead on both sides of the first lead; at least one semiconductor chip mounted on the first surface of the lead frame by a plurality of bumps; and an encapsulant that encapsulates the lead frame and the at least one semiconductor chip, wherein the first lead has a groove in the first surface that partitions the plurality of bumps in contact with the first lead.

Abstract: A semiconductor device is described. The semiconductor device includes a substrate and a metal layer disposed on the substrate. A seed layer is formed on the metal layer. A ferroelectric gate layer is formed on the seed layer. A channel layer is formed over the ferroelectric gate layer. The seed layer is arranged to increase the orthorhombic phase fraction of the ferroelectric gate layer.

Abstract: The present invention provides a method of manufacturing a graphene transistor 101, the method comprising: (a) providing a substrate having a substantially flat surface, wherein the surface comprises an insulating region 110 and an adjacent semiconducting region 105; (b) forming a graphene layer structure 115 on the surface, wherein the graphene layer structure is disposed on and across a portion of both the insulating region and the adjacent semiconducting region; (c) forming a layer of dielectric material 120 on a portion of the graphene layer structure which is itself disposed on the semiconducting region 105; and (d) providing: a source contact 125 on a portion of the graphene layer structure which is itself disposed on the insulating region 110; a gate contact 130 on the layer of dielectric material 120 and above a portion of the graphene layer structure which is itself disposed on the semiconducting region 105; and a drain contact 135 on the semiconducting region 105 of the substrate surface.

Abstract: An integrated circuit device includes a plurality of gate structures each including a gate line extending on a fin-type active region and insulation spacers on sidewalls of the gate line; a source/drain contact between first and second gate structures, and having opposing sides that are asymmetric in the first horizontal direction; and an insulation liner on sidewalls of the source/drain contact. The source/drain contact includes a lower contact portion and an upper contact portion having a horizontal extension that extends on an upper corner of the first gate structure, the insulation liner includes a first local region between the upper corner and the horizontal extension and a second local region that is farther from the substrate than the first local region, and a thickness of the first local region is greater than that of the second local region.

Abstract: A semiconductor device includes a gate interconnect, extending in a first direction, and configured to transmit an input signal, and a transistor including gate electrodes extending in a second direction perpendicular to the first direction, and spaced apart from one another, and connected to the gate interconnect, and source and drain regions alternately arranged along the first direction, so that each gate electrode is sandwiched between the source and drain region which are adjacent to each other. The semiconductor device also includes drain interconnects, arranged above the drain regions, and connected to the drain regions, respectively, an output interconnect, connected to the drain interconnects, and configured to transmit an output signal output from the drain regions, and stubs connected to the drain interconnects, respectively. At least one of the stubs is connected to one of the drain interconnects at an end opposite from the gate interconnect.

Abstract: The current disclosure describes a vertical tunnel FET device including a vertical P-I-N heterojunction structure of a P-doped nanowire gallium nitride source/drain, an intrinsic InN layer, and an N-doped nanowire gallium nitride source/drain. A high-K dielectric layer and a metal gate wrap around the intrinsic InN layer.

Abstract: A light-emitting element having high external quantum efficiency is provided. A light-emitting element having a long lifetime is provided. A light-emitting element is provided which includes a light-emitting layer containing a phosphorescent compound, a first organic compound, and a second organic compound between a pair of electrodes, in which a combination of the first organic compound and the second organic compound forms an exciplex (excited complex). The light-emitting element transfers energy by utilizing an overlap between the emission spectrum of the exciplex and the absorption spectrum of the phosphorescent compound and thus has high energy transfer efficiency. Therefore, a light-emitting element having high external quantum efficiency can be obtained.

Abstract: A merged-PN-Schottky, MPS, diode includes an N substrate, an N-drift layer, a P-doped region in the drift layer, an ohmic contact on the P-doped region, a plurality of cells within the P-doped region and being portions of the drift layer where the P-doped region is absent, an anode metallization on the ohmic contact and on said cells, to form junction-barrier contacts and Schottky contacts respectively. The P-doped region has a grid-shaped layout separating from one another each cell and defining, together with the cells, an active area of the MPS diode. Each cell has a same geometry among quadrangular, quadrangular with rounded corners and circular; and the ohmic contact extends at the doped region with continuity along the grid-shaped layout.