Patents Examined by Moin M Rahman
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Patent number: 11967634Abstract: A semiconductor device includes a semiconductor element. The semiconductor element has a semiconductor layer, a first-conductivity-type layer, a saturation current suppression layer, a current dispersion layer, a base region, a source region, trench gate structures, an interlayer insulation film, a source electrode, a drain electrode, and a second deep layer. The first-conductivity-type layer is disposed above the semiconductor layer. The saturation current suppression layer disposed above the first-conductivity-type layer includes a first deep layer and a JEFT portion. The base region is disposed above the saturation current suppression layer. The source region and the contact region are disposed above the region. Each of the trench gate structures has a gate trench, a gate insulation film, and a gate electrode. The second deep layer is disposed among the trench gate structures and is connected to the first deep layer.Type: GrantFiled: May 25, 2022Date of Patent: April 23, 2024Assignees: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA, MIRISE Technologies CorporationInventors: Kensuke Nagata, Yohei Iwahashi, Ryota Suzuki, Katsuhiko Hamasaki
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Patent number: 11961889Abstract: A semiconductor device includes a substrate, a semiconductor channel layer, a semiconductor barrier layer, a gate electrode, a first electrode, and a dielectric layer. The semiconductor channel layer is disposed on the substrate, and the semiconductor barrier layer is disposed on the semiconductor channel layer. The gate electrode is disposed on the semiconductor barrier layer. The first electrode is disposed at one side of the gate electrode. The first electrode includes a body portion and a vertical extension portion. The body portion is electrically connected to the semiconductor barrier layer, and the bottom surface of the vertical extension portion is lower than the top surface of the semiconductor channel layer. The dielectric layer is disposed between the vertical extension portion and the semiconductor channel layer.Type: GrantFiled: September 22, 2022Date of Patent: April 16, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventor: Po-Yu Yang
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Patent number: 11961761Abstract: One or more techniques or systems for mitigating pattern collapse are provided herein. For example, a semiconductor structure for mitigating pattern collapse is formed. In some embodiments, the semiconductor structure includes an extreme low-k (ELK) dielectric region associated with a via or a metal line. For example, a first metal line portion and a second metal line portion are associated with a first lateral location and a second lateral location, respectively. In some embodiments, the first portion is formed based on a first stage of patterning and the second portion is formed based on a second stage of patterning. In this manner, pattern collapse associated with the semiconductor structure is mitigated, for example.Type: GrantFiled: March 15, 2021Date of Patent: April 16, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Chih-Yuan Ting, Ya-Lien Lee, Chung-Wen Wu, Jeng-Shiou Chen
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Patent number: 11956952Abstract: A device, including: a first structure including first memory cells, the first memory cells including first transistors; and a second structure including second memory cells, the second memory cells including second transistors, where the second transistors overlay the first transistors, and a plurality of memory cells control lines, where the first transistors are self-aligned to the second transistors, where a second transistor channel of the second transistors is aligned to a first transistor channel of the first transistors, the aligned is at an atomic level as would have been resulted from an epitaxial growth process.Type: GrantFiled: August 22, 2016Date of Patent: April 9, 2024Assignee: Monolithic 3D Inc.Inventors: Zvi Or-Bach, Jin-Woo Han
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Patent number: 11949212Abstract: The present disclosure provides a method and structure for producing large area gallium and nitrogen engineered substrate members configured for the epitaxial growth of layer structures suitable for the fabrication of high performance semiconductor devices. In a specific embodiment the engineered substrates are used to manufacture gallium and nitrogen containing devices based on an epitaxial transfer process wherein as-grown epitaxial layers are transferred from the engineered substrate to a carrier wafer for processing. In a preferred embodiment, the gallium and nitrogen containing devices are laser diode devices operating in the 390 nm to 425 nm range, the 425 nm to 485 nm range, the 485 nm to 550 nm range, or greater than 550 nm.Type: GrantFiled: December 22, 2020Date of Patent: April 2, 2024Assignee: KYOCERA SLD Laser, Inc.Inventors: Melvin McLaurin, James W. Raring
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Patent number: 11935931Abstract: Techniques for selective CD shrink for source and drain contact trench to optimize FET device performance are provided. In one aspect, a semiconductor FET device includes: at least one gate; source and drains on opposite sides of the at least one gate; recesses in the source and drains; and metal contacts disposed over the source and drains and in the recesses, wherein the metal contacts are in direct contact with a bottom and sidewalls of each of the recesses in both a first direction and a second direction, wherein the first direction is perpendicular to the at least one gate, and wherein the second direction is parallel to the at least one gate. A method of forming a semiconductor FET device is also provided.Type: GrantFiled: June 6, 2020Date of Patent: March 19, 2024Assignee: International Business Machines CorporationInventors: Ruilong Xie, Jing Guo, Ekmini Anuja De Silva, Abraham Arceo de la Pena
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Patent number: 11935940Abstract: A method for making a bipolar junction transistor (BJT) may include forming a first superlattice on a substrate defining a collector region therein. The first superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a base on the first superlattice, and forming a second superlattice on the base comprising a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may also include forming an emitter on the second superlattice.Type: GrantFiled: July 26, 2022Date of Patent: March 19, 2024Assignee: ATOMERA INCORPORATEDInventor: Richard Burton
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Patent number: 11928988Abstract: A plurality of display panels having a curved surface are placed in a limited space. Two, or three or more display panels are combined to form one display region having a T-shaped outer edge as one screen, and a driver can curve part of the display panel as appropriate so that the driver can see the screen easily. A first display panel or a second display panel has flexibility and includes a position adjustment function of curving an end portion. That is, by curving part of the display panel, the user can see the display panel easily. The in-car design can also be varied.Type: GrantFiled: June 2, 2022Date of Patent: March 12, 2024Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yosuke Tsukamoto, Daiki Nakamura, Daisuke Furumatsu, Kazuhiko Fujita, Kyoichi Mukao, Junya Maruyama
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Patent number: 11923427Abstract: A semiconductor device includes a semiconductor substrate, a control gate, a select gate, a charge trapping structure, and a dielectric structure. The semiconductor substrate has a drain region, a source region, and a channel region between the drain region and the source region. The control gate is over the channel region of the semiconductor substrate. The select gate is over the channel region of the semiconductor substrate and separated from the control gate. The charge trapping structure is between the control gate and the semiconductor substrate. The dielectric structure is between the select gate and the semiconductor substrate. The dielectric structure has a first part and a second part, the first part is between the charge trapping structure and the second part, and the second part is thicker than the first part.Type: GrantFiled: February 25, 2021Date of Patent: March 5, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Meng-Han Lin, Wei-Cheng Wu, Te-Hsin Chiu
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Patent number: 11908909Abstract: A semiconductor may include an active region, an epitaxial source/drain formed in and extending above the active region, and a first dielectric layer formed over a portion of the active region. The semiconductor may include a first metal gate and a second metal gate formed in the first dielectric layer, a second dielectric layer formed over the first dielectric layer and the second metal gate, and a titanium layer, without an intervening fluorine residual layer, formed on the metal gate and the epitaxial source/drain. The semiconductor may include a first metal layer formed on top of the titanium on the first metal gate, a second metal layer formed on top of the titanium layer on the epitaxial source/drain, and a third dielectric layer formed on the second dielectric layer. The semiconductor may include first and second vias formed in the third dielectric layer.Type: GrantFiled: July 29, 2022Date of Patent: February 20, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Ting Tsai, Chung-Liang Cheng, Hong-Ming Lo, Chun-Chih Lin, Chyi-Tsong Ni
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Patent number: 11910626Abstract: A light-emitting device includes: a substrate including a first subpixel, as second subpixel, and a third subpixel; a plurality of first electrodes respectively in the first subpixel, the second subpixel, and the third subpixel of the substrate; a second electrode facing the first electrode; an emission layer located between the plurality of first electrodes and the second electrode; a hole injection layer between the plurality of first electrodes and the emission layer; a first common layer between the hole injection layer and the emission layer, the first common layer integrated with the first subpixel, the second subpixel, and the third subpixel; a second common layer between the hole injection layer and the first common layer, the second common layer integrated with the first subpixel, the second subpixel, and the third subpixel, wherein the first common layer and the second common layer satisfy certain conditions.Type: GrantFiled: September 26, 2020Date of Patent: February 20, 2024Assignee: Samsung Display Co., Ltd.Inventors: Hyomin Kim, Illsoo Park, Sijin Sung, Gina Yoo, Sunhwa Kim, Jaehong Kim, Heeseong Jeong, Jongseok Han
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Patent number: 11908842Abstract: Disclosed are embodiments of apparatus and methods that provide light emitting displays with improved wide angle color viewing. A plurality of light emitting elements is arranged in a predetermined pattern and collectively creates a viewing plane. A portion of the light emitting elements are disposed in a primary orientation while the remainder of the light emitting element are disposed in a complementary orientation. Each light emitting element in a primary orientation is adjacent to a light emitting element in the complementary orientation. The spatial light emission pattern of the primary orientation is complementary to the spatial light emission pattern of the complementary orientation. Adjacent pairs of primary-complementary oriented light emitting elements cancel a substantial amount of color variation that would otherwise be seen when one varies the gaze angle upon the viewing plane.Type: GrantFiled: December 17, 2021Date of Patent: February 20, 2024Assignee: Nanolumens Acquisition, Inc.Inventor: Jorge Perez-Bravo
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Patent number: 11908949Abstract: A semiconductor device with a high on-state current is provided. The semiconductor device includes a first oxide, a second oxide over the first oxide, a third oxide over the second oxide, a first insulator over the third oxide, a conductor over the first insulator, a second insulator in contact with the second oxide and the third oxide, and a third insulator over the second insulator; the second oxide includes first region to fifth regions; the resistance of the first region and the resistance of the second region are lower than the resistance of the third region; the resistance of the fourth region and the resistance of the fifth region are lower than the resistance of the third region and higher than the resistance of the first region and the resistance of the second region; and the conductor is provided over the third region, the fourth region, and the fifth region to overlap with the third region, the fourth region, and the fifth region.Type: GrantFiled: December 8, 2022Date of Patent: February 20, 2024Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yuki Hata, Katsuaki Tochibayashi, Junpei Sugao, Shunpei Yamazaki
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Patent number: 11897761Abstract: In one example, an electronic device includes a semiconductor sensor device having a cavity extending partially inward from one surface to provide a diaphragm adjacent an opposite surface. A barrier is disposed adjacent to the one surface and extends across the cavity, the barrier has membrane with a barrier body and first barrier strands bounded by the barrier body to define first through-holes. The electronic device further comprises one or more of a protrusion pattern disposed adjacent to the barrier structure, which can include a plurality of protrusion portions separated by a plurality of recess portions; one or more conformal membrane layers disposed over the first barrier strands; or second barrier strands disposed on and at least partially overlapping the first barrier strands. The second barrier strands define second through-holes laterally offset from the first through-holes. Other examples and related methods are also disclosed herein.Type: GrantFiled: June 6, 2022Date of Patent: February 13, 2024Assignee: Amkor Technology Singapore Holding Pte. Ltd.Inventors: Ki Yeul Yang, Kyung Han Ryu, Seok Hun Yun, Bora Baloglu, Hyun Cho, Ramakanth Alapati
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Patent number: 11901433Abstract: A device includes a first III-V compound layer, a second III-V compound layer, a dielectric layer, a contact, a metal-containing layer, and a metal contact. The second III-V compound layer is over the first III-V compound layer. The dielectric layer is over the second III-V compound layer. The contact extends through the dielectric layer to the second III-V compound layer. The contact is in contact with a top surface of the dielectric layer and an inner sidewall of the dielectric layer. The metal-containing layer is over and in contact with the contact, and a portion of the metal-containing layer is directly above the dielectric layer. The metal contact is over and in contact with the metal-containing layer.Type: GrantFiled: August 24, 2021Date of Patent: February 13, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jheng-Sheng You, Hsin-Chih Lin, Kun-Ming Huang, Lieh-Chuan Chen, Po-Tao Chu, Shen-Ping Wang, Chien-Li Kuo
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Patent number: 11901344Abstract: A manufacturing method of a semiconductor package is provided as follows. A semiconductor die is provided, wherein the semiconductor die comprises a semiconductor substrate, an interconnection layer and a through semiconductor via, the interconnection layer is disposed on an active surface of the semiconductor substrate, the through semiconductor via penetrates the semiconductor substrate from a back surface of the semiconductor substrate to the active surface of the semiconductor substrate. An encapsulant is provided to laterally encapsulate the semiconductor die. A through encapsulant via penetrating through the encapsulant is formed.Type: GrantFiled: October 21, 2021Date of Patent: February 13, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Shing-Yih Shih
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Patent number: 11895836Abstract: Some embodiments of the present application are directed towards an integrated circuit (IC). The integrated circuit includes a semiconductor substrate having a peripheral region and a memory cell region separated by an isolation structure. The isolation structure extends into a top surface of the semiconductor substrate and comprises dielectric material. A logic device is arranged on the peripheral region. A memory device is arranged on the memory region. The memory device includes a gate electrode and a memory hardmask over the gate electrode. An anti-dishing structure is disposed on the isolation structure. An upper surface of the anti-dishing structure and an upper surface of the memory hardmask have equal heights as measured from the top surface of the semiconductor substrate.Type: GrantFiled: September 16, 2020Date of Patent: February 6, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Meng-Han Lin, Chih-Ren Hsieh, Chen-Chin Liu, Chih-Pin Huang
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Patent number: 11894434Abstract: A semiconductor device includes a substrate, a semiconductor channel layer, a semiconductor barrier layer, a gate electrode, a first electrode, and a dielectric layer. The semiconductor channel layer is disposed on the substrate, and the semiconductor barrier layer is disposed on the semiconductor channel layer. The gate electrode is disposed on the semiconductor barrier layer. The first electrode is disposed at one side of the gate electrode. The first electrode includes a body portion and a vertical extension portion. The body portion is electrically connected to the semiconductor barrier layer, and the bottom surface of the vertical extension portion is lower than the top surface of the semiconductor channel layer. The dielectric layer is disposed between the vertical extension portion and the semiconductor channel layer. The first electrode is a conformal layer covers the semiconductor barrier layer and the dielectric layer.Type: GrantFiled: September 28, 2022Date of Patent: February 6, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventor: Po-Yu Yang
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Patent number: 11888037Abstract: A power semiconductor device includes a wide-bandgap semiconductor layer having an active region and a termination region that laterally surrounds the active region. The wide-bandgap semiconductor layer has a first recess that is recessed from the first main side in the termination region and surrounds the active region and a second recess that is recessed from the first main side in the active region and is filled with an insulating material. A depth of the second recess is the same as a depth of the first recess. A field plate on the first main side of the wide-bandgap semiconductor layer exposes a first portion of the wide-bandgap semiconductor layer in the termination region.Type: GrantFiled: March 5, 2019Date of Patent: January 30, 2024Assignee: Hitachi Energy LtdInventors: Andrei Mihaila, Lars Knoll, Lukas Kranz
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Patent number: 11881433Abstract: A device relates to a semiconductor device. The semiconductor device includes a narrow-line bamboo microstructure integrated within a metal layer of the semiconductor device and a narrow-line polycrystalline microstructure. The narrow-line polycrystalline microstructure is integrated within the same metal layer as the narrow-line bamboo microstructure.Type: GrantFiled: December 9, 2021Date of Patent: January 23, 2024Assignee: Tessera LLCInventors: Daniel C. Edelstein, Chih-Chao Yang