Patents Examined by Moin M Rahman
  • Patent number: 11367726
    Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and access lines and vertically oriented digit lines having a first source/drain region and a second source drain region separated by a channel region, and gates opposing the channel region formed fully around every surface of the channel region as gate all around (GAA) structures, horizontal oriented access lines coupled to the gates and separated from a channel region by a gate dielectric. The memory cells have horizontally oriented storage nodes coupled to the second source/drain region and vertically oriented digit lines coupled to the first source/drain regions. A vertical body contact is formed in direct electrical contact with a body region of one or more of the horizontally oriented access devices and separate from the first source/drain region and the vertically oriented digit lines by a dielectric.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: June 21, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Si-Woo Lee, Sangmin Hwang
  • Patent number: 11362177
    Abstract: One illustrative transistor of a first dopant type disclosed herein includes a gate structure positioned above a semiconductor substrate and first and second overall epitaxial cavities formed in the semiconductor substrate on opposite sides of the gate structure. The device also includes a counter-doped epitaxial semiconductor material positioned proximate a bottom of each of the first and second overall epitaxial cavities, wherein the counter-doped epitaxial semiconductor material is doped with a second dopant type that is opposite to the first dopant type, and a same-doped epitaxial semiconductor material positioned in each of the first and second overall epitaxial cavities above the counter-doped epitaxial semiconductor material, wherein the same-doped epitaxial semiconductor material is doped with a dopant of the first dopant type.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: June 14, 2022
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Arkadiusz Malinowski, Baofu Zhu, Frank W. Mont, Ali Razavieh, Julien Frougier
  • Patent number: 11362294
    Abstract: Provided is an organic light-emitting diode. The organic light-emitting diode includes a first electrode, a second electrode, a light-emitting layer and a hole blocking layer, where the first electrode and the second electrode are oppositely disposed; the light-emitting layer is disposed between the first electrode and the second electrode; the hole blocking layer is disposed between the light-emitting layer and the second electrode; and the hole blocking layer includes at least two hole blocking sub-layers which are stacked, where a lowest unoccupied molecular orbital (LUMO) energy level decreases sequentially in the at least two hole blocking sub-layers.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: June 14, 2022
    Assignee: YUNGU (GU'AN) TECHNOLOGY CO., LTD.
    Inventors: Weiwei Li, Chao Chi Peng, Lin He, Jingwen Tian, Tiantian Li, Mengzhen Li
  • Patent number: 11355590
    Abstract: The current disclosure describes a vertical tunnel FET device including a vertical P-I-N heterojunction structure of a P-doped nanowire gallium nitride source/drain, an intrinsic InN layer, and an N-doped nanowire gallium nitride source/drain. A high-K dielectric layer and a metal gate wrap around the intrinsic InN layer.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: June 7, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Peter Ramvall, Matthias Passlack
  • Patent number: 11352252
    Abstract: In one example, an electronic device includes a semiconductor sensor device having a cavity extending partially inward from one surface to provide a diaphragm adjacent an opposite surface. A barrier is disposed adjacent to the one surface and extends across the cavity, the barrier has membrane with a barrier body and first barrier strands bounded by the barrier body to define first through-holes. The electronic device further comprises one or more of a protrusion pattern disposed adjacent to the barrier structure, which can include a plurality of protrusion portions separated by a plurality of recess portions; one or more conformal membrane layers disposed over the first barrier strands; or second barrier strands disposed on and at least partially overlapping the first barrier strands. The second barrier strands define second through-holes laterally offset from the first through-holes. Other examples and related methods are also disclosed herein.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: June 7, 2022
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Ki Yeul Yang, Kyung Han Ryu, Seok Hun Yun, Bora Baloglu, Hyun Cho, Ramakanth Alapati
  • Patent number: 11355594
    Abstract: A diode includes an n-type semiconductor layer including an n-type Ga2O3-based single crystal, and a p-type semiconductor layer including a p-type semiconductor in which a volume of an amorphous portion is higher than a volume of a crystalline portion. The n-type semiconductor layer and the p-type semiconductor layer form a pn junction.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: June 7, 2022
    Assignees: Tamura Corporation, Novel Crystal Technology, Inc.
    Inventor: Kohei Sasaki
  • Patent number: 11349071
    Abstract: A memory device may include at least one inert electrode, at least one active electrode, an insulating element arranged at least partially between the at least one active electrode and the at least one inert electrode, and a switching element arranged under the insulating element. The switching element may be arranged at least partially between the at least one active electrode and the at least one inert electrode. The switching element may include a first end and a second end contacting the at least one active electrode; and a middle segment between the first end and the second end, where the middle segment may at least partially contact the at least one inert electrode.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: May 31, 2022
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Desmond Jia Jun Loy, Eng Huat Toh, Shyue Seng Tan, Steven Soss
  • Patent number: 11349093
    Abstract: The present application provides an organic electroluminescent device and a display apparatus. The organic electroluminescent device includes a first conductive layer group, a second conductive layer group, and a light emitting layer disposed between the first conductive layer group and the second conductive layer group and in ohmic contact with the two groups. The first conductive layer group includes an electron blocking layer in ohmic contact with the light emitting layer, and a hole transport layer in ohmic contact with the electron blocking layer. The HOMO energy level of the electron blocking layer is between that of the hole transport layer and that of the light emitting layer, and the LUMO energy level of the electron blocking layer is shallower than that of the hole transport layer and that of the light emitting layer.
    Type: Grant
    Filed: April 28, 2018
    Date of Patent: May 31, 2022
    Assignee: KUNSHAN GO-VISIONOX OPTO-ELECTRONICS CO., LTD.
    Inventors: Xiaozhen Zhang, Lin He, Wenkai Chen
  • Patent number: 11342429
    Abstract: A semiconductor device and method of making the same are disclosed. The semiconductor device includes a memory gate on a charge storage structure formed on a substrate, a select gate on a gate dielectric on the substrate proximal to the memory gate, and a dielectric structure between the memory gate and the select gate, and adjacent to sidewalls of the memory gate and the select gate, wherein the memory gate and the select gate are separated by a thickness of the dielectric structure. Generally, the dielectric structure comprises multiple dielectric layers including a first dielectric layer adjacent the sidewall of the memory gate, and a nitride dielectric layer adjacent to the first dielectric layer and between the memory gate and the select gate. Other embodiments are also disclosed.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: May 24, 2022
    Assignee: Cypress Semiconductor Corporation
    Inventors: Shenqing Fang, Chun Chen, Unsoon Kim, Mark T. Ramsbey, Kuo Tung Chang, Sameer S. Haddad, James Pak
  • Patent number: 11342241
    Abstract: A power module, including: a first conductor, disposed at a first reference plane; a second conductor, disposed at a second reference plane, wherein projections of the first and second conductors on the first reference plane have a first overlap area; a third conductor, disposed at a third reference plane; a plurality of first switches, first ends of which are coupled to the first conductor; and a plurality of second switches, first ends of which are coupled to second ends of the first switches through the third conductor, and second ends of the second switches are coupled to the second conductor, wherein projections of minimum envelope areas of the first and second switches on the first reference plane have a second overlap area, and the first and second overlap areas have an overlap region. Heat sources of the power module are evenly distributed and its parasitic inductance is low.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: May 24, 2022
    Assignee: Delta Electronics (Shanghai) CO., LTD
    Inventors: Wei Cheng, Shouyu Hong, Dongfang Lian, Tao Wang, Zhenqing Zhao
  • Patent number: 11329190
    Abstract: There is provided a light emitting device including: a substrate; and a laminated structure provided on the substrate and having a plurality of columnar portion groups, in which the columnar portion group includes at least one first columnar portion, and a plurality of second columnar portions, the first columnar portion has a light emitting layer into which a current is injected to generate light, no current is injected into the second columnar portion, an optical confinement mode is formed in the plurality of columnar portion groups, the first columnar portion is disposed at a position that overlaps a peak of electric field intensity, and the second columnar portion is disposed at a position that does not overlap the peak of electric field intensity.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: May 10, 2022
    Inventors: Shunsuke Ishizawa, Katsumi Kishino
  • Patent number: 11329165
    Abstract: A semiconductor device structure is provided, which includes a first fin structure over a semiconductor substrate. The first fin structure has multiple first semiconductor nanostructures suspended over the semiconductor substrate. The semiconductor device structure includes a second fin structure over the semiconductor substrate, and the second fin structure has multiple second semiconductor nanostructures suspended over the semiconductor substrate. The semiconductor device structure includes a dielectric fin between the first fin structure and the second fin structure. In addition, the semiconductor device structure includes a metal gate stack wrapping around the first fin structure, the second fin structure, and the dielectric fin. The semiconductor device structure includes a dielectric protection structure over the metal gate stack.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: May 10, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Cheng Chiang, Huan-Chieh Su, Kuan-Ting Pan, Shi-Ning Ju, Chih-Hao Wang
  • Patent number: 11329193
    Abstract: An optoelectronic semiconductor component and a method for producing an optoelectronic semiconductor component are disclosed.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: May 10, 2022
    Assignee: OSRAM OLED GMBH
    Inventors: Xiaojun Chen, Alexander Frey, Philipp Drechsel, Thomas Lehnhardt, Lise Lahourcade, J├╝rgen Off
  • Patent number: 11322410
    Abstract: Methods for tuning threshold voltages of fin-like field effect transistor (FinFET) devices are disclosed herein. An exemplary integrated circuit device includes a high voltage n-type FinFET, a high voltage p-type FinFET, a low voltage n-type FinFET, and a low voltage p-type FinFET. Threshold voltages of the high voltage n-type FinFET and the high voltage p-type FinFET are greater than threshold voltages of the low voltage n-type FinFET and the low voltage p-type FinFET, respectively. The high voltage n-type FinFET, the high voltage p-type FinFET, the low voltage n-type FinFET, and the low voltage p-type FinFET each include a threshold voltage tuning layer that includes tantalum and nitrogen. Thicknesses of the threshold voltage tuning layer of the low voltage n-type FinFET and the low voltage p-type FinFET are less than thicknesses of the threshold voltage tuning layer of the high voltage n-type FinFET and the high voltage p-type FinFET, respectively.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: May 3, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Liang Cheng, Wei-Jen Chen, Yen-Yu Chen, Ming-Hsien Lin
  • Patent number: 11322457
    Abstract: Embodiments include semiconductor device packages and methods of forming such packages. In an embodiment, the package may include a die-side reinforcement layer with a cavity formed through the die-side reinforcement layer. A die having a first side and an opposite second side comprising a device side may be positioned in the cavity with the first side of the die being substantially coplanar with a first side of the die-side reinforcement layer. In an embodiment, a build-up structure may be coupled to a second side of the die. Embodiments include a build-up structure that includes a plurality of alternating layers of patterned conductive material and insulating material.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: May 3, 2022
    Assignee: Intel Corporation
    Inventors: Digvijay A. Raorane, Ian En Yoon Chin, Daniel N. Sobieski
  • Patent number: 11315785
    Abstract: A method includes providing a semiconductor substrate; epitaxially growing a blocking layer from a top surface of the semiconductor substrate, wherein the blocking layer has a lattice constant different from the semiconductor substrate; epitaxially growing a semiconductor layer above the blocking layer; patterning the semiconductor layer to form a semiconductor fin, wherein the blocking layer is under the semiconductor fin; forming a source/drain (S/D) feature in contact with the semiconductor fin; and forming a gate structure engaging the semiconductor fin.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: April 26, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Che Chiang, Wei-Chih Kao, Chun-Sheng Liang, Kuo-Hua Pan
  • Patent number: 11315921
    Abstract: An integrated circuit die includes a FinFET transistor. The FinFET transistor includes an anti-punch through region below a channel region. Undesirable dopants are removed from the anti-punch through region during formation of the source and drain regions. When source and drain recesses are formed, a layer of dielectric material is deposited in the recesses. An annealing process is then performed. Undesirable dopants diffuse from the anti-punch through region into the layer of dielectric material during the annealing process. The layer of dielectric material is then removed. The source and drain regions are then formed by depositing semiconductor material in the recesses.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: April 26, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Chen Ho, Chien Lin, Tzu-Wei Lin, Ju Ru Hsieh, Ching-Lun Lai, Ming-Kai Lo
  • Patent number: 11309434
    Abstract: A semiconductor device includes a layer stack with a plurality of first semiconductor layers of a first doping type and a plurality of second semiconductor layers of a second doping type complementary to the first doping type. A first semiconductor region of a first semiconductor device adjoins the first semiconductor layers. Each second semiconductor region of the first semiconductor device adjoins at least one of the second semiconductor layers, and is spaced apart from the first semiconductor region. A third semiconductor layer adjoins the layer stack and each first semiconductor region and each second semiconductor region. The third semiconductor layer includes a first region arranged between the first semiconductor region and the second semiconductor region in a first direction. A third semiconductor region of the first or the second doping type extends from a first surface of the third semiconductor layer into the first region.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: April 19, 2022
    Assignee: Infineon Technologies Dresden GmbH & Co. KG
    Inventors: Ahmed Mahmoud, Rolf Weis, Armin Willmeroth
  • Patent number: 11302879
    Abstract: A flexible display substrate and a manufacturing method therefor, and a display apparatus, for relieving the problem that it is difficult to bend the flexible display substrate in a bending region to damage an upper circuit. The flexible display substrate comprises a back film, a first flexible base substrate located above the back film, and a second flexible base substrate located on one side of the first flexible base substrate facing away from the back film. The flexible display substrate has a bending region. An auxiliary layer is further provided between the first flexible base substrate and the second flexible base substrate. At least part of the auxiliary layer in the bending region can be decomposed in a preset condition, wherein the other film layers except the auxiliary layer are maintained at the original status in the preset condition.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: April 12, 2022
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Lu Liu, Pao Ming Tsai, Peng Cai, Hong Li, Dejun Bu, Jianwei Li, Liqiang Chen
  • Patent number: 11296149
    Abstract: A display substrate having an array of a plurality of subpixels is provided. The display substrate includes a base substrate; a pixel driving layer including a plurality of thin film transistors on the base substrate; a tuning layer on a side of the pixel driving layer away from the base substrate, thicknesses of the tuning layer being different in subpixels of different colors; and a plurality of organic light emitting diodes on a side of the tuning layer away from the pixel driving layer. A respective one of the plurality of organic light emitting diodes includes a hole injection layer, thicknesses of the hole injection layer being different in subpixels of different colors. The thicknesses of the tuning layer and the thicknesses of the hole injection layer are negatively correlated among the subpixels of different colors.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: April 5, 2022
    Assignees: Hefei Xinsheng Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Youyuan Hu, Mengyu Luan