Abstract: A sacrificial memory opening fill structure for a multi-tier memory device may include a semiconductor fill material portion a metallic fill material portion to enhance control of a vertical cross-sectional profile of an inter-tier memory opening. Multiple inter-tier dielectric layers may be employed to reduce sharp corners in a memory opening fill structure. Alternatively or additionally, a combination of an isotropic etch process followed by an anisotropic etch process may be used to form a first-tier memory opening.

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a lower portion of a stack that will comprise vertically-alternating conductive tiers and insulative tiers. The stack comprises laterally-spaced memory-block regions. The lower portion comprises multiple lower of the conductive tiers and multiple lower of the insulative tiers. The lower insulative tiers comprise insulative material. The lower conductive tiers comprise sacrificial material that is of different composition from that of the insulative material. The sacrificial material is replaced with conducting material. After the replacing of the sacrificial material, the vertically-alternating conductive tiers and insulative tiers of an upper portion of the stack are formed above the lower portion. The upper portion comprises multiple upper of the conductive tiers and multiple upper of the insulative tiers. The upper insulative tiers comprise insulating material.

Abstract: A microelectronic unit may include an epitaxial silicon layer having a source and a drain, a buried oxide layer beneath the epitaxial silicon layer, an ohmic contact extending through the buried oxide layer, a dielectric layer beneath the buried oxide layer, and a conductive element extending through the dielectric layer. The source and the drain may be doped portions of the epitaxial silicon layer. The ohmic contact may be coupled to a lower surface of one of the source or the drain. The conductive element may be coupled to a lower surface of the ohmic contact. A portion of the conductive element may be exposed at the second dielectric surface of the dielectric layer. The second dielectric surface may be directly bonded to an external component to form a microelectronic assembly.

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack structure of a quantum dot device, wherein the quantum well stack structure includes an insulating material to define multiple rows of quantum dot formation regions; and a gate that extends over multiple ones of the rows.

Abstract: A semiconductor device includes a substrate, a p-type well over the substrate and having a p-type anti-punch-through (APT) layer, an n-type source feature and an n-type drain feature over the p-type APT layer, and multiple first channel layers suspended over the p-type APT layer and connecting the n-type source feature to the n-type drain feature. The multiple first channel layers are vertically stacked one over another and are undoped. The semiconductor device further includes a high-k metal gate wrapping around each of the first channel layers, a first source contact disposed over and electrically coupled to the n-type source feature, and a drain contact disposed over and electrically coupled to the n-type drain feature. A bottom surface of the n-type source feature is about 5 nm to about 25 nm below an interface between the high-k metal gate and the p-type APT layer.

Abstract: A method of fabricating a semiconductor device includes the following steps. A substrate is provided. A semiconductor channel layer is formed on the substrate. A semiconductor barrier layer is formed on the semiconductor channel layer. An etching process is performed to expose a portion of the semiconductor channel layer. A dielectric layer is formed to cover the semiconductor barrier layer and the exposed semiconductor channel layer. A first electrode is formed after forming the dielectric layer, where the first electrode includes a body portion and a vertical extension portion, the body portion is electrically connected to the semiconductor barrier layer, and a bottom surface of the vertical extension portion is lower than a top surface of the semiconductor channel layer.

Abstract: A circuit device having an interlayer dielectric with pillar-type air gaps and a method of forming the circuit device are disclosed. In an exemplary embodiment, the method comprises receiving a substrate and depositing a first layer over the substrate. A copolymer layer that includes a first constituent polymer and a second constituent polymer is formed over the first layer. The first constituent polymer is selectively removed from the copolymer layer. A first region of the first layer corresponding to the selectively removed first constituent polymer is etched. The etching leaves a second region of the first layer underlying the second constituent polymer unetched. A metallization process is performed on the etched substrate, and the first layer is removed from the second region to form an air gap. The method may further comprise depositing a dielectric material within the etched first region.

Abstract: A display device includes an auxiliary wiring located on a substrate; an insulating layer arranged on the auxiliary wiring, overlapping the auxiliary wiring in a plan view, and including an opening having a width greater than a width of the auxiliary wiring; a first electrode located on the insulating layer; a bank layer including an emission opening that overlaps the first electrode in a plan view; an intermediate layer overlapping the first electrode through an emission opening in a plan view and including an emission layer; a second electrode on the intermediate layer; and an auxiliary layer arranged on the second electrode, wherein the auxiliary wiring includes sub-layers, and each of the second electrode and the auxiliary layer contacts a side surface of one of the sub-layers through the opening of the insulating layer.

Abstract: An imaging device according to an embodiment of the present disclosure includes: a semiconductor layer having one surface serving as a light incident surface and another surface opposed to the one surface, and having a light reception region and a peripheral region in the one surface, the light reception region in which a plurality of photoelectric converters that performs photoelectric conversion on incident light is arranged, and the peripheral region provided around the light reception region; a through via that penetrates between the one surface and the other surface; a first coupling section that is provided on the peripheral region on the one surface side, and has a width wider than the through via; a second coupling section that is provided on the peripheral region on the one surface side, and is used for coupling to an external substrate; a first semiconductor element including a coupling wiring line that electrically couples the first coupling section, the second coupling section, and the through via

Abstract: A 3-dimensional vertical memory string array includes high-speed ferroelectric field-effect transistor (FET) cells that are low-cost, low-power, or high-density and suitable for SCM applications. The memory circuits of the present invention provide random-access capabilities. The memory string may be formed above a planar surface of substrate and include a vertical gate electrode extending lengthwise along a vertical direction relative to the planar surface and may include (i) a ferroelectric layer over the gate electrode, (ii) a gate oxide layer; (iii) a channel layer provided over the gate oxide layer; and (iv) conductive semiconductor regions embedded in and isolated from each other by an oxide layer, wherein the gate electrode, the ferroelectric layer, the gate oxide layer, the channel layer and each adjacent pair of semiconductor regions from a storage transistor of the memory string, and wherein the adjacent pair of semiconductor regions serve as source and drain regions of the storage transistor.

Abstract: A circuit capable of high-speed operation and a pixel are integrally formed over the same substrate. A first metal oxide film, a first metal film, and an island-shaped first resist mask are formed over a first insulating layer. An island-shaped first metal layer and an island-shaped first oxide semiconductor layer are formed and a part of a top surface of the first insulating layer is exposed; then, the first resist mask is removed. A second metal oxide film, a second metal film, and an island-shaped second resist mask are formed over the first metal layer and the first insulating layer. An island-shaped second metal layer and an island-shaped second oxide semiconductor layer are formed; then, the second resist mask is removed. The first metal layer and the second metal layer are removed.

Abstract: A semiconductor device includes a vertical stack of gate electrodes. The gate electrodes extend in different lengths to provide contact regions. The gate electrodes have a conductive region and an insulating region. Contact plugs fills contact holes that pass through the stack of gate electrodes in the contact regions. The contact plugs are connected to the gate electrodes. The contact plugs pass through a conductive region of one gate electrode and are electrically connected to the one gate electrode and pass through the insulating region of other gate electrodes in the contact region. The insulating region is disposed outside of the contact holes in a region in which the gate electrodes intersect the contact plugs.

Abstract: A semiconductor device includes a substrate, and a plurality of active regions disposed over the substrate. The plurality of active regions have a first total area. One or more inactive regions are also disposed over the substrate. The one or more inactive regions have a second total area. The second total area is greater than or equal to 1.5 times the first total area. The active regions may be formed in an epitaxial layer formed over the substrate. A plurality of cells of an active device may be disposed in the plurality of active regions. The inactive regions may include only structures that do not dissipate substantial power when the semiconductor device is functioning as it is designed to function.

Abstract: In one example, an electronic device includes a semiconductor sensor device having a cavity extending partially inward from one surface to provide a diaphragm adjacent an opposite surface. A barrier is disposed adjacent to the one surface and extends across the cavity, the barrier has membrane with a barrier body and first barrier strands bounded by the barrier body to define first through-holes. The electronic device further comprises one or more of a protrusion pattern disposed adjacent to the barrier structure, which can include a plurality of protrusion portions separated by a plurality of recess portions; one or more conformal membrane layers disposed over the first barrier strands; or second barrier strands disposed on and at least partially overlapping the first barrier strands. The second barrier strands define second through-holes laterally offset from the first through-holes. Other examples and related methods are also disclosed herein.

Abstract: Provided are a light emitting element and a display device comprising same. The light emitting element comprises: a first conductivity type semiconductor doped with a dopant having a first polarity, a second conductivity type semiconductor doped with a dopant having a second polarity opposite to the first polarity; an active layer between the first conductivity type semiconductor and the second conductivity type semiconductor; and an insulation film which surrounds at least a side surface of the active layer, wherein the insulation film includes an insulation coating film and at least one light conversion particle on at least a portion of the insulation coating film.

Abstract: A method includes: forming a dielectric fin protruding above a substrate; forming a channel layer over an upper surface of the dielectric fin and along first sidewalls of the dielectric fin, the channel layer including a low dimensional material; forming a gate structure over the channel layer; forming metal source/drain regions on opposing sides of the gate structure; forming a channel enhancement layer over the channel layer; and forming a passivation layer over the gate structure, the metal source/drain regions, and the channel enhancement layer.

Abstract: A semiconductor package is disclosed. The package includes a package substrate having top and bottom major package substrate surfaces, the top major package surface including a die region. A die having first and second major die surfaces is attached onto the die region. The second major die surface is attached to the die region. The first major die surface includes a sensor region and a cover adhesive region surrounding the sensor region. The package also includes applying a cover adhesive to the cover adhesive region on the first major die surface. A protective cover with first and second major cover surfaces and side surfaces is attached to the die using the cover adhesive. The second major cover surface contacts the cover adhesive. The protective cover covers the sensor region. The protective cover includes a recessed structure on the second major cover surface.

Abstract: A heat sink having a coolant flow path formed inside through which a coolant flows includes: a heat transfer plate having a first surface on which a semiconductor device is disposed and a second surface; a junction flow path-forming plate having a third surface and a fourth surface; a first partition wall provided in contact with the second surface and the third surface; and first fins provided in contact with the second surface. The coolant flow path includes a first flow path. A plurality of first divided regions separated by the at least one first partition wall are formed in the first flow path. The plurality of first fins are arranged by being spaced side by side in the first divided regions.

Abstract: A semiconductor device includes a substrate having a fin element extending therefrom. In some embodiments, a gate structure is formed over the fin element, where the gate structure includes a dielectric layer on the fin element, a metal capping layer disposed over the dielectric layer, and a metal electrode formed over the metal capping layer. In some cases, first sidewall spacers are formed on opposing sidewalls of the metal capping layer and the metal electrode. In various embodiments, the dielectric layer extends laterally underneath the first sidewall spacers to form a dielectric footing region.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes an isolation layer formed over a substrate, and a plurality of nanostructures formed over the isolation layer. The semiconductor device structure includes a gate structure wrapped around the nanostructures, and an S/D structure wrapped around the nanostructures. The semiconductor device structure also includes a first oxide layer between the substrate and the S/D structure. The first oxide layer and the isolation layer are made of different materials, and the first oxide layer is in direct contact with the isolation layer, and a sidewall surface of the S/D structure is aligned with a sidewall surface of the first oxide layer.