Abstract: An electronic device comprises an array of memory cells comprising a channel material laterally proximate to tiers of alternating conductive materials and dielectric materials. The channel material comprises a heterogeneous semiconductive material varying in composition across a width thereof. Related electronic systems and methods are also disclosed.

Abstract: The invention relates to a method for optically representing electronic semiconductor components 2 on structural units 1 as used for contacting semiconductor components, and to a device which can be used for this purpose. The aim of the invention is to improve navigation on the structural unit 1. Regarding the structural unit 1 provided on a holding surface 19 of a holding device 18, a graphical representation 4 of the structural unit 1 or its semiconductor component 2, or of a section thereof, is provided, and a live image 3 of the semiconductor component 2 is displayed on a first display unit 33. A first graphical representation 4 is also displayed on the first display unit 33 in such a way that elements of the first graphical representation 4, referred to as overlays 5, superimpose the live image 3. The first graphical representation 4 is synchronized with the live image 3 in a computer-aided manner such that at least one overlay 5 corresponds to the associated element of the live image 3.

Abstract: Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a semiconductor device includes NAND memory cells and a first bonding layer including first bonding contacts. The semiconductor device also includes a second semiconductor structure including DRAM cells and a second bonding layer including second bonding contacts. The semiconductor device also includes a third semiconductor structure including a processor, SRAM cells, and a third bonding layer including third bonding contacts. The semiconductor device further includes a first bonding interface between the first and third bonding layers, and a second bonding interface between the second and third bonding layers. The first bonding contacts are in contact with a first set of the third bonding contacts at the first bonding interface. The second bonding contacts are in contact with a second set of the third bonding contacts at the second bonding interface. The first and second bonding interfaces are in a same plane.

Abstract: According to one embodiment, a display device includes a first substrate, a second substrate opposing the first substrate, a wiring substrate connected to the first substrate, a cover member located on an opposite side to the first substrate so as to interpose the second substrate therebetween and a conductive layer maintained at a predetermined potential, and the first substrate includes an extension portion extending further from the second substrate, the wiring substrate is connected to the extension portion, the cover member includes a first surface opposing the extension portion, and the conductive layer overlaps the extension portion in plan view.

Abstract: A semiconductor structure includes a first epitaxial source/drain (S/D) feature disposed over a first semiconductor fin, a second epitaxial S/D feature disposed over a second semiconductor fin and adjacent to the first epitaxial S/D feature, an interlayer dielectric (ILD) layer disposed over the first and the second epitaxial S/D features, a dielectric feature disposed In the ILD layer and contacting the second epitaxial S/D feature, and a conductive feature disposed in the ILD layer and contacting the first epitaxial S/D feature, where a portion of the conductive feature extends to contact the dielectric feature.

Abstract: A Junction Barrier Schottky (JBS) diode includes an N-type epitaxial layer disposed on SiC substrate, P+ wavy regions are disposed in the epitaxial layer adjoining a top planar surface, each of which is separated from an adjacent one of the wavy regions by a Schottky barrier contact region. P+ island regions are disposed in the Schottky barrier contact regions. A top metal layer is disposed along the top planar surface in direct contact with the Schottky barrier contact regions, the P+ wavy regions, and the P+ island regions, the top metal layer comprising the anode of the JBS diode. A bottom metal layer is disposed beneath the SiC substrate. The bottom metal layer comprises the cathode of the JBS diode.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming first nanostructures and second nanostructures over a semiconductor substrate. The method also includes forming a dielectric fin between the first nanostructures and the second nanostructures. The method further includes forming a metal gate stack wrapped around the first nanostructures, the second nanostructures, and the dielectric fin. In addition, the method includes forming an insulating structure penetrating into the metal gate stack and aligned with the dielectric fin.

Abstract: A display device may include a substrate, a first electrode on the substrate, a pixel defining layer exposing the first electrode and covering a side of the first electrode, a second electrode on the first electrode, a hole injection layer between the first electrode and the second electrode and having an upper surface having a side protruding toward the second electrode, a light emitting layer between the hole injection layer and the second electrode and having an upper surface having a side protruding toward the second electrode. A shortest distance between a first fixing point between the side of the upper surface of the hole injection layer and the pixel defining layer and a second fixing point between the side of the upper surface of the light emitting layer and the pixel defining layer is greater than or equal to an insulation breakdown limit distance of the light emitting layer.

Abstract: A silicon carbide semiconductor device includes a substrate, a drift layer disposed above the substrate, a base region disposed above the drift layer, a source region disposed above the base region, a gate trench formed deeper than the base region from a surface of the source region, a gate insulating film covering an inner wall surface of the gate trench, a gate electrode disposed on the gate insulating film, an interlayer insulating film covering the gate electrode and the gate insulating film and having a contact hole, a source electrode brought in ohmic contact with the source region through the contact hole, and a drain electrode disposed to a rear surface of the substrate. The source region has a lower impurity concentration on a side close to the base region than on a surface side brought in ohmic contact with the source region.

Abstract: This application discloses an array substrate and a display panel. The array substrate includes a first metal layer and a second metal layer, and an area of a region overlapping the second metal layer on the first metal layer is less than that of a region not overlapping the second metal layer on the first metal layer.

Abstract: A P-type field effect transistor (PFET) device and a method for fabricating a PFET device using fully depleted silicon on insulator (FDSOI) technology is disclosed. The method includes introducing germanium into the channel layer using ion implantation. This germanium implant increases the axial stress in the channel layer, improving device performance. This implant may be performed at low temperatures to minimize damage to the crystalline structure. Further, rather than using a long duration, high temperature anneal process, the germanium implanted in the channel layer may be annealed using a laser anneal or a rapid temperature anneal. The implanted regions are re-crystallized using the channel layer that is beneath the gate as the seed layer. In some embodiments, an additional oxide spacer is used to further separate the raised source and drain regions from the gate.

Abstract: A Schottky diode includes an upper region having a first doping concentration of a first conductivity type, the upper region disposed above the SiC substrate and extending up to a top planar surface. First and second layers of a second conductivity type are disposed in the upper region adjoining the top planar surface and extending downward to a depth. Each of the first and second layers has a second doping concentration, the depth, first doping concentration, and second doping concentration being selected such that the first and second layers are depleted of carriers at a zero bias condition of the Schottky diode. A top metal layer disposed along the top planar surface in direct contact with the upper region and the first and second layers is the anode, and bottom metal layer disposed beneath the SiC substrate is the cathode, of the Schottky diode.

Abstract: A circuit device having an interlayer dielectric with pillar-type air gaps and a method of forming the circuit device are disclosed. In an exemplary embodiment, the method comprises receiving a substrate and depositing a first layer over the substrate. A copolymer layer that includes a first constituent polymer and a second constituent polymer is formed over the first layer. The first constituent polymer is selectively removed from the copolymer layer. A first region of the first layer corresponding to the selectively removed first constituent polymer is etched. The etching leaves a second region of the first layer underlying the second constituent polymer unetched. A metallization process is performed on the etched substrate, and the first layer is removed from the second region to form an air gap. The method may further comprise depositing a dielectric material within the etched first region.

Abstract: A method for manufacturing a merged PiN Schottky (MPS) diode may include steps of providing a substrate having a first conductivity type; forming an epitaxial layer with the first conductivity type on top of the substrate; forming a plurality of regions with a second conductivity type under a top surface of the epitaxial layer; forming a plasma spreading layer; depositing and patterning a first Ohmic contact metal on the regions with the second conductivity type; depositing a Schottky contact metal on top of the entire epitaxial layer; and forming a second Ohmic contact metal on a backside of the substrate. In another embodiment, the step of forming a plurality of regions with a second conductivity type may include steps of depositing and patterning a mask layer on the epitaxial layer, implanting P-type dopant into the epitaxial layer, and removing the mask layer.

Abstract: An organic electric element, a display panel and a display device including the organic electric element are provided. The organic electric element includes a first electrode; a second electrode; and an organic layer positioned between the first electrode and the second electrode. The organic layer includes a first layer having a first compound and a second compound, and a emitting layer having a third compound. A specific general formula related to energy levels of the component compounds is satisfied so that they may have excellent efficiency or lifespan.

Abstract: An integrated circuit device includes: a fin-type active area including a fin top surface on a top portion and an anti-punch-through recess having a lowermost level lower than a level of the fin top surface; a nanosheet stack facing the fin top surface, the nanosheet stack including a plurality of nanosheets having vertical distances different from each other from the fin top surface; a gate structure surrounding each of the plurality of nanosheets; a source/drain region having a side wall facing at least one of the plurality of nanosheets; and an anti-punch-through semiconductor layer including a first portion filling the anti-punch-through recess, and a second portion being in contact with a side wall of a first nanosheet most adjacent to the fin-type active area among the plurality of nanosheets, the anti-punch-through semiconductor layer including a material different from a material of the source/drain region.

Abstract: The embodiments described herein are directed to a method for reducing fin oxidation during the formation of fin isolation regions. The method includes providing a semiconductor substrate with an n-doped region and a p-doped region formed on a top portion of the semiconductor substrate; epitaxially growing a first layer on the p-doped region; epitaxially growing a second layer different from the first layer on the n-doped region; epitaxially growing a third layer on top surfaces of the first and second layers, where the third layer is thinner than the first and second layers. The method further includes etching the first, second, and third layers to form fin structures on the semiconductor substrate and forming an isolation region between the fin structures.

Abstract: An object of the present invention is to provide a Schottky barrier diode which is less likely to cause dielectric breakdown due to concentration of an electric field. A Schottky barrier diode includes a semiconductor substrate 20 made of gallium oxide, a drift layer 30 made of gallium oxide and provided on the semiconductor substrate 20, an anode electrode 40 brought into Schottky contact with the drift layer 30, and a cathode electrode 50 brought into ohmic contact with the semiconductor substrate 20. The drift layer 30 has an outer peripheral trench 10 formed at a position surrounding the anode electrode 40 in a plan view. An electric field is dispersed by the presence of the outer peripheral trench 10 formed in the drift layer 30. This alleviates concentration of the electric field on the corner of the anode electrode 40, making it unlikely to cause dielectric breakdown.

Abstract: Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a semiconductor device includes NAND memory cells and a first bonding layer including first bonding contacts. The semiconductor device also includes a second semiconductor structure including DRAM cells and a second bonding layer including second bonding contacts. The semiconductor device also includes a third semiconductor structure including a processor, SRAM cells, and a third bonding layer including third bonding contacts. The semiconductor device further includes a first bonding interface between the first and third bonding layers, and a second bonding interface between the second and third bonding layers. The first bonding contacts are in contact with a first set of the third bonding contacts at the first bonding interface. The second bonding contacts are in contact with a second set of the third bonding contacts at the second bonding interface. The first and second bonding interfaces are in a same plane.

Abstract: Methods of forming a self-aligned gate (SAG) and self-aligned source (SAD) device for high Ecrit semiconductors are presented. A dielectric layer is deposited on a high Ecrit substrate. The dielectric layer is etched to form a drift region. A refractory material is deposited on the substrate and dielectric layer. The refractory material is etched to form a gate length. Implant ionization is applied to form high-conductivity and high-critical field strength source with SAG and SAD features. The device is annealed to activate the contact regions. Alternately, a refractory material may be deposited on a high Ecrit substrate. The refractory material is etched to form a channel region. Implant ionization is applied to form high-conductivity and high Ecrit source and drain contact regions with SAG and SAD features. The refractory material is selectively removed to form the gate length and drift regions. The device is annealed to activate the contact regions.