Abstract: The present invention relates to a solid-state imaging device. In a pixel array section in the solid-state imaging device, a vertical signal line is provided right under power supply wiring apart from a floating diffusion region in order to reduce load capacitance of the vertical signal line. Furthermore, the power supply wiring is wired to make a cover rate of each vertical signal line with respect to the power supply wiring nearly uniform. As a result, it is possible to suppress variation of load capacitance of the vertical signal line for each pixel. It becomes possible to suppress deviation in a black level, variation of charge transfer, and variation of settling. It becomes possible to obtain an image with higher quality.

Abstract: An object of the present invention is to provide a Schottky barrier diode less liable to cause dielectric breakdown due to concentration of an electric field. A Schottky barrier diode according to this disclosure includes a semiconductor substrate made of gallium oxide, a drift layer made of gallium oxide and provided on the semiconductor substrate, an anode electrode 40 brought into Schottky contact with the drift layer, a cathode electrode brought into ohmic contact with the semiconductor substrate, an insulating layer provided on the drift layer so as to surround the anode electrode in a plan view, and a semiconductor layer provided on a surface of a part of the drift layer that is positioned between the anode electrode and the insulating layer and on the insulating layer. The semiconductor layer has a conductivity type opposite to that of the drift layer.

Abstract: A method of forming an electrical device that includes forming an amorphous semiconductor material on a metal surface of a memory device, in which the memory device is vertically stacked atop a first transistor. The amorphous semiconductor material is annealed with a laser anneal having a nanosecond duration to convert the amorphous semiconductor material into a crystalline semiconductor material. A second transistor is formed from the semiconductor material. The second transistor vertically stacked on the memory device.

Abstract: A vertical field effect transistor structure having at least two vertically oriented fins extending from a substrate. The vertical field effect transistor structure further includes a first source/drain region disposed in the substrate between the two vertically oriented fins and under each of the fins. The outer ends of the first source/drain region are in contact with outer ends of the fins. A portion of the first source/drain region extends beyond the fins.

Abstract: A high electron mobility transistor (HEMT) includes a substrate, a P-type III-V composition layer, a gate electrode and a carbon containing layer. The P-type III-V composition layer is disposed on the substrate, and the gate electrode is disposed on the P-type III-V composition layer. The carbon containing layer is disposed under the P-type III-V composition layer to function like an out diffusion barrier for preventing from the dopant within the P-type III-V composition layer diffusing into the stacked layers underneath during the annealing process.

Abstract: According to an embodiment of the present invention, a display device includes: a substrate including a through-hole, a peripheral area surrounding the through-hole, a wiring area surrounding the peripheral area, and a display area surrounding the wiring area; a gate insulating layer disposed on the substrate; a gate wire disposed in the wiring area and on the gate insulating layer; an interlayer insulating layer disposed on the gate wire; a data wire disposed in the wiring area and on the interlayer insulating layer; a middle insulating layer disposed on the data wire; and a first main insulating dam disposed in the wiring area and on the middle insulating layer, wherein the first main insulating dam includes an organic material, and wherein a width of a lower surface of the first main insulating dam is narrower than a width of an upper surface of the first main insulating dam.

Abstract: A silicon carbide MOSFET includes first and second source regions respectively disposed in the first and second well regions. Each of the first and second source regions extends up to a top surface of the substrate. First and second channel regions of the respective first and second well regions laterally separate the first and second source regions from a JFET region by a channel length. The first and second channel regions extend up to the top surface. The first and second channel regions are each arranged in a wave-shaped pattern at the top surface of the substrate. The wave-shaped pattern extends in first and second lateral directions. In an on-state, current flows laterally from the first and second source regions to the JFET region, and then in a vertical direction down through an extended drain region to the drain region.

Abstract: An array substrate, including: a base substrate including a display area and a non-display area; a first transistor in the display area; a second transistor in the non-display area; and a substrate electrode, the substrate electrode including: a first substrate electrode between the first transistor and the base substrate; and a second substrate electrode between the second transistor and the base substrate, wherein the first substrate electrode and the second substrate electrode are configured to adjust threshold voltages of the first transistor and the second transistor, respectively, there is an open circuit between the first substrate electrode and the second substrate electrode, the first substrate electrode is supplied with a first adjustment voltage, the second substrate electrode is supplied with a second adjustment voltage, and an absolute value of the first adjustment voltage is different from an absolute value of the second adjustment voltage.

Abstract: A semiconductor device includes a substrate having first fin and a second fin spaced apart and extending lengthwise in parallel. A fin remnant is disposed between the first fin and the second fin, extends lengthwise in parallel with the first and second fins, and has a height lower than a height of each of the first fin and the second fin. A first field insulation layer is disposed between a sidewall of the first fin and a first sidewall of the fin remnant and a second field insulating layer is disposed on a sidewall of the second fin. A blocking liner conforms to a sidewall and a bottom surface of a trench bounded by a second sidewall of the fin remnant and a sidewall of the second field insulating layer. A trench insulation layer is disposed on the blocking liner in the trench.

Abstract: The present application provides a laterally diffused metal oxide semiconductor (LDMOS) transistor and a manufacturing method thereof. The transistor comprising: a semiconductor substrate having a doping region, wherein the doping region comprises a first well region and a second well region with opposite doping types; a source region, a drain region, a shallow trench isolation (STI) structure comprising a laminated structure having an alternate layers of insulating material and ferroelectric material, a gate, a contact hole, and a metal layer. The LDMOS transistor simultaneously increases breakdown voltage (BV) and reduces on-resistance (Ron).

Abstract: A package structure and method of forming the same are provided. The package structure includes a die, a via, an encapsulant, an adhesion promoter layer, and a polymer layer. The via is laterally aside the die. The encapsulant laterally encapsulates the die and the via. The adhesion promoter layer is sandwiched between the via and the encapsulant. The encapsulant comprises a portion aside the via and under the adhesion promoter layer, and the portion of the encapsulant is sandwiched between the adhesion promoter layer and the polymer layer.

Abstract: A high efficiency satellite transmitter comprises an RF amplifier chip in thermal contact with a radiant cooling element via a heat conducting element. The RF amplifier chip comprises an active layer disposed on a high thermal conductivity substrate having a thermal conductivity greater than about 1000 W/mK, maximizing heat conduction out of the RF amplifier chip and ultimately into outer space when the chip is operating within a satellite under normal transmission conditions. In one embodiment, the active layer comprises materials selected from the group consisting of GaN, InGaN, AlGaN, and InGaAlN alloys. In one embodiment, the high thermal conductivity substrate comprises synthetic diamond.

Abstract: A power semiconductor device includes an active cell region with a drift region of a first conductivity type, a plurality of IGBT cells arranged within the active cell region, each of the IGBT cells includes at least one trench that extends into the drift, an edge termination region surrounding the active cell region, a transition region arranged between the active cell region and the edge termination region, at least some of the IGBT cells are arranged within or extend into the transition region, a barrier region of a second conductivity type, the barrier region is arranged within the active cell region and in contact with at least some of the trenches of the IGBT cells and does not extend into the transition region, and a first load terminal and a second load terminal, the power semiconductor device is configured to conduct a load current along a vertical direction between.

Abstract: A display device includes pixels, scan lines, and data lines. A first driving gate electrode is disposed at a first pixel of the display device. A second driving gate electrode is disposed at a second pixel of the display device. A first driving voltage line includes a first extending part that overlaps a first driving gate electrode. A second driving voltage line includes a second extending part that overlaps a second driving gate electrode. A first pixel electrode of the first pixel overlaps the second driving gate electrode. The second extending part includes a first recess portion. A center line of the first recess portion is offset in a direction away from the first pixel electrode with respect to a center line of the second driving gate electrode.

Abstract: A semiconductor device includes a substrate, a tunneling oxide layer, a floating gate, an isolation layer and a control gate. The tunneling oxide layer is over the substrate. The floating gate is over the tunneling oxide layer. The isolation layer covers a top of the floating gate and peripherally encloses the tunneling oxide layer and the floating gate. The control gate is over a top of the isolation layer.

Abstract: A vertical field-effect transistor (FET), comprising a first doped region of a first material, said first doped region having a first doping and being formed on a surface of a substrate, a second doped region of said first material, said second doped region having a second doping and being formed on the first doped region, and a third doped region of said first material, said third doped region having a third doping and being formed on the second doped region, wherein the first doped region has a first width along a first direction parallel to said surface of the substrate, the second doped region has a second width along said first direction, the third doped region has a third width along said first direction, the second width being smaller than the first and third widths.

Abstract: An electroluminescent display substrate and a manufacturing method thereof, and an electroluminescent display apparatus, are disclosed. The display substrate includes: a base substrate; an electroluminescent element on the base substrate, the electroluminescent element including a first electrode layer, a light-emitting layer and a second electrode layer which are disposed in sequence on the base substrate; an encapsulating layer disposed on the base substrate and covering the electroluminescent element; an aperture, the aperture at least penetrating the encapsulating layer; and at least one eave structure on the base substrate, the at least one eave structure surrounding the aperture, and being located between the aperture and the electroluminescent element. Each eave structure includes at least one undercut at one end of the eave structure close to the base substrate, and at least one of the light-emitting layer and the second electrode layer is disconnected at the at least one undercut.

Abstract: A method of manufacturing a semiconductor light emitting device, the method including forming a first conductivity-type semiconductor layer on a substrate; forming an active layer on the first conductivity-type semiconductor layer; forming a mask layer having an opening on the active layer; growing a second conductivity-type semiconductor layer through the opening; removing the mask layer; removing a portion of the active layer and a portion of the first conductivity-type semiconductor layer that do not overlap the second conductivity-type semiconductor layer; and removing a portion of the first conductivity-type semiconductor layer to expose the substrate.

Abstract: Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a method for forming a semiconductor device is disclosed. First semiconductor structures are formed on a first wafer. At least one of the first semiconductor structures includes a processor, an array of SRAM cells, and a first bonding layer including first bonding contacts. Second semiconductor structures are formed on a second wafer. At least one of the second semiconductor structures includes an array of DRAM cells and a second bonding layer including second bonding contacts. The first wafer and the second wafer in are bonded in a face-to-face manner, such that the at least one of the first semiconductor structures is bonded to the at least one of the second semiconductor structures. The first bonding contacts of the first semiconductor structure are in contact with the second bonding contacts of the second semiconductor structure at a bonding interface. The bonded first and second wafers are diced into dies.

Abstract: A semiconductor device includes a substrate, a semiconductor channel layer, a semiconductor barrier layer, a gate electrode, a first electrode, and a dielectric layer. The semiconductor channel layer is disposed on the substrate, and the semiconductor barrier layer is disposed on the semiconductor channel layer. The gate electrode is disposed on the semiconductor barrier layer. The first electrode is disposed at one side of the gate electrode. The first electrode includes a body portion and a vertical extension portion. The body portion is electrically connected to the semiconductor barrier layer, and the bottom surface of the vertical extension portion is lower than the top surface of the semiconductor channel layer. The dielectric layer is disposed between the vertical extension portion and the semiconductor channel layer.