Abstract: A semiconductor device includes a source electrode and a drain electrode located over a surface of a semiconductor layer including an electron transit layer and an electron supply layer. A gate electrode is located between the source electrode and the drain electrode. A first diamond layer is located between the source electrode and the drain electrode over the surface with an insulating film therebetween. A second diamond layer is located directly on the surface between the gate electrode and the drain electrode. Of heat generated by the semiconductor layer of the semiconductor device in operation, heat on the side of the electrode on which a relatively strong electric field is applied is efficiently transferred to the second diamond layer. The semiconductor device achieves an excellent heat dissipation property from the semiconductor layer and effectively suppresses overheating and a failure and degradation of the characteristics due to the overheating.

Abstract: A microelectronic unit may include an epitaxial silicon layer having a source and a drain, a buried oxide layer beneath the epitaxial silicon layer, an ohmic contact extending through the buried oxide layer, a dielectric layer beneath the buried oxide layer, and a conductive element extending through the dielectric layer. The source and the drain may be doped portions of the epitaxial silicon layer. The ohmic contact may be coupled to a lower surface of one of the source or the drain. The conductive element may be coupled to a lower surface of the ohmic contact. A portion of the conductive element may be exposed at the second dielectric surface of the dielectric layer. The second dielectric surface may be directly bonded to an external component to form a microelectronic assembly.

Abstract: A filter-based color imaging array that resolves N different colors detects only 1/Nth of the incoming light. In the thermal infrared wavelength range, filtering loss is exacerbated by the lower sensor detectivity at infrared wavelengths than at visible wavelengths. To avoid loss due to filtering, most spectral imagers use bulky optics, such as diffraction gratings or Fourier transform interferometers, to resolve different colors. Fortunately, it is possible to avoid filtering loss without bulky optics: detect light with interleaved arrays of sub-wavelength-spaced antennas tuned to different wavelengths. An optically sensitive element inside each antenna absorbs light at the antenna's resonant wavelength. Metallic slot antennas offer high efficiency, intrinsic unidirectionality, and lower cross-talk than dipole or bowtie antennas. Graphene serves at the optically active material inside each antenna because its 2D nature makes it easily adaptable to this imager architecture.

Abstract: In a method of manufacturing a semiconductor device, a fin structure having a bottom portion, an intermediate portion disposed over the bottom portion and an upper portion disposed over the intermediate portion is formed. The intermediate portion is removed at a source/drain region of the fin structure, thereby forming a space between the bottom portion and the upper portion. An insulating layer is formed in the space. A source/drain contact layer is formed over the upper portion. The source/drain contact layer is separated by the insulating layer from the bottom portion of the fin structure.

Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); a middle low-k (LK) dielectric layer over the lower ESL; a supporting layer over the middle LK dielectric layer; an upper LK dielectric layer over the supporting layer; an upper conductive feature in the upper LK dielectric layer, wherein the upper conductive feature is through the supporting layer; a gap along an interface of the upper conductive feature and the upper LK dielectric layer; and an upper ESL over the upper LK dielectric layer, the upper conductive feature, and the gap.

Abstract: Disclosed are a memory device including a vertical stack structure and a method of manufacturing the memory device. The memory device includes an insulating structure having a shape including a first surface and a protrusion portion protruding in a first direction from the first surface, a recording material layer covering the protrusion portion along a protruding shape of the protrusion portion and extending to the first surface on the insulating structure a channel layer on the recording material layer along a surface of the recording material layer, a gate insulating layer on the channel layer, and a gate electrode formed at a location on the gate insulating layer to face a second surface which is a protruding upper surface of the protrusion portion, wherein a void exists between the gate electrode and the insulating structure, defined by the insulating structure and the recording material layer.

Abstract: A semiconductor device is described. The semiconductor device includes a substrate and a metal layer disposed on the substrate. A seed layer is formed on the metal layer. A ferroelectric gate layer is formed on the seed layer. A channel layer is formed over the ferroelectric gate layer. The seed layer is arranged to increase the orthorhombic phase fraction of the ferroelectric gate layer.

Abstract: Methods for forming a coating over a surface are disclosed. A method includes directing a first source of barrier film material toward a substrate in a first direction at an angle ? relative to the substrate, wherein ? is greater than about 0° and less than about 85°. Additionally, a method of depositing a barrier film over a substrate includes directing a plurality of N sources of barrier film material toward a substrate, each source being directed at an angle ?N relative to the substrate, wherein for each ?N, ? is greater than about 0° and less than about 180°. For at least a first of the ?N, ?N is greater than about 0° and less than about 85°, and for at least a second of the ?N, ?N is greater than about 95° and less than about 180°.

Abstract: A light-emitting device includes a first electrode; a second electrode facing the first electrode; m emission units between the first electrode and the second electrode; and m?1 charge-generating unit(s) between adjacent ones of the emission units, where m is a natural number of 2 or more. The emission units each include an emission layer. At least one of the charge-generating unit(s) includes an n-type charge-generating layer and a p-type charge-generating layer; and the n-type charge-generating layer includes a first material and a second material. The first material includes an organic electron transport compound; and the second material includes at least one selected from an alkali metal, an alkali metal alloy, an alkaline earth metal, an alkaline earth metal alloy, a lanthanide metal, and a lanthanide metal alloy. The light-emitting device may have improved hole and electron balance, a decreased driving voltage, and excellent efficiency and/or lifespan characteristics.

Abstract: By widening a terrace on a crystal surface on a bottom face of a recess by step flow caused by heating, a flat face is formed on the bottom face of the recess, a two-dimensional material layer made of a two-dimensional material is formed on the formed flat face, and then a device made of the two-dimensional material layer is produced.

Abstract: Describe is a resonator that uses anti-ferroelectric (AFE) materials in the gate of a transistor as a dielectric. The use of AFE increases the strain/stress generated in the gate of the FinFET. Along with the usual capacitive drive, which is boosted with the increased polarization, additional current drive is also achieved from the piezoelectric response generated to due to AFE material. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using the metal line above and vias' to body and dummy fins on the side. As such, a Bragg reflector is formed above or below the AFE based transistor. Increased drive signal from the AFE results in larger output signal and larger bandwidth.

Abstract: A first integrated circuit chip is assembled to a second integrated circuit chip with a back-to-back surface relationship. The back surfaces of the integrated circuit chips are attached to each other using one or more of an adhesive, solder or molecular bonding. The back surface of at least one the integrated circuit chips is processed to include at least one of a trench, a cavity or a saw cut.

Abstract: A semiconductor package structure includes a plurality of first dies spaced from each other, a molding layer between the first dies, a second die over the plurality of first dies and the molding layer, and an adhesive layer between the plurality of first dies and the second die, and between the molding layer and the second die. A first interface between the adhesive layer and the molding layer and a second interface between the adhesive layer and the plurality of first dies are at different levels.

Abstract: The disclosure describes various aspects of monolithic integration of different light emitting structures on a same substrate. In an aspect, a device for light generation is described having a substrate with one or more buffer layers made a material that includes GaN. The device also includes light emitting structures, which are epitaxially grown on a same surface of a top buffer layer of the substrate, where each light emitting structure has an active area parallel to the surface and laterally terminated, and where the active area of different light emitting structures is configured to directly generate a different color of light. The device also includes a p-doped layer disposed over the active area of each light emitting structure and made of a p-doped material that includes GaN. The device may be part of a light field display and may be connected to a backplane of the light field display.

Abstract: The present technology provides a semiconductor device. The semiconductor device includes a stack including insulating patterns and conductive patterns stacked alternately with each other, a channel layer including a first channel portion protruding out of the stack and a second channel portion in the stack, and passing through the stack, and a conductive line surrounding the first channel portion, and the first channel portion includes metal silicide.

Abstract: Describe is a resonator that uses ferroelectric (FE) materials in the gate of a transistor as a dielectric. The use of FE increases the strain/stress generated in the gate of the FinFET. Along with the usual capacitive drive, which is boosted with the increased polarization, FE material expands or contacts depending on the applied electric field on the gate of the transistor. As such, acoustic waves are generated by switching polarization of the FE materials. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using the metal line above and vias' to body and dummy fins on the side. As such, a Bragg reflector is formed above the FE based transistor.

Abstract: A display panel, a manufacturing method thereof, and an electronic device are provided. The panel includes a thickness of a first setting film layer of each of the colored organic light-emitting units of each color is an odd multiple of a half wavelength of the light of the corresponding color, and/or a thickness of a second setting film layer of each of the colored organic light-emitting units is an even multiple of the half wavelength of the light of the corresponding color, wherein the second setting film layer is close to a light-emitting side of the display panel, and the first setting film layer is disposed below the second setting film layer.

Abstract: A Schottky diode includes an upper region having a first doping concentration of a first conductivity type, the upper region disposed above the SiC substrate and extending up to a top planar surface. First and second layers of a second conductivity type are disposed in the upper region adjoining the top planar surface and extending downward to a depth. Each of the first and second layers has a second doping concentration, the depth, first doping concentration, and second doping concentration being selected such that the first and second layers are depleted of carriers at a zero bias condition of the Schottky diode. A top metal layer disposed along the top planar surface in direct contact with the upper region and the first and second layers is the anode, and bottom metal layer disposed beneath the SiC substrate is the cathode, of the Schottky diode.

Abstract: In a method of manufacturing a negative capacitance structure, a dielectric layer is formed over a substrate. A first metallic layer is formed over the dielectric layer. After the first metallic layer is formed, an annealing operation is performed, followed by a cooling operation. A second metallic layer is formed. After the cooling operation, the dielectric layer becomes a ferroelectric dielectric layer including an orthorhombic crystal phase.

Abstract: A Schottky barrier diode includes a semiconductor substrate made of gallium oxide, a drift layer made of gallium oxide and provided on the semiconductor substrate, an anode electrode brought into Schottky contact with the drift layer, and a cathode electrode brought into ohmic contact with the semiconductor substrate. The drift layer has a plurality of trenches formed in a position overlapping the anode electrode in a plan view. Among the plurality of trenches, a trench positioned at the end portion has a selectively increased width. Thus, the curvature radius of the bottom portion of the trench is increased, or an edge part constituted by the bottom portion as viewed in a cross section is divided into two parts. As a result, an electric field to be applied to the bottom portion of the trench positioned at the end portion is mitigated, making dielectric breakdown less likely to occur.