Abstract: An OLED display substrate, a manufacturing method thereof, and a display device are provided. The manufacturing method includes forming a PIN photodiode on a base substrate, forming an insulative protection layer covering the PIN photodiode, and forming an oxide TFT. The PIN photodiode is formed prior to the formation of an active layer of the oxide TFT, and the insulative protection layer covering the PIN photodiode is formed prior to the formation of a source electrode and a drain electrode of the oxide TFT.

Abstract: A first integrated circuit chip is assembled to a second integrated circuit chip with a back-to-back surface relationship. The back surfaces of the integrated circuit chips are attached to each other using one or more of an adhesive, solder or molecular bonding. The back surface of at least one the integrated circuit chips is processed to include at least one of a trench, a cavity or a saw cut.

Abstract: Variable resistance memory devices are provided. A variable resistance memory device includes conductive lines and a memory cell including a variable resistance element on one of the conductive lines. The variable resistance memory device includes a first insulating region between the conductive lines. Moreover, the variable resistance memory device includes a second insulating region on the first insulating region between the conductive lines. Methods of forming variable resistance memory devices are also provided.

Abstract: A first wafer including a first substrate, first semiconductor devices overlying the first substrate, and first dielectric material layers overlying the first semiconductor devices is provided. A sacrificial material layer is formed over a top surface of a second wafer including a second substrate. Second semiconductor devices and second dielectric material layers are formed over a top surface of the sacrificial material layer. The second wafer is attached to the first wafer such that the second dielectric material layers face the first dielectric material layers. A plurality of voids is formed through the second substrate. The sacrificial material layer is removed by providing an etchant that etches a material of the sacrificial material layer through the plurality of voids. The substrate is detached from a bonded assembly including the first wafer, the second semiconductor devices, and the second dielectric material layers upon removal of the sacrificial material layer.

Abstract: A semiconductor device including: a substrate; a via which penetrates the substrate; a via insulating film formed along an inner wall of the via; and a core plug which fills the via, wherein a residual stress of the via insulating film is 60 MPa to ?100 MPa.

Abstract: Disclosed herein is a light-emitting device package a body including a cavity; a first electrode disposed on a bottom surface of the cavity; a plurality of second electrodes disposed on the bottom surface of the cavity and configured to surround the first electrode; a first light-emitting device disposed on the first electrode; a second light-emitting device disposed on one among the plurality of second electrodes; and a light-transmitting member disposed on the body, wherein the bottom surface of the cavity includes a first edge extending in a first direction, a second edge configured to face the first edge and extend in the first direction, a third edge configured to extend in a second direction perpendicular to the first direction and connected to the first and second edges, and a fourth edge configured to face the third edge, extend in the second direction, and connected to the first and second edges; the first electrode includes an arrangement portion, on which the first light-emitting device is disposed

Abstract: A transistor including an oxide semiconductor layer can have stable electrical characteristics. In addition, a highly reliable semiconductor device including the transistor is provided. A semiconductor device includes a multi-layer film including an oxide layer and an oxide semiconductor layer, a gate insulating film in contact with the multi-layer film, and a gate electrode overlapping with the multi-layer film with the gate insulating film provided therebetween. In the semiconductor device, the oxide semiconductor layer contains indium, the oxide semiconductor layer is in contact with the oxide layer, and the oxide layer contains indium and has a larger energy gap than the oxide semiconductor layer.

Abstract: The disclosure is directed to techniques in preparing an atom probe tomography (“APT”) specimen. A structure in a semiconductor device is identified as including a test object for an APT procedure. A target region is identified in the structure where an APT specimen will be obtained. The target region is analyzed to determine whether a challenging component feature exists therein. A challenging component may include a hard-to-evaporate material, a hollow region, or a material unidentifiable with respect to the test object, or other structural features that pose a challenge to a successful APT analysis. If it is determined that a challenging component exists in the target region, the challenging component is replaced with a more suitable material before the APT specimen is prepared.

Abstract: The present invention discloses a SONOS memory in which two storage gates in a storage unit are self-aligned on the side of a selection gate, states of information stored in two storage gates in the same storage unit being opposite, the storage information of the storage unit being judged by comparing the magnitude of reading currents corresponding to two storage gates. The present invention further discloses a method for manufacturing a SONOS memory. The present invention can improve the reliability of the product and reduce the area of the device at the same time.

Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); a middle low-k (LK) dielectric layer over the lower ESL; a supporting layer over the middle LK dielectric layer; an upper LK dielectric layer over the supporting layer; an upper conductive feature in the upper LK dielectric layer, wherein the upper conductive feature is through the supporting layer; a gap along an interface of the upper conductive feature and the upper LK dielectric layer; and an upper ESL over the upper LK dielectric layer, the upper conductive feature, and the gap.

Abstract: An optical semiconductor element includes a semiconductor substrate, a first laminated structure provided on a front surface of the semiconductor substrate, and a second laminated structure provided on the front surface of the semiconductor substrate, the first laminated structure includes a first quantum cascade region, the second laminated structure includes a dummy region having the same layer structure as the first quantum cascade region, a second quantum cascade region provided on the front surface of the semiconductor substrate via the dummy region, and one of the first quantum cascade region and the second quantum cascade region is a quantum cascade laser, and the other of the first quantum cascade region and the second quantum cascade region is a quantum cascade detector.

Abstract: The present invention provides a GaN-based microwave power device with a large gate width and manufacturing method thereof. The device includes an AlGaN/GaN heterojunction epitaxial layer, a first dielectric layer overlying the AlGaN/GaN heterojunction epitaxial layer, a strip-like source electrode, a drain electrode distributed in a shape of a fishbone, an annular gate electrode, a second dielectric layer separating upper and lower electrodes, and an interconnect metal electrode pad. The GaN-based microwave power device with the large gate width prepared according to the present invention, has a small phase shift of the signals, a small parasitic capacitance of the device, a high signal gain, high power added efficiency and a high output power. At the same time, the manufacturing process of the device is simple, the chip area is saved, and the device has a good repeatability.

Abstract: Embodiments of the disclosure provide methods and apparatus for fabricating magnetic tunnel junction (MTJ) structures on a substrate in for hybrid (or called integrated) spin-orbit-torque magnetic spin-transfer-torque magnetic random access memory (SOT-STT MRAM) applications. In one embodiment, the method includes one or more magnetic tunnel junction structures disposed on a substrate, the magnetic tunnel junction structure comprising a first ferromagnetic layer and a second ferromagnetic layer sandwiching a tunneling barrier layer, a spin orbit torque (SOT) layer disposed on the magnetic tunnel junction structure, and a back end structure disposed on the spin orbit torque (SOT) layer.

Abstract: A middle-of-line (MOL) structure is provided and includes device and resistive memory (RM) regions. The device region includes trench silicide (TS) metallization, a first interlayer dielectric (ILD) portion and a first dielectric cap portion disposed over the TS metallization and the first ILD portion. The RM region includes a second dielectric cap portion, a second ILD portion and an RM resistor interposed between the second dielectric cap portion and the second ILD portion.

Abstract: In SiC-MOSFETs including Schottky diodes, passage of a bipolar current to a well region in an edge portion of an active region cannot be sufficiently reduced, which may reduce the reliability of elements. In a SiC-MOSFET including Schottky diodes, the Schottky diodes formed in a terminal region are made higher in density in a plane direction than those formed in the active region or intervals between the Schottky diodes in the plane direction are shortened, without an ohmic connection between the well and the source in the terminal region.

Abstract: An example device in accordance with an aspect of the present disclosure includes an active oxide layer to form and dissipate a conductive bridge. The conductive bridge is to dissipate spontaneously within a relaxation time to enable the memory device to self-refresh according to volatile behavior in response to the input voltage being below a threshold corresponding to disregarding sneak current and noise of a crossbar array in which the memory device is to operate. The conductive bridge is to persist beyond the relaxation time to enable the memory device to retain programming for neuromorphic computing training according to non-volatile behavior of the memory device in response to the input voltage not being below the threshold.

Abstract: A light emitting device includes a substrate, a plurality of light emitting elements disposed in a light-emitting region on the substrate, at least one first wiring part surrounding the light-emitting region, at least one second wiring part, together with the at least one first wiring part, demarcating the light-emitting region into a plurality of demarcated regions, a first wall formed along and covering the at least one first wiring part to surround the light-emitting region, at least one second wall formed along and covering corresponding one or more of the at least one second wiring part, and a light-transmissive member containing a wavelength converting material, covering an entire light-emitting region.

Abstract: An image sensor may include a pixel array including a plurality of pixel blocks operable to convert light into electrical signals. Each of the plurality of pixel blocks may include a first light receiving circuit including a plurality of unit pixels that share a first floating diffusion; a second light receiving circuit arranged adjacent to the first light receiving circuit in a second direction, and including a plurality of unit pixels that share a second floating diffusion; a first driving circuit positioned between the first light receiving circuit and the second light receiving circuit; a second driving circuit positioned adjacent to the other side facing away from one side of the first light receiving circuit or the second light receiving circuit, which is adjacent to the first driving circuit; and a third driving circuit positioned adjacent to the first driving circuit or the second driving circuit.

Abstract: A semiconductor die package includes a semiconductor die, a film for improving die warpage bonded to a first face of the semiconductor die, a plurality of electrically conductive bumps formed on a second face of the semiconductor die, a substrate onto which the electrically conductive bumps of the second face of the semiconductor die are bonded to electrically connect the semiconductor die and the substrate, and a mold compound applied these components to form an exposed surface of the semiconductor die package that is coplanar with an exposed surface of the film.

Abstract: A display device includes a flexible substrate including a display area and a non-display area. The substrate has a first surface and a second surface opposite to the first surface. A first protection film is disposed on the first surface of the substrate. The first protection film is disposed over the display area of the substrate. A second protection film is disposed on the first surface of the substrate. The second protection film is disposed over the non-display area of the substrate. A light transmittance of the first protection film is higher than that of the second protection film.