Abstract: A semiconductor package structure includes a substrate; a first die on the substrate, wherein an active surface of the first die is facing away from the substrate; a second die on the active surface of the first die, electrically connected to the first die through a plurality of conductive terminals; and a sealing structure on the active surface of the first die, surrounding the plurality of conductive terminals and abutting the second die thereby forming a cavity between the first die and the second die. A method for manufacturing the semiconductor package structure is also provided.

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate and forming a bottom layer, a middle layer, and a top layer on the substrate. The method also includes patterning the top layer to form a patterned top layer and patterning the middle layer by a patterning process including a plasma process to form a patterned middle layer. The plasma process is performed by using a mixed gas including hydrogen gas (H2). The method further includes controlling a flow rate of the hydrogen gas (H2) to improve an etching selectivity of the middle layer to the top layer, and the patterned middle layer includes a first portion and a second portion parallel to the first portion, and a pitch is between the first portion and the second portion.

Abstract: A method includes receiving a first design for conductive bumps on a first surface of an interposer, the conductive bumps in the first design having a same cross-section area; grouping the conductive bumps in the first design into a first group of conductive bumps in a first region of the first surface and a second group of conductive bumps in a second region of the first surface, where a bump pattern density of the second region is lower than that of the first region; forming a second design by modifying the first design, where modifying the first design includes modifying a cross-section area of the second group of conductive bumps in the second region; and forming the conductive bumps on the first surface of the interposer in accordance with the second design, where after being formed, the first group of conductive bumps and the second group of conductive bumps have different cross-section areas.

Abstract: A silicon carbide semiconductor device includes a substrate, a drift layer disposed above the substrate, a base region disposed above the drift layer, a source region disposed above the base region, a gate trench formed deeper than the base region from a surface of the source region, a gate insulating film covering an inner wall surface of the gate trench, a gate electrode disposed on the gate insulating film, an interlayer insulating film covering the gate electrode and the gate insulating film and having a contact hole, a source electrode brought in ohmic contact with the source region through the contact hole, and a drain electrode disposed to a rear surface of the substrate. The source region has a lower impurity concentration on a side close to the base region than on a surface side brought in ohmic contact with the source region.

Abstract: Provided is a solid-state imaging device including a first substrate that includes a pixel unit, a first semiconductor substrate, and a first multi-layered wiring layer stacked, a second substrate that includes circuit, a second semiconductor substrate, and a second multi-layered wiring layer stacked, the circuit having a predetermined function, a third substrate that includes a circuit, a third semiconductor substrate, and a third multi-layered wiring layer. The first substrate and the second substrate being bonded together such that the first multi-layered wiring layer is opposite to the second semiconductor substrate, and a first coupling structure for electrically coupling the circuit of the first substrate with the circuit of the second substrate, the first coupling structure is on bonding surfaces of the first substrate and the second substrate, and includes an electrode junction structure in which electrodes on the respective bonding surfaces are joined to each other in direct contact.

Abstract: A gate-all-around structure including a first transistor is provided. The first transistor includes a semiconductor substrate having a top surface, and a first nanostructure over the top surface of the semiconductor substrate and between a first source and a first drain. The first transistor also includes a first gate structure around the first nanostructure, and an inner spacer between the first gate structure and the first source, wherein an interface between the inner spacer and the first gate structure is non-flat. The first transistor includes an isolation layer between the top surface of the semiconductor substrate and the first source and the first drain.

Abstract: A semiconductor package and a manufacturing method are provided. The semiconductor package includes a semiconductor die, an encapsulant and a through encapsulant via. The semiconductor die includes a semiconductor substrate, an interconnection layer and a through semiconductor via. The semiconductor substrate has an active surface and a back surface opposite to the active surface. The interconnection layer is disposed over the active surface of the semiconductor substrate. The through semiconductor via penetrates through the semiconductor substrate from the back surface of the semiconductor substrate to the active surface of the semiconductor substrate. The semiconductor die is encapsulated by the encapsulant. The through encapsulant via penetrates through the encapsulant.

Abstract: Embodiments of the present application provide a package structure and a display device including package structure. The package structure includes a graphene layer and a graphene oxide layer which are disposed in a stack. In the package structure according to the embodiments of the present application, the graphene oxide layer is stacked on the graphene layer.

Abstract: A method for forming a semiconductor package is disclosed. The method includes providing a package substrate having top and bottom major package substrate surfaces, the top major package surface including a die attach region. A die having first and second major die surfaces is attached onto the die attach region. The second major die surface is attached to the die attach region. The first major die surface includes an die active region and a cover adhesive region surrounding the die active region. The method also includes applying a cover adhesive to the cover adhesive region on the first major die surface. A protective cover with first and second major cover surfaces and side surfaces is attached to the die using the cover adhesive. The second major cover surface contacts the cover adhesive. The protective cover covers the die active region. The protective cover includes a discontinuity on at least one of the side surfaces.

Abstract: A method includes forming a device structure, the method including forming a first redistribution structure over and electrically connected to a semiconductor device, forming a molding material surrounding the first redistribution structure and the semiconductor device, forming a second redistribution structure over the molding material and the first redistribution structure, the second redistribution structure electrically connected to the first redistribution structure, attaching an interconnect structure to the second redistribution structure, the interconnect structure including a core substrate, the interconnect structure electrically connected to the second redistribution structure, forming an underfill material on sidewalls of the interconnect structure and between the second redistribution structure and the interconnect structure.

Abstract: A method for manufacturing a semiconductor device and a semiconductor device, the method including forming an active pattern on a substrate such that the active pattern includes sacrificial patterns and semiconductor patterns alternately and repeatedly stacked on the substrate; and forming first spacer patterns at both sides of each of the sacrificial patterns by performing an oxidation process, wherein the first spacer patterns correspond to oxidized portions of each of the sacrificial patterns, wherein the sacrificial patterns include a first semiconductor material containing impurities, wherein the semiconductor patterns include a second semiconductor material different from the first semiconductor material, and wherein the impurities include an element different from semiconductor elements of the first semiconductor material and the second semiconductor material.

Abstract: The present disclosure relates to a semiconductor structure and a method of manufacturing the semiconductor structure. The semiconductor structure includes a substrate including a first surface and a conductive trace extending over the substrate; a die disposed over the first surface of the substrate; a molding disposed over the first surface of the substrate and covering the die; and a metallic layer surrounding the molding and the substrate, wherein the metallic layer is electrically connected to at least a portion of the conductive trace exposed through the substrate.

Abstract: Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a semiconductor device includes NAND memory cells and a first bonding layer including first bonding contacts. The semiconductor device also includes a second semiconductor structure including DRAM cells and a second bonding layer including second bonding contacts. The semiconductor device also includes a third semiconductor structure including a processor, SRAM cells, and a third bonding layer including third bonding contacts. The semiconductor device further includes a first bonding interface between the first and third bonding layers, and a second bonding interface between the second and third bonding layers. The first bonding contacts are in contact with a first set of the third bonding contacts at the first bonding interface. The second bonding contacts are in contact with a second set of the third bonding contacts at the second bonding interface. The first and second bonding interfaces are in a same plane.

Abstract: A silicon carbide MOSFET includes a plurality of first and second trenches each of which extends a predetermined vertical distance from the top of a source down through a body region and into a current spreading layer (CSL). An insulated gate member is disposed in each first trench. The first trenches are each arranged in a wave-shaped pattern that extends in first and second lateral directions. Each of the second trenches is disposed between a pair of adjacent first trenches in the first lateral direction. A shielding region extends vertically from the bottom of each of the second trenches down into a drift region. A top metal layer fill each of the second trenches and electrically contacts the source region, the body region, the CSL, and the shielding region. A bottom metal layer electrically contacts the drain region.

Abstract: A method of manufacturing a capacitor having an MIM structure includes forming a dielectric by laminating a plurality of times on an upper surface of a lower electrode, and forming an upper electrode on an upper surface of the dielectric. The forming of the dielectric includes forming a first dielectric layer on the upper surface of the lower electrode, cleaning an upper surface of the first dielectric layer by at least one of jet cleaning and dual fluid cleaning, and forming a second dielectric layer on the cleaned upper surface of the first dielectric layer.

Abstract: A semiconductor transistor device includes a GaN transistor including a drain, a gate, and a source, the GaN transistor having a driving voltage applied across the gate and the source and configured to switch between an on-voltage associated with an on-state of the GaN transistor and an off-voltage associated with an off-state of the GaN transistor. The semiconductor transistor device further includes a variable gate-source resistor connected between the gate and the source and having a variable resistance that varies in response to changes in the driving voltage when switching between the on-state and the off-state of the GaN transistor.

Abstract: According to one embodiment, a semiconductor memory device includes a substrate, semiconductor pillars, first electrode films, a second electrode film, a first insulating film, a second insulating film, and a contact. The semiconductor pillars are provided on the substrate, extend in a first direction crossing an upper surface of the substrate, and are arranged along second and third directions being parallel to the upper surface and crossing each other. The first electrode films extend in the third direction. The second electrode film is provided between the semiconductor pillars and the first electrode films. The first insulating film is provided between the semiconductor pillars and the second electrode film. The second insulating film is provided between the second electrode film and the first electrode films. The contact is provided at a position on the third direction of the semiconductor pillars and is connected to the first electrode films.

Abstract: A semiconductor device includes a semiconductor substrate having first and second semiconductor fins, an insulating layer on the semiconductor substrate, the insulating layer including a first recess exposing an upper portion of the first semiconductor fin and a second recess exposing an upper portion of the second semiconductor fin, a gate dielectric layer on the first and second recesses and the exposed upper portions of the first and second semiconductor fins, a first work function adjustment layer on the gate dielectric layer, a functional layer on the first function adjustment layer, and first and second gates on portions of the functional layer of the respective first and second semiconductor fins. The surface area of a lateral opening of the first recess is larger than the surface area of a lateral opening of the second recess.

Abstract: Disclosed is an organic light emitting diode display including an organic light emitting display panel configured to display an image, and a lower passivation film attached to a bottom of the organic light emitting diode display panel. The lower passivation film includes a support film that is in contact with the organic light emitting diode display panel, and a stress adjustment layer formed beneath the support film and configured to reduce a bending stress to be induced in the organic light emitting display panel when the organic light emitting display panel and the lower passivation film are bent.

Abstract: An electronic component mounting substrate includes: an insulating substrate having a recess that opens in a main surface of the insulating substrate, the recess for mounting an electronic component; a metal layer located on a bottom surface of the recess; an external electrode located on the other main surface of the insulating substrate, the other main surface opposite to the main surface; a connection wiring located between the metal layer and the external electrode in a thickness direction of the insulating substrate; a plurality of first vias that connects the metal layer and the connection wiring and that is located along a side wall of the recess in a perspective plan view; and a plurality of second vias that connects the connection wiring and the external electrode and that is located in a strip shape in the perspective plan view.