Abstract: A bonding structure production method for producing a bonding structure (100) includes at least bonding a semiconductor element (30) and a substrate (10) using a silver paste. The substrate (10) includes a die attachment portion (12) to which the semiconductor element (30) is to be bonded. The die attachment portion (12) includes an alumina layer (16) serving as a surface layer on a bonding side of the die attachment portion (12) to which the semiconductor element (30) is to be bonded. The silver paste contains a solvent and silver particles with a residual strain measured by X-ray diffractometry of at least 5.0%. Preferably, the silver particles have a volume-based 50% cumulative diameter of at least 100 nm and no greater than 50 ?m.

Abstract: Semiconductor device structures and methods for manufacturing the same are provided. The semiconductor device structure includes a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a first dielectric layer and a second dielectric layer. The first nitride semiconductor layer is disposed on the substrate. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer and has a bandgap greater than that of the first nitride semiconductor layer. The first dielectric layer is disposed on the second nitride semiconductor layer. The second dielectric layer is disposed on the first dielectric layer. The second dielectric layer includes a first portion and a second portion separated from the first portion by a trench, wherein the trench terminates at an upper surface of the first dielectric layer.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack including interleaved conductive layers and dielectric layers above the substrate, a plurality of channel structures each extending vertically through the memory stack, a semiconductor layer above and in contact with the plurality of channel structures, a plurality of source contacts above the memory stack and in contact with the semiconductor layer, a plurality of contacts through the semiconductor layer, and a backside interconnect layer above the semiconductor layer including a source line mesh in a plan view. The plurality of source contacts are distributed below and in contact with the source line mesh. A first set of the plurality of contacts are distributed below and in contact with the source line mesh.

Abstract: A power module includes: a first substrate having metal plates formed on one surface thereof; a second substrate spaced apart from the first substrate and having metal plates formed on one surface thereof facing the metal plates of the first substrate; a plurality of power elements disposed between the first substrate and the second substrate; a first electrode formed on the first substrate of each of the plurality of power elements; and a second electrode formed on the second surface of each of the plurality of power elements, where the plurality of power elements comprise a first power element in which the first electrode is bonded to the metal plates of the second substrate; and a second power element in which the first electrode is bonded to the metal plates of the first substrate.

Abstract: A light emitting diode (LED) precursor is provided. The LED precursor comprises a substrate (10), an LED structure (30) comprising a plurality of Group III-nitride layers, and a passivation layer (40). The LED structure comprises a p-type semiconductor layer (36), an n-type semiconductor layer (32), and an active layer (34) between the p-type and n-type semiconductor layers. Each of the plurality of Group III-nitride layers comprises a crystalline Group III-nitride. The LED structure has a sidewall (37) which extends in a plane orthogonal to a (0001) crystal plane of the Group III-nitride layers. The passivation layer is provided on the sidewall of the LED structure such that the passivation layer covers the active layer. The passivation layer comprises a crystalline Group III-nitride with a bandgap higher than a bandgap of the active layer.

Abstract: There is provided an information processing device which efficiently executes machine learning. The information processing device according to one embodiment includes: an obtaining unit which obtains a source code including a code which defines Forward processing of each layer constituting a neural network; a storage unit which stores an association relationship between each Forward processing and Backward processing associated with each Forward processing; and an executing unit which successively executes each code included in the source code, and which calculates an output value of the Forward processing defined by the code based on an input value at a time of execution of each code, and generates a reference structure for Backward processing in a layer associated with the code based on the association relationship stored in the storage unit.

Abstract: The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure. The manufacturing method of a semiconductor structure includes: providing a substrate, the substrate includes active regions and isolation regions, each of the isolation regions includes a first trench and an isolation layer formed in the first trench; removing part of the isolation layer to form first grooves; forming a first mask layer, the first mask layer covers upper surfaces of the active regions and fills the first grooves; planarizing the first mask layer, such that an upper surface of a portion of the first mask layer located above the active regions is flush with an upper surface of a portion of the first mask layer located above the isolation regions; removing part of the first mask layer, part of the isolation layer, and part of the substrate, to form second trenches and third trenches.

Abstract: An emission enhancement structure having at least one energy augmentation structure; and an energy converter capable of receiving energy from an energy source, converting the energy and emitting therefrom a light of a different energy than the received energy. The energy converter is disposed in a vicinity of the at least one energy augmentation structure such that the emitted light is emitted with an intensity larger than if the converter were remote from the at least one energy augmentation structure. Also described are various uses for the energy emitters, energy augmentation structures and energy collectors in a wide array of fields, including various adhesives applications.

Abstract: A semiconductor device includes: a metal sheet; an insulating pattern provided on the metal sheet; a power circuit pattern and a signal circuit pattern that are provided on the insulating pattern; a power semiconductor chip mounted on the power circuit pattern; and a control semiconductor chip that is mounted on the signal circuit pattern and controls the power semiconductor chip. The power semiconductor chip is bonded to the power circuit pattern with a first die bonding material comprised of copper, and the control semiconductor chip is bonded to the signal circuit pattern with a second die bonding material.

Abstract: The invention relates to a light-emitting component comprising a light-emitting section consisting of a Hex-Si1?xGex compound material, said Hex-Si1?xGex compound material having a direct band gap for emitting light. The invention also pertains to a light-absorbing component comprising a light-absorbing section consisting of a Hex-S1?xGex compound material, said Hex-Si1?xGex compound material having a direct band gap for absorbing light.

Abstract: A method for wafer bonding includes: providing a semiconductor wafer having a first main face; fabricating at least one semiconductor device in the semiconductor wafer, wherein the semiconductor device is arranged at the first main face; generating trenches and a cavity in the semiconductor wafer such that the at least one semiconductor device is connected to the rest of the semiconductor wafer by no more than at least one connecting pillar; arranging the semiconductor wafer on a carrier wafer such that the first main face faces the carrier wafer; attaching the at least one semiconductor device to the carrier wafer; and removing the at least one semiconductor device from the semiconductor wafer by breaking the at least one connecting pillar.

Abstract: We herein describe a semiconductor device sub-assembly comprising at least two power semiconductor devices and a contact of a first type. A first power semiconductor device is located on a first side of the contact of a first type, and a second power semiconductor device is located on a second side of the contact of a first type, where the second side is opposite to the first side.

Abstract: A device includes a resistance switching layer, a capping layer, a top electrode, a first spacer, and a second spacer. The resistance switching layer is over a substrate. The capping layer is over the resistance switching layer. The top electrode is over the capping layer. The first spacer lines the resistance switching layer and the capping layer. The second spacer lines the first spacer. The capping layer is in contact with the top electrode, the first spacer, and the second spacer.

Abstract: A semiconductor module includes: a semiconductor device; a bonding layer that is arranged on the semiconductor device, and contains nickel or copper, an entire back surface of the bonding layer being electrically connected to and in direct contact with an electrode in the semiconductor device; an anti-oxidation layer disposed on the bonding layer; and a protective layer disposed directly on a top surface of a peripheral portion of the bonding layer on which the anti-oxidation layer is absent, covering an outer peripheral edge of the bonding layer, wherein the protective layer is made of an electrically insulating resin.

Abstract: One type of plasmonic organic electrochemical transistor (POECT) includes a channel comprising an organic semiconductor, a gate electrode comprising at least one of: an ensemble of nanoparticles and an array of nanostructures, wherein each of the at least one of: an ensemble of nanoparticles and an array of nanostructures comprises localized plasmonic material, an analyte formed at least one of: (a) over the at least one of: the ensemble of nanoparticles and the array of nanostructures and (b) around the at least one of: the ensemble of nanoparticles and the array of nanostructures, wherein an electrolyte is configured to be formed at least one of: between the channel and the gate electrode and over the channel and the gate electrode, a source electrode electrically connected to a first end of the channel; and a drain electrode electrically connected to a second end of the channel which is opposite the first end.

Abstract: A micro LED display device includes a display back plate having a first connecting electrode and a second connecting electrode, a micro LED structure disposed on the display back plate, and a first bonding structure and a second bonding structure disposed between the display back plate and the micro LED structure. The micro LED structure includes an epitaxial structure, and a first electrode and a second disposed on the side of the epitaxial structure closest to the display back plate. The orthogonal projections of the extension portions of the first electrode and the second electrode both exceed the orthogonal projection of the epitaxial structure on the display back plate. Neither the orthogonal projection of the first bonding structure nor the orthogonal projection of the second bonding structure overlaps the orthogonal projection of the bottom surface of the epitaxial structure on the display back plate.

Abstract: The present application discloses an array substrate, a manufacturing method therefor and a display panel. The manufacturing method for the array substrate includes steps of: forming a base layer; forming a semiconductor layer on the base layer; forming a metal layer on the semiconductor layer, where the upper surface of the metal layer contains a first nitride or a first oxide; etching the metal layer into a source/drain electrode; and forming a passivation layer on the source/drain electrode, where the passivation layer is a second nitride structure corresponding to the first nitride or a second oxide structure corresponding to the first oxide.

Abstract: A display substrate, including a base substrate, and a driving circuit layer and light emitting elements formed on the base substrate, and in a same pixel circuit, an active general layer includes a first column-wise active portion including active layers of the a data writing transistor and the a first light emission control transistor, and a first active connection portion, an orthographic projection of the first active connection portion on the base substrate at least partially overlapping an orthographic projection of a corresponding power supply line on the base substrate, a dimension of the first active connection portion in a row direction of pixel units being less than a dimension of the active layer of the data writing transistor in the row direction, and a dimension of the active layer of the first light emission control transistor in the row direction. A display panel is further provided.

Abstract: The invention provides a method for forming a semiconductor structure, which comprises providing a substrate, sequentially a first groove and a second groove are formed in the substrate, the depth of the first groove is different from the depth of the second groove, a first oxide layer is formed in the first groove, a second oxide layer is formed in the second groove, an etching step is performed to remove part of the first oxide layer, a first gate structure is formed on the first oxide layer, and a second gate structure is formed on the second oxide layer.

Abstract: A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a transistor and a capacitor. The transistor includes a metal oxide and a first conductor that is electrically connected to the metal oxide. The capacitor includes a first insulator which is provided over the metal oxide and which the first conductor penetrates; a second insulator provided over the first insulator and including an opening reaching the first insulator and the first conductor; a second conductor in contact with an inner wall of the opening, the first insulator, and the first conductor; a third insulator provided over the second conductor; and a fourth conductor provided over the third insulator. The first insulator has higher capability of inhibiting the passage of hydrogen than the second insulator.