Abstract: Disclosed herein are systems, apparatuses, methods, and non-transitory computer readable media related to a display construct coupled to a structure (e.g., a vision window). The structure can be a supportive structure such as a fixture. The display construct is configured to facilitate media display and is at least partially transparent. The vision window may be a tintable window, e.g., a window in which its tint is electrically controllable (e.g., an electrochromic window). Various interactive capabilities with the display construct are disclosed (e.g., via a touch screen).

Abstract: The present invention provides a motion control structure and a actuator. The motion control structure includes a motion platform, a first actuator having a first execution unit arranged on opposite sides of the motion platform along an X-axis direction and a second execution unit arranged on opposite sides of the motion platform along a Y-axis direction. The first execution unit includes a first actuating element displaced along the X-axis direction. The second execution unit includes a second actuating element displaced along the Y-axis direction. A second actuator surrounds an inner periphery of the motion platform and includes a third execution unit having an assembly portion displaced along the Z-axis direction. The motion control structure of the invention has the advantages that the motion platform can be driven to realize motion in six degrees of freedom.

Abstract: A semiconductor device includes a semiconductor wafer or a single semiconductor chip or die, and a layer stack. The layer stack comprises a first layer comprising NiSi, and a second layer comprising NiV, wherein the second layer is arranged between the first layer and the semiconductor wafer or single semiconductor chip or die.

Abstract: The invention relates to a method for producing a plurality of optoelectronic semiconductor components, including the following steps: preparing a plurality of semiconductor chips spaced in a lateral direction to one another; forming a housing body assembly, at least one region of which is arranged between the semiconductor chips; forming a plurality of fillets, each adjoining a semiconductor chip and being bordered in a lateral direction by a side surface of each semiconductor chip and the housing body assembly; and separating the housing body assembly into a plurality of optoelectronic components, each component having at least one semiconductor chip and a portion of the housing body assembly as a housing body, and each semiconductor chip not being covered by material of the housing body on a radiation emission surface of the semiconductor component, which surface is located opposite a mounting surface. The invention also relates to a semiconductor component.

Abstract: High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to gate structures and methods of manufacture. The structure includes: a gate structure comprising a horizontal portion and a substantially vertical stem portion; and an air gap surrounding the substantially vertical stem portion and having a curved surface under the horizontal portion.

Abstract: A display panel includes a substrate, a planarization layer disposed at a side of the substrate being provided with partitioning slots to form driving areas in an array; a first electrode layer on the planarization layer having first electrodes; wherein orthographic projections of the first electrodes on the planarization layer are within the driving areas; each of the first electrodes includes a planar center portion and an edge portion, the edge portion includes a planarization portion surrounding the center portion and a slope portion connected between the center portion and the planarization portion; a pixel definition layer on the planarization layer that exposes part of the center portion; a light-emitting functional layer covering the pixel definition layer, the center portion being exposed by the pixel definition layer and the planarization layer and a second electrode covering the light-emitting functional layer.

Abstract: The present invention relates to a semiconductor device. The semiconductor device includes: a first main electrode provided on an active region; a second main electrode provided on an opposite side of the semiconductor substrate from the first main electrode; a protection film covering a terminal region; and a non-electrolytic plating layer provided on the first main electrode not covered by the protection film, the first main electrode includes a center electrode in a center part and an outer peripheral electrode provided along the center electrode to be separately from the center electrode, the protection film is provided to extend from the terminal region to an end edge portion of the outer peripheral electrode, the center electrode and the outer peripheral electrode include: a first metal layer; and a second metal layer provided on the first metal layer, and the outer peripheral electrode includes a hole part to reach the first metal layer.

Abstract: A method is provided for producing a hermetically sealed housing having a semiconductor component. The method comprises introducing a housing having a housing body and a housing cover into a process chamber. The housing cover closes off a cavity of the housing body and is attached in a gas-tight manner to the housing body. At least one opening is formed in the housing. At least one semiconductor component is arranged in the cavity. The method furthermore comprises generating a vacuum in the cavity by evacuating the process chamber, and also generating a predetermined gas atmosphere in the cavity and the process chamber. The method moreover comprises applying sealing material to the at least one opening while the predetermined gas atmosphere prevails in the process chamber.

Abstract: Embodiments of the invention describe semiconductor devices with high aspect ratio fins and methods for forming such devices. According to an embodiment, the semiconductor device comprises one or more nested fins and one or more isolated fins. According to an embodiment, a patterned hard mask comprising one or more isolated features and one or more nested features is formed with a hard mask etching process. A first substrate etching process forms isolated and nested fins in the substrate by transferring the pattern of the nested and isolated features of the hard mask into the substrate to a first depth. A second etching process is used to etch through the substrate to a second depth. According to embodiments of the invention, the first etching process utilizes an etching chemistry comprising HBr, O2 and CF4, and the second etching process utilizes an etching chemistry comprising Cl2, Ar, and CH4.

Abstract: The present disclosure describes a method for forming polysilicon resistors with high-k dielectrics and polysilicon gate electrodes. The method includes depositing a resistor stack on a substrate having spaced apart first and second isolation regions. Further the method includes patterning the resistor stack to form a polysilicon resistor structure on the first isolation region and a gate structure between the first and second isolation regions, and doping the polysilicon resistor structure to form a doped layer in the polysilicon layer of the polysilicon resistor structure and source-drain regions in the substrate adjacent to the gate structure. Also, the method includes replacing the polysilicon layer in the gate structure with a metal gate electrode to form a transistor structure.

Abstract: Disclosed herein are systems, apparatuses, methods, and non-transitory computer readable media related to a display construct coupled to a structure (e.g., a vision window). The structure can be a supportive structure such as a fixture. The display construct is configured to facilitate media display and is at least partially transparent. The vision window may be a tintable window, e.g., a window in which its tint is electrically controllable (e.g., an electrochromic window). Various interactive capabilities with the display construct are disclosed (e.g., via a touch screen).

Abstract: In a method of group control and management among electronic devices, wherein the electronic devices is in communication with a control device, a projectable space instance is provided for the control device to create a workspace, wherein a control and management tool and a plurality of unified tools for driving respective electronic devices are selectively added to the projectable space instance. The projectable space instance is then parsed with a projector by the control device to automatically generate a projected workspace corresponding to the workspace to be created via the projectable space instance. The control and management tool realizes at least one status information of at least a first one of the electronic devices by way of the unified tools, and controls at least a second one of the electronic devices to execute at least one task corresponding to the at least one status information.

Abstract: An semiconductor device includes a first dielectric layer, an etch stop layer, an interconnect structure, and a second dielectric layer. The etch stop layer is over the first dielectric layer. The interconnect structure includes a conductive via in the first dielectric layer and the etch stop layer, a conductive line over the conductive via, an intermediate conductive layer over the conductive line, and a conductive pillar over the intermediate conductive layer. The interconnect structure is electrically conductive at least from a top of the conductive pillar to a bottom of the conductive via. The second dielectric layer surrounds the conductive line, the intermediate conductive layer, and the conductive pillar, wherein a bottom of the second dielectric layer is lower than a top of the conductive line, and a top of the second dielectric layer is higher than the top of the conductive line.

Abstract: Disclosed is a semiconductor structure and a manufacturing method. The semiconductor structure includes an N-type doped region in a substrate; a metal structure on a surface of the substrate and including a middle portion and an edge portion, wherein the middle portion is in contact with the N-type doped region so as to form an SBD; a first P-type well region which is located in the N-type doped region, in contact with the edge portion and separates the edge portion from the N-type doped region; a first P-type contact region located in the first P-type well region and separated from the edge portion. When the first P-type contact region is grounded, the first P-type well region receives an anode voltage of the SBD. Low voltage drop and high frequency characteristics of the SBD are maintained on a premise of improving the breakdown voltage reducing the leak current.

Abstract: An adhesive film includes a base material layer; an adhesive resin layer (A) provided on a first surface side of the base material layer; and an adhesive resin layer (B) provided on a second surface side of the base material layer and in which an adhesive force is decreased by an external stimulus, in which, as measured by method 1, an integrated tacking force value (F2.5) of the adhesive resin layer (B) is 1.0 gf/sec or more at a test speed of 2.5 mm/min and a test temperature of 130° C., and an integrated tacking force value (F30) of the adhesive resin layer (B) is 7.0 gf/sec or more at a test speed of 30 mm/min and a test temperature of 130° C.

Abstract: The present description concerns a microelectromechanical sensor control method, including the steps of: exciting, with same first signal (FSL), a first resonant (206L) and at least one second resonant element (206R); and estimating a phase shift (??) between the first signal and a second signal (FSR) which is an image of vibrations of the second resonant element.

Abstract: A light emitting device package including a package body comprising a first opening; a light emitting device disposed in the first opening and including a first bonding part and a second bonding part; a first conductor disposed below the first bonding part; and a second conductor disposed below the second bonding part. Further, the first conductor is electrically connected to the first bonding part, and the second conductor is electrically connected to the second bonding part.

Abstract: RF amplifiers are provided that include an interconnection structure and a Group III nitride-based RF amplifier die that is mounted on top of the interconnection structure. The Group III nitride-based RF amplifier die includes a semiconductor layer structure. A plurality of unit cell transistors are provided in an upper portion of the semiconductor layer structure, and a gate terminal, a drain terminal and a source terminal are provided on a lower surface of the semiconductor layer structure that is adjacent the interconnection structure.

Abstract: A semiconductor device includes a first doped zone and a second doped zone in a first semiconductor material, the first doped zone being separated from the second doped zone; an isolation structure between the first doped zone and the second doped zone; and a first line segment over a top surface of the first doped zone, where the ends of the first line segment and the ends of the second line are over the isolation structure. The first line segment and the second line segment have a first width; and a dielectric material is between the first line segment and the second line segment and over the isolation structure. The first width is substantially similar to a width of a gate electrode in the semiconductor device.