Abstract: An optical sensing system, comprising: a first light source, configured to emit first light to a first position; a second light source, configured to emit second light to a second position, wherein the first position is above the second position, wherein the first light is not emitted to the second position and the second light is not emitted to the first position; and an optical sensor, configured to sense optical data generated based on at least one of the first light source and the second light source; wherein a detecting region of the optical sensor comprises an upper half region and a lower half region, wherein a size of the upper half region is adjustable.

Abstract: A semiconductor memory device includes a bit line, a common source pattern above the bit line, a channel layer in contact with the common source pattern, the channel layer extending toward the bit line, and a filling insulating layer disposed between the bit line and the common source pattern, the filling insulating layer surrounding a first part of the channel layer. The semiconductor memory device also includes a gate stack structure disposed between the bit line and the filling insulating layer, the gate stack structure surrounding a second part of the channel layer. The semiconductor memory device further includes a first etch stop pattern on a sidewall of the filling insulating layer, a second etch stop pattern between the first etch stop pattern and the filling insulating layer, and a memory pattern between the gate stack structure and the channel layer.

Abstract: The present disclosure provides a flexible display panel, a method for forming the flexible display panel and an adhesive application device for the method. The flexible display panel includes a cover plate layer and a screen film layer. The screen film layer includes a plurality of film layers laminated one on another at one side of the cover plate layer, and an adhesive is filled into a gap between an edge of an outermost film layer of the screen film layer relative to the cover plate layer and the cover plate layer.

Abstract: A display device including a light-emitting element, an encapsulation layer over the light-emitting element and including a first inorganic encapsulation layer, an organic encapsulation layer and a second inorganic encapsulation layer in order, and the first inorganic encapsulation layer and the second inorganic encapsulation layer in direct contact with each other to define an inorganic encapsulation area of the display device, a supply voltage line electrically connected to the light-emitting element, a signal line which provides an electrical signal to the display area, and within the inorganic encapsulation area of the display device, the signal line overlapping the supply voltage line and an etch stop pattern between the supply voltage line and the signal line which overlap each other.

Abstract: A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region by forming a plurality of metal lines in a first dielectric layer; and recessing in a recess region first portions of the plurality of metal lines such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; wherein a non-recess region includes second portions of the plurality of metal lines that are outside the recess region.

Abstract: Disclosed is a single transistor with a double gate structure for an adjustable firing threshold voltage and a neuromorphic system using the same. A single transistor neuron with a double gate structure according to an example embodiment includes a barrier material layer formed on a semiconductor substrate and comprising a hole barrier material or an electron barrier material; a floating body layer formed on the barrier material layer; a source and a drain formed at both sides of the floating body layer, respectively; a driving gate formed at a first side of the floating body layer without contacting the source and the drain; a control gate formed at a second side of the floating body layer without contacting the source and the drain; and a gate insulating film formed between the floating body layer and the driving gate and between the floating body layer and the control gate.

Abstract: An embodiment of the present disclosure relates to a detector that includes an AD and detects charged particles or light, and enables speeding up of response of the detector without changing a structure of the AD that limits the response of the detector. A drive circuit of the AD includes a first capacitor and a first resistor. Both the first capacitor and the first resistor are connected in series to the AD in a state where both terminals are set to have the same potential. This configuration reduces the apparent capacitance of the AD and speeds up the response of the entire detector including the drive circuit.

Abstract: A semiconductor device includes a plurality of nanostructures. The nanostructures each contain a semiconductive material. A plurality of first spacers circumferentially wrap around the nanostructures. A plurality of second spacers circumferentially wrap around the first spacers. A plurality of third spacers is disposed between the second spacers vertically. A gate structure surrounds the second spacers and the third spacers.

Abstract: A flexible display panel, a flexible display device and a method of forming the flexible display panel are provided. The flexible display panel includes: a substrate; thin film transistors arranged in an array on the substrate; an electroluminescent device arranged on the thin film transistors and driven by the thin film transistors, including a pixel defining layer and an electroluminescent material defined by the pixel defining layer; a thin film encapsulation layer on the electroluminescent device; a quantum dot photoconversion layer on the thin film encapsulation layer, including an isolation portion and a quantum dot luminescent material surrounded by the isolation portion, where an orthographic projection of the isolation portion onto the substrate covers an orthographic projection of the pixel defining layer onto the substrate; and a cover plate arranged on the quantum dot photoconversion layer.

Abstract: A photomask according to an exemplary embodiment includes: a mask substrate; and a first test pattern and a second test pattern disposed along a first edge of the mask substrate, wherein the first test pattern has a first outer shape and a first inner shape, the second test pattern has a second outer shape, and the second outer shape of the second test pattern is larger than the first inner shape of the first test pattern and smaller than the first outer shape of the first test pattern.

Abstract: A semiconductor device including a FET includes an isolation insulating layer disposed in a trench of the substrate, a gate dielectric layer disposed over a channel region of the substrate, a gate electrode disposed over the gate dielectric layer, a source and a drain disposed adjacent to the channel region, and an embedded insulating layer disposed below the source, the drain and the gate electrode and both ends of the embedded insulating layer are connected to the isolation insulating layer.

Abstract: The disclosure provides an electronic device. The electronic device includes a substrate, a transistor, and a variable capacitor. The transistor is disposed on the substrate. The variable capacitor is disposed on the substrate and adjacent to the transistor. A material of the transistor and a material of the variable capacitor both a include a III-V semiconductor material. The electronic device of an embodiment of the disclosure may simplify manufacturing process, reduce costs, or reduce dimensions.

Abstract: A semiconductor device includes a semiconductor wafer or a single semiconductor chip or die, and a layer stack. The layer stack comprises a first layer comprising NiSi, and a second layer comprising NiV, wherein the second layer is arranged between the first layer and the semiconductor wafer or single semiconductor chip or die.

Abstract: A display substrate includes: a base substrate having a display region and a peripheral region surrounding the display region; a plurality of sub-pixels in the display region; a plurality of data lines in the display region, electrically coupled to the plurality of sub-pixels respectively, and configured to provide a data signal to the plurality of sub-pixels respectively; a plurality of pads in the peripheral region, wherein at least a portion of the plurality of pads are configured to provide a data signal to the plurality of data lines respectively; at least one test data signal line in the peripheral region; at least one test control signal line in the peripheral region; and a plurality of test units in the peripheral region and on a side of the plurality of pads away from the display region.

Abstract: An etch stop detection structure and an etch stop detection method are provided. The etch stop detection structure includes a substrate, a first dielectric layer, a first stop layer, and a second dielectric layer. The substrate includes a device region and a detection region. The first dielectric layer is located on the substrate. The first stop layer is located on the first dielectric layer. The second dielectric layer is located on the first stop layer. There is a first air gap in the first dielectric layer and the first stop layer in the device region. There is a trench in the second dielectric layer in the detection region. The trench exposes the first stop layer. The etch stop detection structure can be used to detect the etch stop signal.

Abstract: The disclosure is directed to an electronic package with an interposer between integrated circuit dies. At least one inner capacitor (e.g., single layer capacitor) is mounted to the interposer. The electronic package further includes an input passive circuit substrate and an output passive circuit substrate mechanically coupled to the metal base. Use of an interposer to be simultaneously solder attached with integrated circuit dies provides a configuration that improves linearity performance and/or wide video bandwidth of the electronic package (e.g., packages that use epoxy and laminate interposers). Further, such configuration facilitates efficient manufacturing of the electronic package at high volumes.

Abstract: High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region.

Abstract: Embodiments of the invention describe semiconductor devices with high aspect ratio fins and methods for forming such devices. According to an embodiment, the semiconductor device comprises one or more nested fins and one or more isolated fins. According to an embodiment, a patterned hard mask comprising one or more isolated features and one or more nested features is formed with a hard mask etching process. A first substrate etching process forms isolated and nested fins in the substrate by transferring the pattern of the nested and isolated features of the hard mask into the substrate to a first depth. A second etching process is used to etch through the substrate to a second depth. According to embodiments of the invention, the first etching process utilizes an etching chemistry comprising HBr, O2 and CF4, and the second etching process utilizes an etching chemistry comprising Cl2, Ar, and CH4.

Abstract: A micro light-emitting device includes an epitaxial structure. The epitaxial structure has a bottom surface and includes a plurality of grooves, and the grooves are located on the bottom surface. Each of the grooves includes a plurality of sub-grooves, and the sub-grooves define an inner wall of each of the grooves. A ratio of a size of each of the grooves to a size of each of the sub-grooves is greater than 1 and less than or equal to 4000.

Abstract: A semiconductor device may include a Silicon on Insulator (SOI) substrate, and a diode formed on the SOI substrate, the diode including a cathode region and an anode region. The semiconductor device may include at least one breakdown voltage trench disposed at an edge of the cathode region, and between the cathode region and the anode region.