Abstract: The present disclosure describes a method for forming polysilicon resistors with high-k dielectrics and polysilicon gate electrodes. The method includes depositing a resistor stack on a substrate having spaced apart first and second isolation regions. Further the method includes patterning the resistor stack to form a polysilicon resistor structure on the first isolation region and a gate structure between the first and second isolation regions, and doping the polysilicon resistor structure to form a doped layer in the polysilicon layer of the polysilicon resistor structure and source-drain regions in the substrate adjacent to the gate structure. Also, the method includes replacing the polysilicon layer in the gate structure with a metal gate electrode to form a transistor structure.

Abstract: Disclosed herein are systems, apparatuses, methods, and non-transitory computer readable media related to a display construct coupled to a structure (e.g., a vision window). The structure can be a supportive structure such as a fixture. The display construct is configured to facilitate media display and is at least partially transparent. The vision window may be a tintable window, e.g., a window in which its tint is electrically controllable (e.g., an electrochromic window). Various interactive capabilities with the display construct are disclosed (e.g., via a touch screen).

Abstract: An semiconductor device includes a first dielectric layer, an etch stop layer, an interconnect structure, and a second dielectric layer. The etch stop layer is over the first dielectric layer. The interconnect structure includes a conductive via in the first dielectric layer and the etch stop layer, a conductive line over the conductive via, an intermediate conductive layer over the conductive line, and a conductive pillar over the intermediate conductive layer. The interconnect structure is electrically conductive at least from a top of the conductive pillar to a bottom of the conductive via. The second dielectric layer surrounds the conductive line, the intermediate conductive layer, and the conductive pillar, wherein a bottom of the second dielectric layer is lower than a top of the conductive line, and a top of the second dielectric layer is higher than the top of the conductive line.

Abstract: In a method of group control and management among electronic devices, wherein the electronic devices is in communication with a control device, a projectable space instance is provided for the control device to create a workspace, wherein a control and management tool and a plurality of unified tools for driving respective electronic devices are selectively added to the projectable space instance. The projectable space instance is then parsed with a projector by the control device to automatically generate a projected workspace corresponding to the workspace to be created via the projectable space instance. The control and management tool realizes at least one status information of at least a first one of the electronic devices by way of the unified tools, and controls at least a second one of the electronic devices to execute at least one task corresponding to the at least one status information.

Abstract: Disclosed is a semiconductor structure and a manufacturing method. The semiconductor structure includes an N-type doped region in a substrate; a metal structure on a surface of the substrate and including a middle portion and an edge portion, wherein the middle portion is in contact with the N-type doped region so as to form an SBD; a first P-type well region which is located in the N-type doped region, in contact with the edge portion and separates the edge portion from the N-type doped region; a first P-type contact region located in the first P-type well region and separated from the edge portion. When the first P-type contact region is grounded, the first P-type well region receives an anode voltage of the SBD. Low voltage drop and high frequency characteristics of the SBD are maintained on a premise of improving the breakdown voltage reducing the leak current.

Abstract: An adhesive film includes a base material layer; an adhesive resin layer (A) provided on a first surface side of the base material layer; and an adhesive resin layer (B) provided on a second surface side of the base material layer and in which an adhesive force is decreased by an external stimulus, in which, as measured by method 1, an integrated tacking force value (F2.5) of the adhesive resin layer (B) is 1.0 gf/sec or more at a test speed of 2.5 mm/min and a test temperature of 130° C., and an integrated tacking force value (F30) of the adhesive resin layer (B) is 7.0 gf/sec or more at a test speed of 30 mm/min and a test temperature of 130° C.

Abstract: A light emitting device package including a package body comprising a first opening; a light emitting device disposed in the first opening and including a first bonding part and a second bonding part; a first conductor disposed below the first bonding part; and a second conductor disposed below the second bonding part. Further, the first conductor is electrically connected to the first bonding part, and the second conductor is electrically connected to the second bonding part.

Abstract: RF amplifiers are provided that include an interconnection structure and a Group III nitride-based RF amplifier die that is mounted on top of the interconnection structure. The Group III nitride-based RF amplifier die includes a semiconductor layer structure. A plurality of unit cell transistors are provided in an upper portion of the semiconductor layer structure, and a gate terminal, a drain terminal and a source terminal are provided on a lower surface of the semiconductor layer structure that is adjacent the interconnection structure.

Abstract: A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region by forming a plurality of metal lines in a first dielectric layer; and recessing in a recess region first portions of the plurality of metal lines such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; wherein a non-recess region includes second portions of the plurality of metal lines that are outside the recess region.

Abstract: A packaged integrated circuit (IC) includes a leadframe including a die pad and leads around the die pad, an analog IC die having first bond pads on its active top side, and a second circuit including second circuit bond pads attached to the analog IC die by an attachment layer configured as a ring with a hollow center that provides an inner gap. A bottom side of the analog IC or the second circuit is attached to the die pad. Bond wires couple at least some of the first bond pads or some of the second circuit bond pads to the leads, and there is a second coupling between others of the second circuit bond pads and others of the first bond pads. A mold compound is for encapsulating the second circuit and the analog IC.

Abstract: The present description concerns a microelectromechanical sensor control method, including the steps of: exciting, with same first signal (FSL), a first resonant (206L) and at least one second resonant element (206R); and estimating a phase shift (??) between the first signal and a second signal (FSR) which is an image of vibrations of the second resonant element.

Abstract: A semiconductor device includes a first doped zone and a second doped zone in a first semiconductor material, the first doped zone being separated from the second doped zone; an isolation structure between the first doped zone and the second doped zone; and a first line segment over a top surface of the first doped zone, where the ends of the first line segment and the ends of the second line are over the isolation structure. The first line segment and the second line segment have a first width; and a dielectric material is between the first line segment and the second line segment and over the isolation structure. The first width is substantially similar to a width of a gate electrode in the semiconductor device.

Abstract: Various embodiments of the present disclosure are directed towards a method to embed planar field-effect transistor (FETs) with fin field-effect transistors (finFETs). A semiconductor substrate is patterned to define a mesa and a fin. A trench isolation structure is formed overlying the semiconductor substrate and surrounding the mesa and the fin. A first gate dielectric layer is formed on the mesa, but not the fin. The trench isolation structure recessed around the fin, but not the mesa, after the forming the first gate dielectric layer. A second gate dielectric layer is deposited overlying the first gate dielectric layer at the mesa and further overlying the fin. A first gate electrode is formed overlying the first and second gate dielectric layers at the mesa and partially defining a planar FET. A second gate electrode is formed overlying the second gate dielectric layer at the fin and partially defining a finFET.

Abstract: A display device according to an exemplary embodiment of the present invention includes: a first substrate and a second substrate; a plurality of signal lines that are formed on the first substrate or on the second substrate; and a plurality of side wires that are disposed in a side surface of a first edge of the first substrate and a side surface of a second edge of the second substrate, wherein the plurality of side wires are disposed apart from each other along a direction in which the first edge extends, and are connected with the plurality of signal lines, and a first thickness of side wires disposed at an end of the first edge and at and end of the second edge is different from a second thickness of the side wire disposed at inside of the edges of the first edge and the second edge.

Abstract: Some embodiments include an integrated assembly having a first semiconductor material between two regions of a second semiconductor material. The second semiconductor material is a different composition than the first semiconductor material. Hydrogen is diffused within the first and second semiconductor materials. The conductivity of the second semiconductor material increases in response to the hydrogen diffused therein to thereby create a structure having the second semiconductor material as source/drain regions, and having the first semiconductor material as a channel region between the source/drain regions. A transistor gate is adjacent the channel region and is configured to induce an electric field within the channel region. Some embodiments include methods of forming integrated assemblies.

Abstract: A semiconductor module includes: a semiconductor device; a bonding layer that is arranged on the semiconductor device, contains nickel or copper, and is electrically connected to the semiconductor device; a solder portion containing gold, disposed on the bonding layer; and a protective layer disposed directly on the bonding layer, covering an outer peripheral edge of the bonding layer.

Abstract: A semiconductor device includes a light-emitting element, a light-receiving element, a switching element, an input-side terminal, an output-side terminal, and a resin layer. The light-emitting element, the light-receiving element and the switching element are provided at the front side of the resin layer. The light-receiving element and the switching element are arranged in a first direction along the front side of the resin layer. The switching element is electrically connected to the light-receiving element. The light-receiving element is provided between the light-emitting element and the resin layer. The input-side and output-side terminals are provided at the backside of the resin layer. The input-side terminal is electrically connected to the light-emitting element. The output-side terminal is electrically connected to the switching element.

Abstract: A display module and a method for manufacturing thereof are provided. The display module includes a substrate including a pad, a conduction film which is bonded to the substrate including the pad, wherein at least one of a surface of the conduction film and an inner portion of the conduction film is black color treated, and a display device mounted on the pad to which the conduction film is bonded.

Abstract: A display device includes a substrate; a plurality of pixels on the substrate; a light emitting element in each of the plurality of pixels; a first electrode electrically coupled with the light emitting element; a transistor on the substrate and electrically coupled with the first electrode; and a coupling layer between the first electrode and the light emitting element in a direction perpendicular to the substrate and containing a plurality of first conductive nanoparticles.

Abstract: A power module includes a first substrate including a first metal plate, a second substrate spaced apart from the first substrate and having a second metal facing the first substrate, a plurality of power elements that are disposed between the first substrate and the second substrate and include a first electrode and a second electrode. The plurality of power elements include a first power element having the first electrode bonded to the second metal plate, and a second power element having the first electrode bonded to the first metal plate.