Abstract: Implementations of semiconductor packages may include: a digital signal processor having a first side and a second side and an image sensor array, having a first side and a second side. The first side of the image sensor array may be coupled to the second side of the digital signal processor through a plurality of hybrid bond interconnect (HBI) bond pads and an edge seal. One or more openings may extend from the second side of the image sensor array into the second side of the digital signal processor to an etch stop layer in the second side of the digital signal processor. The one or more openings may form a second edge seal between the plurality of HBI bond pads and the edge of the digital signal processor.

Abstract: An optoelectronic device comprises a substrate, an optoelectronic element mounted on the substrate, a shielding cap providing electromagnetic shielding, at least one optical element attached to the shielding cap, and a detection element configured to detect if the shielding cap is mounted on the substrate.

Abstract: Electronic devices that detect their position and/or orientation with respect to earth's frame of reference are described. A coupler can removeably maintain the electronic devices in physical proximity of one another. Each electronic device can have a housing and the coupler can be included on the housing and arranged to physically connect the housing of the electronic device to the housing of at least one other electronic device. Alternatively, the coupler can be a packaging that maintains the electronic devices in physical proximity of one another. Each electronic device can be calibrated using the orientation or position information obtained by other electronic devices maintained by the coupler. Further, each electronic device can include a power source that remains inactive until the device is ready for use.

Abstract: A heat sink and power interconnect for a UV LED array are provided. A first circuit is disposed on a surface of a first substrate. A UV LED array is positioned thereon. A second substrate and second circuit are spaced apart from the first substrate and a first heat sink is positioned adjacent thereto. An aperture passes through each of the first substrate, the second substrate, and the heat sink. An electrical insulator lines the aperture with an electrically and thermally conductive liner positioned adjacent to the electrical insulator. A fastener is positioned in the aperture and electrically interconnects the first circuit and the second circuit through the electrically and thermally conductive liner and electrically communicates with an external power supply. The fastener carries one or more of a power or an electrical signal, and dissipates heat through the electrically and thermally conductive liner to the heat sink.

Abstract: Computational systems and methods employ characteristics of a quantum processor determined or sampled between a start and an end of an annealing evolution per an annealing schedule. The annealing evolution can be reinitialized, reversed or continued after determination. The annealing evolution can be interrupted. The annealing evolution can be ramped immediately prior to or as part of determining the characteristics. The annealing evolution can be paused or not paused immediately prior to ramping. A second representation of a problem can be generated based at least in part on the determined characteristics from an annealing evolution performed on a first representation of the problem. The determined characteristics can be autonomously compared to an expected behavior, and alerts optionally provided and/or the annealing evolution optionally terminated based on the comparison. Iterations of annealing evolutions may be performed until an exit condition occurs.

Abstract: A semiconductor package includes a wafer and at least one chip attached on first portions of an upper surface of the wafer. Further, the semiconductor package includes an insulating barrier layer, a thermally conductive layer, and a heat sink. The insulating barrier layer is arranged over the at least one chip attached on first portions of an upper surface of the wafer. The thermally conductive layer is arranged over the insulating barrier layer and at least partially encapsulates the at least one chip. The heat sink is arranged over the thermally conductive layer.

Abstract: A method for scalable multi-task learning with convex clustering includes: extracting features from a dataset of a plurality of tasks; generating a graph from the extracted features, nodes of the graph representing linear learning models, each of the linear learning models being for one of the tasks; constraining the graph using convex clustering to generate a convex cluster constrained graph; and obtaining a global solution by minimizing a graph variable loss function, the minimizing the graph variable loss function comprising: introducing auxiliary variables for each connection between nodes in the convex cluster constrained graph; iteratively performing the following operations until convergence: updating the linear learning models by solving a sparse linear system; and updating the auxiliary variables by solving an equation having the auxiliary variables each be proportional to a vector norm for their respective nodes.

Abstract: The present invention discloses a double color micro LED display panel including a plurality of pixels and a plurality of barrier components. Each of the pixels includes a substrate, a first bonding layer configured on the substrate, a first light emitting layer configured on the first bonding layer and emitting a first light, a second bonding layer configured on the first light emitting layer and a second light emitting layer configured on the second bonding layer and emitting a second light. The wavelength of the second light is different from that of the first light. The barrier components respectively located between the pixels for blocking a light emitted from one of the pixels to the other of the pixels. Wherein, the material of the second bonding layer is a non-metallic material.

Abstract: A desired range of lift force to raise a window shade is used to select the window shade hardware such as, for example, the optimal LAM. A desired lift force may be 5 pounds for ADA compliance. However, if the user wants to exert less effort to lift the window shade, the user may request an increased lift force of 6 or 7 pounds. Therefore, if a lift force range between 3-8.5 pounds is desired, the system selects the optimal LAM to maintain and guarantee that the lift force required to operate the shades will not exceed the desired range of between 3-8.5 pounds.

Abstract: The present application discloses a semiconductor device with the flowable layer. The semiconductor device includes a substrate, a first isolation layer positioned in the substrate, a first treated flowable layer positioned between the first isolation layer and the substrate, a second isolation layer positioned in the substrate, and a second treated flowable layer positioned between the second isolation layer and the substrate. A width of the first isolation layer is greater than a width of the second isolation layer, and a depth of the first isolation layer is less than a depth of the second isolation layer.

Abstract: Aspects of the present technology are directed toward Integrated Circuits (IC) including a plurality of trenches disposed in a substrate about a set of silicide regions. The trenches can extend down into the substrate below the set of silicide regions. The silicide regions can be formed by implanting metal ions into portions of a substrate exposed by a mask layer with narrow pitch openings. The trenches can be formed by selectively etching the substrate utilizing the set of silicide regions as a trench mask. An semiconductor material with various degree of crystallinity can be grown from the silicide regions, in openings that extend through subsequently formed layers down to the silicide regions.

Abstract: A semiconductor device includes a semiconductor substrate, a first semiconductor stack, a second semiconductor stack, a first gate structure, and a second gate structure. The semiconductor substrate comprising a first device region and a second device region. The first semiconductor stack is located on the semiconductor substrate over the first device region, and has first channels. The second semiconductor stack is located on the semiconductor substrate over the second device region, and has second channels. A total number of the first channels is greater than a total number of the second channels. The first gate structure encloses the first semiconductor stack. The second gate structure encloses the second semiconductor stack.

Abstract: Disclosed herein are IC structures, packages, and devices that include thin-film transistors (TFTs) integrated on the same substrate/die/chip as III-N transistors. An example IC structure includes an III-N semiconductor material provided over a support structure, a III-N transistor provided over a first portion of the III-N material, and a TFT provided over a second portion of the III-N material. Because the III-N transistor and the TFT are both provided over a single support structure, they may be referred to as “integrated” transistors. Because the III-N transistor and the TFT are provided over different portions of the III-N semiconductor material, and, therefore, over different portion of the support structure, their integration may be referred to as “side-by-side” integration. Integrating TFTs with III-N transistors may reduce costs and improve performance, e.g., by reducing losses incurred when power is routed off chip in a multi-chip package.

Abstract: The present disclosure relates to a semiconductor chip that includes a substrate, a metal layer, and a number of component portions. Herein, the substrate has a substrate base and a number of protrusions protruding from a bottom surface of the substrate base. The substrate base and the protrusions are formed of a same material. Each of the protrusions has a same height. At least one via hole extends vertically through one protrusion and the substrate base. The metal layer selectively covers exposed surfaces at a backside of the substrate and fully covers inner surfaces of the at least one via hole. The component portions reside over a top surface of the substrate base, such that a certain one of the component portions is electrically coupled to a portion of the metal layer at the top of the at least one via hole.

Abstract: High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region.

Abstract: Disclosed is a nitride semiconductor apparatus including a substrate, a first nitride semiconductor layer disposed above the substrate, and constituting an electron transit layer, a second nitride semiconductor layer formed on the first nitride semiconductor layer, and constituting an electron supply layer, a nitride semiconductor gate layer disposed on the second nitride semiconductor layer having a ridge portion at at least an area thereof, and containing an acceptor-type impurity, a gate electrode disposed on the ridge portion, a source electrode and a drain electrode disposed opposite to each other, with the ridge portion interposed therebetween, on the second nitride semiconductor layer, and a strip-shaped insulator disposed between the substrate and a surface layer portion of the first nitride semiconductor layer, and extending along a length direction of the ridge portion when viewed in plan.

Abstract: Provided are a semiconductor element and a semiconductor device capable of achieving on-resistance reduction and miniaturization. The semiconductor element is used in a semiconductor switch for protecting an electric circuit, and includes a semiconductor substrate SB, a MOS transistor Tr provided on the semiconductor substrate SB, and a source electrode SE provided on a front surface 2a side of the semiconductor substrate SB. The MOS transistor Tr includes an n-type source region 8 connected to the source electrode SE, an n-type drift region 21 arranged away from the source region 8, and a p-type well region 31 arranged between the source region 8 and the drift region 21. The source region 8 is interposed between the source electrode SE and the well region 31.

Abstract: A light-emitting device includes: a light-emitting element including a first surface provided as a light extraction surface, a second surface opposite to the first surface, a plurality of third surfaces between the first surface and the second surface, and a positive electrode and a negative electrode at the second surface; a light-transmissive member disposed at the first surface; and a bonding member disposed between the light-emitting element and the light-transmissive member and covering from the first surface to the plurality of third surfaces of the light-emitting element to bond the light-emitting element and the light-transmissive member. The bonding member is made of a resin that contains nanoparticles. The nanoparticles have a particle diameter of 1 nm or more and 30 nm or less and a content of 10 mass % or more and 20 mass % or less.

Abstract: Non-limiting examples of the present disclosure describe a convolutional neural network (CNN) architecture configured to evaluate conversational relevance of query-response pairs. A CNN model is provided that can include a first branch, a second branch, and multilayer perceptron (MLP) layers. The first branch includes convolutional layers with dynamic pooling to process a query. The second branch includes convolutional layers with dynamic pooling to process candidate responses for the query. The query and the candidate responses are processed in parallel using the CNN model. The MLP layers are configured to rank query-response pairs based on conversational relevance.

Abstract: Systems and methods for estimating a property of an error in a circuit implemented on an n-qubit quantum system are provided, where the circuit comprises a gate set that comprises a first subset () and a second subset () of elementary gates. The first subset comprises a third subset () of elementary gates each of which consists of an n-fold tensor product of a plurality of single qubit gates. A first procedure is executed that comprises preparing the system in a state ? and then applying D1=T1 to the system. The procedure further comprises, for each respective clock cycle t in clock cycles t?{2, . . . , m+1}, (a) applying H to the system, where H is an elementary gate in the second subset, and then (b) applying a gate Dt=TtGHTt?1†H† to the system, where Dt is an element of the first subset. The procedure further comprises performing a measurement readout R.