Abstract: The embodiments of the application provides a polar code rate matching method and apparatus. The method includes: obtaining, by a communications device, to-be-encoded information; determining, by the communications device, a to-be-used rate matching manner based on the code rate, a code rate threshold, a target code length, and a target code length threshold, where the rate matching manner is a puncturing manner or a shortening manner; and rate matching, by the communications device based on the determined rate matching manner, a polar code of the to-be-encoded information.

Abstract: A method for detecting a code word is proposed, wherein the code word is a code word of one of at least two codes, wherein n states are read from memory cells of a memory, respectively. The n states are determined in a time domain for each of the at least two codes, wherein additionally n states are read from further memory cells and at least one reference value is determined therefrom and wherein the at least one reference value is taken as a basis for determining which of the at least two codes is the correct code. A corresponding device is furthermore specified.

Abstract: A method for execution by a compaction management system includes determining observed compaction information based on compaction observed in at least one storage device during an observed timeframe. An estimated compaction rate is generated for a first future timeframe based on the observed compaction information. An updated ingest rate is generated for the first future timeframe based on a current ingest rate and the estimated compaction rate. A first proper subset of a set of data to be written to the at least one storage device is generated based on the updated ingest rate. Storage of the first proper subset in the at least one storage device is facilitated during the first future timeframe. Storage of a remaining proper subset of the set of data in an elastic buffer is facilitated during the first future timeframe, where the elastic buffer utilizes a memory of the compaction management system.

Abstract: A semiconductor device includes an address conversion circuit which generates the second address for storing an error detecting code in a memory based on the first address for storing data; a write circuit which writes data at the first address and writes an error detecting code at the second address; and a read circuit which reads data from the first address, reads the error detecting code from the second address, and detects an error based on the data and the error detecting code. The address conversion circuit generates an address as the second address by modifying the value of at least one bit of the first address so as to offset the storing position of the error detecting code to the storing position of the data, and by inverting the value of or permutating the order of the prescribed number of bits among the other bits.

Abstract: Embodiments of this application provide a polar code rate matching method and apparatus, and a communications apparatus. The rate matching method includes: determining N to-be-encoded bits, where the N to-be-encoded bits include N1 information bits, and both N1 and N are positive integers; encoding the N to-be-encoded bits to obtain N encoded bits; obtaining a first puncturing sequence based on an information bit length N1, the quantity N of the encoded bits, and a quantity Q of to-be-punctured bits; and performing a puncturing operation on the N encoded bits based on the first puncturing sequence to implement a rate matching. To-be-punctured bits indicated in the first puncturing sequence are obtained based on the information bit length N1, the quantity N of the encoded bits, and the quantity Q of the to-be-punctured bits, and are not generated randomly.

Abstract: The present invention provides an encoding circuit of a flash memory controller, wherein the encoding circuit includes an auxiliary data generating circuit and an encoder. In the operations of the encoding circuit, the auxiliary data generating circuit is configured to receive a plurality of data chunks to generate auxiliary data corresponding to the data chunks. The encoder is configured to encode the data blocks to generate parity codes according to a parity check matrix, and to use the auxiliary data to replace a portion of the parity codes to generate adjusted parity codes, wherein the data chunks and the adjusted parity codes are written into a flash.

Abstract: The purpose of the present invention is to provide a display device for a vehicle which is capable of avoiding NAND flash memory data loss. Provided is a display device for a vehicle, comprising: a display unit 6 which displays vehicle information; a NAND flash memory 1 which stores, together with an error correction code, data which is related to the display of the display unit 6; and a control unit (for example, a second control unit 2) which causes the display 6 to display the vehicle information using said data. When a load upon the vehicle is low, such as when a switch key for commencing the driving of the vehicle is off, the control unit (for example, a first control unit 3), as a data loss avoidance process, assesses, with the error correction code, whether an error is present in the data which is recorded in the NAND flash memory 1. If the error is present in the data, the control unit (for example, the first control unit 3) corrects the error with the error correction code.

Abstract: In a multi-antenna communication system using LDPC codes, a simple method is used to effectively improve the received quality by performing a retransmittal of less data without restricting applicable LDPC codes. In a case of a non-retransmittal, a multi-antenna transmitting apparatus transmits, from two antennas, LDPC encoded data formed by LDPC encoding blocks. In a case of a retransmittal, the multi-antenna transmitting apparatus uses a transmission method, in which the diversity gain is higher than in the previous transmission, to transmit only a part of the LDPC encoded data as previously transmitted. For example, the only the part of the LDPC encoded data to be re-transmitted is transmitted from the single antenna.

Abstract: Provided is an error correction device including an encoding circuit configured to encode a plurality of error correction code sequences, in which the encoding circuit includes a plurality of encoding circuits connected in parallel, and is configured to execute encoding processing for the plurality of error correction code sequences through use of all the plurality of encoding circuits by adjusting an output bus width and a frequency of an operation clock with respect to a difference in transmission rate for any payloads input in one or more systems.

Abstract: A proposed linear time compactor (LTC) with a means of significantly reducing the X-masking effect for designs with X's and supports high levels of test data compression where: 1) The LTC consists of two parts that are unloaded into a tester through an output serializer. 2) The first part is unloaded per t shift cycles while the second part is unloaded once per test pattern. 3) One part of the LTC divides scan chains into groups such that X-masking effect between groups of scan chains is impossible. 4) One part of LTC divides shift cycles into groups such that X-masking effect between groups of shift cycles is impossible. Consequently, the X-masking effect in the proposed LTC is significantly reduced.

Abstract: System and method for autonomous trouble shooting of a unit under test (UUT) having a plurality of replaceable components include: a test station that stores an artificial intelligence (AI) program and a knowledge database (KDB) including acceptable test results for each test point represented by an acceptable test vector, a test probe to test the circuit card assembly; and an operator station to send commands to the test station via the communication network to teach the AI program to capture and store the acceptable test result for each test point of the UUT by the test probe, in the KDB, wherein the AI program commands the test probe to test the UUT, stores the test results in a test result vector, compares the test result vector with the stored acceptable test vector, and displays recommendation as which replaceable component in the UUT to be repaired or replaced.

Abstract: Techniques for a power saving scannable latch output driver in an integrated circuit (IC) are described herein. An aspect includes receiving, by a circuit comprising a scannable latch, a scan signal. Another aspect includes, based on the scan signal being enabled, turning on a scan output driver of the scannable latch, wherein a scan input of the scannable latch propagates through the scannable latch to a scan output based on the scan output driver being turned on. Another aspect includes, based on the scan signal being disabled, turning off the scan output driver, wherein the scan output driver comprises a first p-type field effect transistor (PFET) and a first n-type field effect transistor (NFET), wherein a gate of the first PFET and a gate of the first NFET are connected to an output of a latch of the scannable latch.

Abstract: Embodiments of this application disclose a polar coding method, apparatus, and device, so as to reduce storage overheads of a system. A sequence for polar coding is obtained based on a length M of a target polar code, wherein the sequence comprises L sequence numbers, ordering of the L sequence numbers in the sequence is the same as ordering of the L sequence numbers in a maximum mother code sequence, wherein the maximum mother code sequence is obtained by sorting N sequence numbers of N polarized channels in ascending order or descending order of reliability metrics, wherein L and N are integer power of 2, M is smaller than or equal to L, L is smaller than or equal to N.

Abstract: A semiconductor memory device includes an error correction code (ECC) engine, a memory cell array, an input/output (I/O) gating circuit and a control logic circuit. The memory cell array includes a normal cell region configured to store main data and a parity cell region configured to selectively store parity data which the ECC engine generates based on the main data, and sub data received from outside of the semiconductor memory device. The control logic circuit controls the ECC engine to selectively perform an ECC encoding and an ECC decoding on the main data and controls the I/O gating circuit to store the sub data in at least a portion of the parity cell region.

Abstract: Embodiments of the present application provide a method and an apparatus for generating a code word using a Polar code encoding manner. A sequence has N bits, in which K bits are information bits. A matrix of N rows×N columns is used for encoding the sequence. Each row of the matrix has a weight that equals to total number of non-zero elements in the row, and ith row of the matrix corresponds to ith bit position of the sequence, i=1, 2, . . . , N. Each bit position of the N-bit sequence has a reliability. The K bit positions of the sequence that are occupied by the K information bits are selected according to reliabilities of the bit positions of the sequence and weights of the rows of the matrix. The code word is generated by multiplying the sequence with the matrix.

Abstract: Provided are a computer program product, system, and method for mirroring information on modified data from a primary storage controller to a secondary storage controller for the secondary storage controller to use to calculate parity data. New primary parity data is calculated from modified data for a primary group of tracks in the primary storage and difference data from the modified data and a pre-modified version of the modified data. The difference data and one of the modified data and the new primary parity data are sent to the secondary storage controller to cause the secondary storage controller to write new secondary parity data and the modified data to a secondary group of tracks at the secondary storage. The modified data and the new primary parity data are written to the primary group of tracks in the primary storage.

Abstract: In one embodiment, the disclosure teaches an apparatus including a memory array and a processor in communication with the memory array. The processor is configured to determine health scores of blocks of the memory array, where the health scores indicate the health of the blocks. The processor also is configured to receive data from a host, and select an interleaving scheme for programming the data based on the data type and a block to which the data is written based on the health scores. In one embodiment, sequential type data is written to unhealthy blocks and non-sequential data is written to healthy blocks.

Abstract: A control unit of a multipath data transportation system that optimizes the load of the multiple communication paths of this system when the system transmits a data segment over these paths in parallel with forward error correction. The control unit determines an optimized number of packets to send over each path based on a prediction of quality for each path. The transmitted packets include systematic packets and coded packets.

Abstract: A method for execution by an integrity processing unit includes performing a deterministic function on data for storage to produce an integrity value. The data and the integrity value are combined in accordance with a combining function to produce a data package. The processing system determines an encryption approach in response to determining to encrypt the data package. The data package is encrypted in accordance with the encryption approach to produce a secure package. The secure package is encoded to produce a set of slices. The set of slices is decoded to reproduce the secure package. The secure package is decrypted to reproduce the data package. The data package is de-combined in to generate reproduced data and a received integrity value. The deterministic function is performed on the data to produce a calculated integrity value, and the received integrity value is compared to the calculated integrity value.

Abstract: A first score and a second score for each scan cell are first determined based on numbers of test cubes in a set of test cubes having a specified value of “1” and a specified value of “0” for the each scan cell, respectively. A ranking score for each test cube in the set of test cubes is then determined based on combining the first scores and the second scores corresponding to specified bits of the each test cube in the set of test cubes. Test cubes in the set of test cubes are merged according to a sequence based on the ranking scores in a test pattern generation process.