Abstract: Various implementations described herein relate to systems and methods for decoding data stored in a non-volatile storage device, including determining features for each of a plurality of component codes corresponding to the data by decoding each of the plurality of component codes, determining an extrinsic value output for each of the component codes based on the features, and after the extrinsic value output for each of the component codes is determined, decoding each of the plurality of component codes based on the extrinsic value outputs of all other component codes of the component codes. Each of the component codes depends on all other component codes.

Abstract: A network interface controller including a data alignment module, a boundary determination module and a checksum module is provided. The data alignment module receives raw data and re-combines the raw data as first valid data, wherein the raw data includes a first layer protocol segment and a second layer protocol segment. The boundary determination module receives the raw data in parallel to the data alignment module and performs a boundary determination operation on the raw data to generate a boundary information indicating a boundary between the first layer protocol segment and the second layer protocol segment. The checksum module is coupled to the data alignment module and configured to disassemble the first valid data as second valid data and calculate a checksum according to the boundary information and the second valid data.

Abstract: Aspects of the disclosure relate to wireless communication systems configured to provide techniques for multiplexing dedicated control information for a plurality of users in a single information block and polar coding the information block to produce a polar code block of dedicated control information for transmission over a wireless air interface. The information block may further include group cyclic redundancy check (CRC) information for the information block and individual CRC information for each dedicated control information.

Abstract: A method for correcting an error of a received signal is provided. The method includes: determining a target degree based upon a length of the received signal; obtaining plural primitive polynomials each having a degree equal to the target degree; selecting one of the primitive polynomials as a target polynomial; defining plural syndromes according to the received signal; generating a group of product values based on the syndromes; obtaining plural coefficient polynomials based on the product values; obtaining monomial trace coefficients based on the coefficient polynomials; generating an error correction value based on the monomial trace coefficients; and correcting the error based on the error correction value.

Abstract: In general, embodiments of the technology relate to a method for characterizing persistent storage. The method includes selecting a sample set of physical addresses in a solid state memory module, where the sample set of physical addresses is associated with a region in the solid state memory module (SSMM). The method further includes issuing a write request to the sample set of physical addresses, after issuing the write request, issuing a request read to the sample set of physical addresses to obtain a copy of the data stored in the sample set of physical addresses, obtaining an error parameter for the copy of the data, determining a calculated P/E cycle value for the SSMM using at least the error parameter; and storing the calculated P/E cycle value in the SSMM.

Abstract: Examples disclosed herein relate to a fault-tolerant dot product engine. The fault-tolerant dot product engine has a crossbar array having a number l of row lines and a number n of column lines intersecting the row lines to form l×n memory locations, with each memory location having a programmable memristive element and defining a matrix value. A number l of digital-to-analog converters are coupled to the row lines of the crossbar array to receive an input signal and a number n of analog-to-digital converters are coupled to the column lines of the crossbar array to generate an output signal. The output signal is a dot product of the input signal and the matrix values in the crossbar array, wherein a number m<n of the n column lines in the crossbar array are programmed with matrix values used to detect errors in the output signal.

Abstract: Embodiments of this application provide a method and an apparatus for constructing a coding sequence. The method includes: storing a reliability sequence corresponding to a basic sequence, where a length of the reliability sequence corresponding to the basic sequence is less than or equal to a length of a reliability sequence corresponding to a mother code sequence; storing a reliability reference sequence, where the reliability reference sequence includes at least one element remaining after the reliability sequence corresponding to the basic sequence is excluded from the reliability sequence corresponding to the mother code sequence; and constructing a coding sequence by using the reliability sequence corresponding to the basic sequence and an element in the reliability reference sequence. During implementation of this application, during storage, only the reliability sequence corresponding to the basic sequence and the reliability reference sequence are stored.

Abstract: A method for detecting faults in substring search operations includes providing, using a processor unit including vector registers of M vector elements each, an M×M matrix of comparators for characterwise comparison of the elements of a reference string stored in a first one of the vector registers and a target string stored in a second one of the vector registers. A vector element is an n-bit element for encoding a character. A resulting bit vector is generated using comparison performed by the M×M matrix. The resulting bit vector indicates characters of the target string that fully match the reference string and indicates characters of the target string that partially match the reference string. Fault detection in the substring search operations is performed by utilizing the resulting bit vector.

Abstract: This application provides an encoding method. The method includes: determining a frame of an outer code of to-be-encoded data, where the frame of the outer code includes a data information code and a check code of the data information code, the frame of the outer code is divided into Q data blocks, each data block in the Q data blocks includes W bits, and W and Q are integers greater than 0; and encoding the Q data blocks to obtain Q codewords of an inner code, where the Q data blocks are in a one-to-one correspondence with the Q codewords of the inner code, a first codeword in the Q codewords of the inner code includes a first data block and a check code of the first data block, the first codeword is any codeword in the Q codewords of the inner code.

Abstract: Techniques and apparatus are provided for efficiently generating multiple lifted low-density parity-check (LDPC) codes for a range of block lengths and having good performance. A method for wireless communications by a transmitting device generally includes selecting integer lifting values for a first lifting size value Z, selected from a range of lifting size values, wherein the selected integer lifting value is greater than a maximum lifting size value of the range of lifting size values; determining one or more integer lifting values for generating at least a second lifted LDPC code having a second lifting size value based on an operation involving the second lifting size value and the selected one or more integer lifting values for generating the first lifted LDPC code; encoding a set of information bits based on the second lifted LDPC to produce a code word; and transmitting the code word.

Abstract: A communications apparatus to receive a composite signal including a desired signal and interferer signals, where the desired signal may include desired symbols and the interferer signals may include interferer symbols. The system may include N frameworks, each framework may include a detector to partition the desired symbols and the interferer symbols based on an interference severity into a dominant group and a non-dominant group, and to generate A Posteriori Probabilities (APP) of the desired symbols and the interferer symbols. The detector of each of the N frameworks generates the APP based on a feedback of a priori probabilities from each of the N frameworks.

Abstract: A flash memory system may include a flash memory and a circuit for performing operations of the flash memory. The circuit may be configured to estimate slope information of a plurality of threshold voltage samples based on a first read operation on the flash memory with a first reference voltage. The circuit may be configured to generate soft information based on the estimated slope information. The circuit may be configured to decode a result of a second read operation on the flash memory based on the soft information.

Abstract: A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to perform a low-density parity check (LDPC) encoding on input bits using a parity check matrix to generate an LDPC codeword comprising information word bits and parity bits; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.

Abstract: A RAID storage controller storage-device-assisted data update system includes a RAID storage controller device coupled to a host system and RAID storage devices in a “look aside” RAID storage controller device configuration. Based on command(s) from the RAID storage controller device, a first RAID primary data storage device may perform a first DMA operation to access first primary data stored on the host system, and write the first primary data to its first buffer subsystem. The first RAID primary data storage device may then perform a first XOR operation using the first primary data stored in its first buffer subsystem and second primary data stored in its first storage subsystem in order to produce first interim parity data, and write the first interim parity data to its second buffer subsystem. The first RAID primary data storage device may then update the second primary data with the first primary data.

Abstract: Various embodiments of the invention relate to continuously verifying semiconductor device state integrity. A counter is combined to form part of the Cyclic Redundancy Check (CRC) calculation for control register within the semiconductor device. The counter is initialized to zero and resets after a predetermined number of cycles. The counter value is added to the currently calculated CRC value to get a combined CRC value. Every time a CRC value is calculated for the register bank, the counter value is updated, e.g. incremented. If the CRC calculation is repeated enough times, the counter value will reach its maximum value, and then roll over to its initial value of zero. If no errors occur in the register bank, the combined CRC value at the rolling over point will match an initial combined CRC value. Such a repetitive pattern of the combined CRC value may be used to continuously monitor control register integrity.

Abstract: The embodiments of the application provides a polar code rate matching method and apparatus. The method includes: obtaining, by a communications device, to-be-encoded information; determining, by the communications device, a to-be-used rate matching manner based on the code rate, a code rate threshold, a target code length, and a target code length threshold, where the rate matching manner is a puncturing manner or a shortening manner; and rate matching, by the communications device based on the determined rate matching manner, a polar code of the to-be-encoded information.

Abstract: A data-transfer-based RAID data update system includes a RAID storage controller device coupled to a host system and RAID storage devices. The RAID storage controller device receives a command that is associated with a data update on at least one of the RAID storage devices from the host system. The RAID storage controller device then determines, from a plurality of RAID data update techniques that are available to execute the command and perform the data update on the at least one of the RAID storage devices, a first RAID data update technique that is included in the plurality of RAID data update techniques and that requires the lowest number of data transfers to execute the command and perform the data update. The RAID storage controller device then causes the command to be performed using the first RAID data update technique to provide the data update.

Abstract: A semiconductor memory system including: a semiconductor memory device suitable for storing a codeword; and an LDPC decoder suitable for decoding the codeword to generate decoded data, wherein the LDPC decoder includes: a message passing decoding component suitable for performing a first decoding operation of decoding the codeword, and calculating the minimum value among numbers of UCNs; and an error path detection component suitable for detecting error path candidates using a tree in which each of UCNs corresponding to the minimum value is set to a root node, sorting the detected error path candidates in ascending order of maximum LLRs, resetting symbol values and LLRs of variable nodes in the error path candidates, and providing the message passing decoding unit with information on the reset symbol values and LLRs.

Abstract: This disclosure describes a programmable device, referred to generally as a data processing unit, having multiple processing units for processing streams of information, such as network packets or storage packets. This disclosure also describes techniques that include enabling data durability coding on a network. In some examples, such techniques may involve storing data in fragments across multiple fault domains in a manner that enables efficient recovery of the data using only a subset of the data. Further, this disclosure describes techniques that include applying a unified approach to implementing a variety of durability coding schemes. In some examples, such techniques may involve implementing each of a plurality of durability coding and/or erasure coding schemes using a common matrix approach, and storing, for each durability and/or erasure coding scheme, an appropriate set of matrix coefficients.

Abstract: A computing device includes an interface configured to interface and communicate with a dispersed storage network (DSN), a memory that stores operational instructions, and processing circuitry operably coupled to the interface and to the memory. The processing circuitry is configured to execute the operational instructions to perform various operations and functions. The computing device detects a total number of errors that is associated with a set of memory devices of one or more sets of storage units (SUs) within a DSN that distributedly store a set of encoded data slices (EDSs). When the total number of errors compares unfavorably to a priority error threshold level, the computing device indicates that a minimum number of error-free EDSs are available of the set of EDSs. The computing device also selects a mechanism for data retention process from a plurality of mechanisms for data retention process and executes it.