Patents Examined by Mujtaba M. Chaudry
  • Patent number: 10331518
    Abstract: A method for execution by an integrity processing unit includes performing a deterministic function on data for storage to produce an integrity value. The data and the integrity value are combined in accordance with a combining function to produce a data package. The processing system determines an encryption approach in response to determining to encrypt the data package. The data package is encrypted in accordance with the encryption approach to produce a secure package. The secure package is encoded to produce a set of slices. The set of slices is decoded to reproduce the secure package. The secure package is decrypted to reproduce the data package. The data package is de-combined in to generate reproduced data and a received integrity value. The deterministic function is performed on the data to produce a calculated integrity value, and the received integrity value is compared to the calculated integrity value.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: June 25, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jason K. Resch, Wesley B. Leggette
  • Patent number: 10326555
    Abstract: Embodiments of this application disclose a polar coding method, apparatus, and device, so as to reduce storage overheads of a system. A sequence for polar coding is obtained based on a length M of a target polar code, wherein the sequence comprises L sequence numbers, ordering of the L sequence numbers in the sequence is the same as ordering of the L sequence numbers in a maximum mother code sequence, wherein the maximum mother code sequence is obtained by sorting N sequence numbers of N polarized channels in ascending order or descending order of reliability metrics, wherein L and N are integer power of 2, M is smaller than or equal to L, L is smaller than or equal to N.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: June 18, 2019
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Rong Li, Gongzheng Zhang, Ying Chen, Xiaocheng Liu, Jun Wang
  • Patent number: 10320421
    Abstract: Field error correction coding is particularly suitable for applications in non-volatile flash memories. We describe a method for error correction encoding of data to be stored in a memory device, a corresponding method for decoding a codeword matrix resulting from the encoding method, a coding device, and a computer program for performing the methods on the coding device, using a new construction for high-rate generalized concatenated (GC) codes. The codes, which are well suited for error correction in flash memories for high reliability data storage, are constructed from inner nested binary Bose-Chaudhuri-Hocquenghem (BCH) codes and outer codes, preferably Reed-Solomon (RS) codes. For the inner codes extended BCH codes are used, where only single parity-check codes are applied in the first level of the GC code. This enables high-rate codes.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: June 11, 2019
    Assignee: HYPERSTONE GMBH
    Inventors: Juergen Freudenberger, Christoph Baumhof, Jens Spinner
  • Patent number: 10313095
    Abstract: A control system includes an arithmetic device configured of an A system arithmetic unit including a data dividing unit, a B system arithmetic unit including a data dividing unit, and an A system communication control unit including a data combining unit and a collation unit, wherein the A system arithmetic unit and the B system arithmetic unit have a duplex configuration, the A system arithmetic unit and the B system arithmetic unit are separated by a gap, a frame output from the A system arithmetic unit is transmitted to a B system communication control unit through the A system communication control unit and an interface element, and a frame output from the B system arithmetic unit is transmitted to the A system communication control unit through the B system communication control unit and an interface element.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: June 4, 2019
    Assignee: Hitachi, Ltd.
    Inventors: Katsunobu Natori, Tetsuya Nakajima, Satoshi Nishikawa, Masahiro Shiraishi, Hideo Harada
  • Patent number: 10312940
    Abstract: The present technology relates to a data processing apparatus and a data processing method that are able to secure good communication quality in data transmission using an LDPC code. One symbol is mapped to one of 16 signal points prescribed in 16APSK, with code bits of four bits of an LDPC code having a code length of 16200 bits and a code rate of 7/15 as one symbol. 16 signal points prescribed in 16APSK are four signal points on an inner circle and 12 signal points on an outer circle, and a radius ratio of the inner circle and the outer circle is 5.25. The present technology may be applied to, for example, a case of performing data transmission using an LDPC code.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: June 4, 2019
    Assignee: Sony Corporation
    Inventors: Nabil Sven Loghin Muhammad, Yuji Shinohara, Lachlan Michael, Yuichi Hirayama, Makiko Yamamoto
  • Patent number: 10313057
    Abstract: Certain aspects of the present disclosure relate to techniques and apparatus for increasing decoding performance and/or reducing decoding complexity. An exemplary method generally includes obtaining a payload to be transmitted, partitioning the payload into a plurality of payload sections, deriving redundancy check information for each respective payload section of the plurality of payload sections, merging the redundancy check information for each payload section with the plurality of payload sections to form a sequence of bits, and generating a codeword by encoding the sequence of bits using an encoder. Other aspects, embodiments, and features are also claimed and described.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: June 4, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Jamie Menjay Lin, Yang Yang, Joseph Binamira Soriaga
  • Patent number: 10305631
    Abstract: A system for frame synchronization. Coarse synchronization is performed, in some embodiments, by using soft bit decisions to generate a list of candidate frame start positions, each with an associated estimated probability. The candidate frame start positions are then tested by decoding the frame data, and a frame start position for which a criterion of decoding success is met is selected. Fine synchronization is performed, in some embodiments, by using an encoded synchronization word in the encoded frame data. A first decoding pass is used to identify the position of the synchronization word. The start of the frame is inferred from the position of the synchronization word, and a second decoding pass, using the correct initial state, in the decoder, at the start of the encoded frame data, is performed.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: May 28, 2019
    Assignee: RAYTHEON COMPANY
    Inventor: Mostofa K. Howlader
  • Patent number: 10305634
    Abstract: A plurality of units have a transmitter and a receiver. The transmitter puts the unit's own data string into a coding data array using first array information, and calculates an error-correcting code based on the data array in which 0 is put except for the data string. The receiver decodes a data array in which a data string is put into the coding data array based on second array information, using an error-correcting code. The transmitter adds the unit's own data string to a data string, puts the unit's own data string into the coding data array using the first array information on the data string, calculates an error-correcting code for the data array in which 0 is put except for the data string, and determines an error-correcting code of a transmission packet by addition of an error-correcting code of a received packet and the calculated error-correcting code.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: May 28, 2019
    Assignee: FANUC CORPORATION
    Inventor: Kazuhiro Satou
  • Patent number: 10295595
    Abstract: Configuration values for Lookup tables (LUTs) and programmable routing switches in an FPGA are provided by means of a number of flip flops arranges in a shift register. This shift register may receive test values in a factory test mode, and operational configuration values (implementing whatever functionality the client requires of the FPGA) in an operational mode. The bitstreams are provided at one end of the shift register, and clocked through until the last flip flop receives its value. Values may also be clocked out at the other end of the shift register to be compared to the initial bitstream in order to identify corruption of stored values e.g. due to radiation exposure. A clock gating architecture is proposed for loading data to or reading data from specific selected shift registers.
    Type: Grant
    Filed: October 7, 2016
    Date of Patent: May 21, 2019
    Assignee: MENTA
    Inventors: Laurent Rouge, Julien Eydoux, Marcello Giuffre
  • Patent number: 10291260
    Abstract: Decoding of a first message is disclosed, wherein first and second messages are encoded by a code (represented by a state machine) to produce first and second code words, which are received over a communication channel. A plurality of differences (each corresponding to a hypothesized value of a part of the first message) between the first and second messages are hypothesized. An initial code word segment is selected having, as associated previous states, a plurality of initial states (each associated with a hypothesized difference and uniquely defined by the hypothesized value of the part of the first message).
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: May 14, 2019
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
    Inventors: Joakim Axmon, Bengt Lindoff, Anders Wallén
  • Patent number: 10291262
    Abstract: Decoding of a first message is disclosed, wherein first and second messages are encoded by a code (represented by a state machine) to produce first and second code words, which are received over a communication channel. A plurality of differences (each corresponding to a hypothesized value of a part of the first message) between the first and second messages are hypothesized. An initial code word segment is selected having, as associated previous states, a plurality of initial states (each associated with a hypothesized difference and uniquely defined by the hypothesized value of the part of the first message).
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: May 14, 2019
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
    Inventors: Joakim Axmon, Bengt Lindoff, Anders Wallén
  • Patent number: 10289479
    Abstract: Hardware accelerator memory address translation fault resolution is provided. A hardware accelerator and a switchboard are in communication with a processing core. The hardware accelerator determines at least one memory address translation related to an operation having a fault. The switchboard forwards the operation with the fault memory address translation from the hardware accelerator to a second buffer. The operation and the fault memory address translation are flushed from the hardware accelerator, and the operating system repairs the fault memory address translation. The switchboard forwards the operation with the repaired memory address translation from the second buffer to a first buffer and the hardware accelerator executes the operation with the repaired address.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: May 14, 2019
    Assignee: International Business Machines Corporation
    Inventors: Lakshminarayana B. Arimilli, Richard L. Arndt, Bartholomew Blaner
  • Patent number: 10290353
    Abstract: NAND cell error remediation technologies are disclosed. The remediation technologies are applicable to 3D NAND. In one example, a storage device may include a processor and a memory device comprising NAND flash memory. The processor is configured to detect an error condition associated with a first page of the NAND flash memory, and determine whether the error condition is associated with a read disturbance or with a retention error. The processor is configured to initiate, if the error condition is associated with the read disturbance, a refresh operation with respect to the page to write data stored at the first page to a second page of the NAND flash memory, and initiate, if the error condition is associated with the retention error, a reprogramming operation with respect to the page to rewrite the data stored at the first page to the first page of the NAND flash memory.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: May 14, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Seung-Hwan Song, Viacheslav Anatolyevich Dubeyko, Zvonimir Z. Bandic
  • Patent number: 10285166
    Abstract: A method by a terminal, method by a base station, a terminal, and a base station are provided. The method by the terminal includes transmitting two transport blocks; and if one of the two transport blocks is negatively acknowledged (NACKed) and a physical downlink control channel (PDCCH) including control information is not detected, adjusting retransmission for the NACKed transport block using a precoding index 0 and a number of layers corresponding to the NACKed transport block.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: May 7, 2019
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Jin-Kyu Han, Youn Sun Kim
  • Patent number: 10282251
    Abstract: A system and method is disclosed for managing firmware in a non-volatile memory system having a multi-processor controller. The controller may be configured with a plurality of processors. Each of the plurality of processors may retrieve and check the integrity of firmware for a respective one of the other processors while the processor engaged in checking the respective one of the other processors is in an idle state.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: May 7, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Ilya Gusev, Yevgeny Zagalsky, Beniamin Kantor, Shay Benisty, Judah Gamliel Hahn
  • Patent number: 10284332
    Abstract: A spur cancelation system includes error circuitry, inverse spur circuitry, and injection circuitry. The error circuitry is configured to generate an error signal based at least on a first transceiver signal in a transceiver signal processing chain. The inverse spur circuitry is configured to, based at least on the error signal, determine a gain and a phase of a spur signal in the transceiver signal and generate an inverse spur signal based at least on the gain and the phase of the spur signal. The injection circuitry is configured to inject the inverse spur signal to cancel a spur in a second transceiver signal in the transceiver signal processing chain.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: May 7, 2019
    Assignee: Intel IP Corporation
    Inventors: Rotem Avivi, Michael Kerner, Assaf Gurevitz
  • Patent number: 10270463
    Abstract: A wireless device generates a High Efficiency Signal B (HE-SIG-B) field by Block Convolution Code (BCC) encoding and rate-matching a BCC block of the HE-SIG-B field, generates a Physical Layer Protocol Data Unit (PPDU) including the HE-SIG-B field, and transmits the PPDU. A total number N is a total number of bits of the HE-SIG-B field that precede the BCC block, and is greater than 0. The BCC block has a puncturing pattern depending on the total number N. A wireless device receives a PPDU. The PPDU includes an HE-SIG-B field that includes an encoded BCC block. The wireless device de-rate-matches the encoded BCC block having a puncturing pattern depending on a total number N. The total number N is a total number of decoded bits of the HE-SIG-B field that preceded the BCC block, and the total number N is greater than 0.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: April 23, 2019
    Assignee: NEWRACOM, INC.
    Inventors: Dae Won Lee, Yujin Noh, Sungho Moon, Young Hoon Kwon
  • Patent number: 10263814
    Abstract: A multiple access scheme is described. A first bit stream is scrambled from a first terminal according to a first scrambling signature. A second bit stream is scrambled from a second terminal according to a second scrambling signature, wherein the first bit stream and the second bit stream are encoded using a low rate code. The first scrambling signature and the second scrambling signature are assigned, respectively, to the first terminal and the second terminal to provide a multiple access scheme.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: April 16, 2019
    Assignee: Hughes Network Systems, LLC
    Inventors: Mustafa Eroz, Lin-Nan Lee, Lakshmi Iyer, Neal Becker
  • Patent number: 10255986
    Abstract: The present invention provides a computer implemented method, system, and computer program product of assessing in-field reliability of computer memories. In an embodiment, the present invention includes taking control of a portion of a computer memory circuit, utilizing a portion of a computer memory bus associated with the portion of the computer memory circuit, moving computer memory circuit data stored in the portion of the computer memory circuit to a host computer storage device, executing a set of logical operations assessing reliability of the portion of the computer memory circuit, resulting in assessment data stored in a reliability error monitor (REM) computer storage device, transmitting the stored assessment data from the REM computer storage device to a computer memory controller circuit, and in response to the transmitting, moving the moved computer memory circuit data from the host computer storage device back to the portion of the computer memory circuit.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: April 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Diyanesh B. Chinnakkonda Vidyapoornachary, Kyu-hyoun Kim, Anil B. Lingambudi, Adam J. McPadden
  • Patent number: 10247777
    Abstract: “Shoot-through” timing failures in a scan chain of a defective semiconductor integrated circuit corrupt test pattern data used to perform failure analysis. Methods and procedures are provided to detect “shoot-through” conditions, determine the number of shoot-through scan cells, and to determine the location of the shoot-through cells within a scan chain. Reset test pattern results can be analyzed to identify candidate locations of shoot-through cells and when combined with candidate cell locations from analysis of physical clock distribution trees and potential clock-skew issues, the exact location of all shoot-through cells can be determined. Methods are also provided to use shoot-through cell locations to identify the defective clock net containing the physical defect causing the clock skew conditions needed to produce shoot-through timing failures.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: April 2, 2019
    Assignee: TESEDA CORPORATION
    Inventor: Theodore Clifton Bernard