Abstract: A semiconductor device may include a memory bank and a plurality of mode registers that communicatively couple to each of the plurality of memory banks. The plurality of mode registers may include a pattern of data stored therein. The semiconductor device may also include a bank control that receives a write pattern command that causes the bank control to write the pattern of data into the memory bank, send a signal to a multiplexer to couple the plurality of mode registers to the memory bank, and write the pattern of data to the memory bank via the plurality of mode registers.

Abstract: A computing device includes an interface configured to interface and communicate with a storage network, a memory that stores operational instructions, and processing circuitry operably coupled to the interface and to the memory. The processing circuitry is configured to execute the operational instructions to perform various operations and functions. The computing device determines to execute maintenance operations on a set of memory devices, selects a subset of the set of memory devices for the maintenance operations and initiates execution of the maintenance operations on the subset of memory devices.

Abstract: A storage system and method for implementing an encoder, decoder, and/or buffer using a field programmable gate array are provided. In one embodiment, a storage system is provided with a field programmable gate array and a memory that stores sets of instruction code for the field programmable gate array. The sets of instruction code can be for different error decoder implementations, for providing an additional encoder and/or decoder, or for implementing a host memory buffer or a controller memory buffer.

Abstract: A method and an apparatus are provided for decoding a polar code. A simplified successive cancellation list (SSCL) decoding tree for the polar code is generated. The SSCL decoding tree includes a plurality of nodes. One or more nodes of the plurality of nodes are identified as employing Reed-Muller codes for decoding. Decoding of received log-likelihood ratios (LLRs) is performed using Reed-Muller codes at the one or more nodes. Hard decision values are output from the one or more nodes.

Abstract: Embodiments of this application provide a method for processing information bits in a wireless communication network. A device obtains a Polar encoded bit sequence, then divide the Polar encoded bit sequence into g groups that are of equal length N/g, wherein g is 32. The device block interleaves the g groups to obtain an interleaved bit sequence according to a sequence S, wherein the sequence S comprises: group numbers of the g groups, wherein a group whose number is 0 is the first element in the sequence S, wherein a group whose number is 12 is the 17th element in the sequence S, wherein a group whose number is 31 is the 32nd element in the sequence S, wherein the S is an integer and output the interleaved bit sequence.

Abstract: A transmission apparatus, in particular for use in a Low Throughput Network, comprises an FEC encoder configured to encode payload data into FEC code words each having a predetermined code word length, and a frame forming section configured to form a frame having a predetermined frame length. A frame comprises a first frame portion having a first predetermined length of an integer multiple of the predetermined code word length and a second frame portion having a second predetermined length shorter than the predetermined code word length. The frame forming section is configured to include an FEC code word and a predetermined number of repetitions of said FEC code word into the first frame portion of a frame and to include a selected number of bits of said FEC code word into the second frame portion of said frame.

Abstract: An error correction circuit includes: a first error correction encoder for generating a plurality of row-codewords by performing first error correction encoding on each of a plurality of messages; a second error correction encoder for generating a plurality of column-codewords; a first error correction decoder for performing first error correction decoding on each of read row-vectors corresponding to the plurality of row-codewords, and outputting a soft information of the first error correction decoding; and a second error correction decoder for determining whether each of m-bit symbols in read column-vectors corresponding to the column-codewords is reliable, based on the soft information corresponding to each of the p-bit symbols, and performing second error correction decoding on the read column-vectors, based on the determination of whether each of the m-bit symbols is reliable.

Abstract: A BASE-T Ethernet transceiver is disclosed. The transceiver includes a BASE-T Ethernet transmit circuit that employs a data framing module. The data framing module includes an input interface to receive Ethernet block data bits, and, forward error correction encoder is coupled to the logic to encode at least a first portion of the data bits to generate first error check bits. A Reed-Solomon (RS) encoder is coupled to the logic to encode at least a second portion of the data bits in accordance with a Reed-Solomon error code to generate second error check bits. A symbol mapper modulates the Ethernet block data bits in accordance with an SQ64 constellation comprising back-to-back PAM8 symbols.

Abstract: There is provided mechanisms for decoding an encoded sequence into a decoded sequence. A method is performed by an information decoder. The method comprises obtaining the encoded sequence. The encoded sequence has been encoded using a polar code. The method comprises successively decoding the encoded sequence into the decoded sequence. The decoding is performed for a given list size, LS, where LS>1, defining how many candidate decoded sequences in total the thus far decoded sequence is allowed to branch into during the decoding. The encoded sequence is decoded, until its first branching, by at least as many processing units in parallel as a factor, f, of the given list size. The factor is at least half the given list size, f?LS/2.

Abstract: Described herein is a system that includes a memory component and a processing device coupled to the memory component. The processing device identifies, in a test mode, a memory location of a memory component that is available to write test data, and detects a loss of power to the system while in the test mode. Responsive to detection of the loss of power, the processing device performs a continuous sequence of write operations to write the test data to the memory location using holdup energy until an amount of holdup energy is expended. After reboot of the system, the processing device determines a number of write operations successfully completed in the memory location by the continuous sequence of write operations before the amount of holdup energy is expended, and determines whether the number of write operations successfully completed satisfies a defect criterion.

Abstract: A method is used in validating data in a storage system. The method writes host data to the storage system during processing of a host I/O operation, where the host is in communication with the storage system. The storage system writes host data and test data associated with the host data to a storage device of the storage system. The method reads the host data and the test data from the storage device for validating the host data, and evaluates the test data to determine whether the host data has been written correctly by the storage system to the storage device. Upon determining that the host data has not been written correctly by the storage system to the storage device due to a failure, the method evaluates the test data to determine a cause of the failure.

Abstract: A method performed by a first communication device is disclosed herein. The first communication device operates in a communications network. The first communication device selects a first method to decode a physical broadcast channel from a plurality of methods to decode the physical broadcast channel. The plurality of methods to decode the physical broadcast channel comprises: a) single-shot decoding only, b) soft-combining decoding only, and c) both single-shot decoding and soft-combining decoding simultaneously. The selecting is based on whether or not a time index of a synchronization signal and physical broadcast channel block, SS/PBCH block, for transmitting primary and secondary synchronization signals and a physical broadcast channel is known by the first communication device. The first communication device then decodes the received physical broadcast channel based on the selected first method.

Abstract: A semiconductor memory device includes an error correction code (ECC) engine, a memory cell array, an input/output (I/O) gating circuit and a control logic circuit. The memory cell array includes a normal cell region configured to store main data and a parity cell region configured to selectively store parity data which the ECC engine generates based on the main data, and sub data received from outside of the semiconductor memory device. The control logic circuit controls the ECC engine to selectively perform an ECC encoding and an ECC decoding on the main data and controls the I/O gating circuit to store the sub data in at least a portion of the parity cell region.

Abstract: A method for error correction of logical pages of an erase block of a solid state drive (SSD) memory, the method may include determining an erase block score of the erase block, wherein the calculating is based on a program erase (PE) cycle of the erase block and one or more erase block error correction parameter; determining, based on (a) the erase block score, and (b) a mapping between the erase block score and one or more page error correction parameters for each page type out of multiple pages types, the one or more page error correction parameter for each page type; and allocating, within each page of the erase block, an overprovisioning space and an error correction space, based on at least one page error correction parameter related to a page type of the page.

Abstract: Various aspects of the disclosure relate to encoding information and decoding information. In some aspects, the disclosure relates to an encoder and a decoder for Polar codes with HARQ. If a first transmission of the encoder fails, information bits associated with a lower quality channel may be retransmitted. At the decoder, the resulting decoded retransmitted bits may be used to decode the first transmission by substituting the retransmitted bits for the original corresponding (low quality channel) bits. In some aspects, to decode the first transmission, soft-combining is applied to the decoded retransmitted bits and the original corresponding (low quality channel) bits. In some aspects, CRC bits for a first transmission may be split between a first subset of bits and a second subset of bits. In this case, the second subset of bits and the associated CRC bits may be used for a second transmission (e.g., a retransmission).

Abstract: A computing device includes an interface configured to interface and communicate with a dispersed or distributed storage network (DSN), a memory that stores operational instructions, and a processing module operably coupled to the interface and memory such that the processing module, when operable within the computing device based on the operational instructions, is configured to perform various operations. The computing device receives first samples corresponding to inputs that characterize configuration of the DSN and receives second samples corresponding to outputs that characterize system behavior of the DSN. The computing device then processes the first and samples to generate a DSN model to generate predictive performance of the outputs based on various values of the inputs. In some instances, the DSN model is based on a neural network model that employs the inputs that characterize the configuration of the DSN and generates the outputs that characterize system behavior of the DSN.

Abstract: There is provided a method of recursive sequential list decoding of a codeword of a polar code comprising: obtaining an ordered sequence of constituent codes usable for the sequential decoding of the polar code, representable by a layered graph; generating a first candidate codeword (CCW) of a first constituent code, the first CCW being computed from an input model informative of a CCW of a second constituent code, the first constituent code and second constituent code being children of a third constituent code; using the first CCW and the second CCW to compute, by the decoder, a CCW of the third constituent code; using the CCW of the third constituent code to compute a group of symbol likelihoods indicating probabilities of symbols of a fourth (higher-layer) constituent code having been transmitted with a particular symbol value, and using the group of symbol likelihoods to decode the fourth constituent code.

Abstract: Disclosed herein are methods, systems, and apparatus, including computer programs encoded on computer storage media, for storing blockchain data. One of the methods includes determining, by a blockchain node, one or more blocks that are infrequently visited; performing error correction coding of the one or more blocks to generate one or more encoded blocks; dividing, based on one or more predetermined rules, each of the one or more encoded blocks to a plurality of data sets; selecting one or more data sets from the plurality of data sets of each of the one or more encoded blocks based on the one or more predetermined rules; hashing the one or more data sets to generate one or more hash values corresponding to the one or more data sets; storing the one or more hash values; and deleting the one or more data sets.

Abstract: Methods and apparatus to dynamically assign and relocate object fragments in distributed storage systems are disclosed.

Abstract: Technologies for preserving error correction capability in compute-in-memory operations in a memory include memory media and a media access circuitry coupled with the memory media. The media access circuitry is to detect an error code adjustment state indicative of a failure in the initiated error correction. The media access circuitry is to adjust a voltage to the memory media to eliminate the error code correction adjustment state. Once eliminated, the media access circuitry is to perform the error correction on the read data.