Patents Examined by Mujtaba M. Chaudry
  • Patent number: 10884849
    Abstract: Provided are a computer program product, system, and method for mirroring information on modified data from a primary storage controller to a secondary storage controller for the secondary storage controller to use to calculate parity data. New primary parity data is calculated from modified data for a primary group of tracks in the primary storage and difference data from the modified data and a pre-modified version of the modified data. The difference data and one of the modified data and the new primary parity data are sent to the secondary storage controller to cause the secondary storage controller to write new secondary parity data and the modified data to a secondary group of tracks at the secondary storage. The modified data and the new primary parity data are written to the primary group of tracks in the primary storage.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: January 5, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lokesh M. Gupta, Matthew G. Borlick, Kevin J. Ash, John C. Elliott
  • Patent number: 10871910
    Abstract: In one embodiment, the disclosure teaches an apparatus including a memory array and a processor in communication with the memory array. The processor is configured to determine health scores of blocks of the memory array, where the health scores indicate the health of the blocks. The processor also is configured to receive data from a host, and select an interleaving scheme for programming the data based on the data type and a block to which the data is written based on the health scores. In one embodiment, sequential type data is written to unhealthy blocks and non-sequential data is written to healthy blocks.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: December 22, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Idan Alrod, Ariel Navon, Eran Sharon
  • Patent number: 10862620
    Abstract: A control unit of a multipath data transportation system that optimizes the load of the multiple communication paths of this system when the system transmits a data segment over these paths in parallel with forward error correction. The control unit determines an optimized number of packets to send over each path based on a prediction of quality for each path. The transmitted packets include systematic packets and coded packets.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: December 8, 2020
    Assignee: Dolby Laboratories Licensing Corporation
    Inventors: Mingchao Yu, Mark Craig Reed
  • Patent number: 10853171
    Abstract: A method for execution by an integrity processing unit includes performing a deterministic function on data for storage to produce an integrity value. The data and the integrity value are combined in accordance with a combining function to produce a data package. The processing system determines an encryption approach in response to determining to encrypt the data package. The data package is encrypted in accordance with the encryption approach to produce a secure package. The secure package is encoded to produce a set of slices. The set of slices is decoded to reproduce the secure package. The secure package is decrypted to reproduce the data package. The data package is de-combined in to generate reproduced data and a received integrity value. The deterministic function is performed on the data to produce a calculated integrity value, and the received integrity value is compared to the calculated integrity value.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: December 1, 2020
    Assignee: PURE STORAGE, INC.
    Inventors: Jason K. Resch, Wesley B. Leggette
  • Patent number: 10830815
    Abstract: A first score and a second score for each scan cell are first determined based on numbers of test cubes in a set of test cubes having a specified value of “1” and a specified value of “0” for the each scan cell, respectively. A ranking score for each test cube in the set of test cubes is then determined based on combining the first scores and the second scores corresponding to specified bits of the each test cube in the set of test cubes. Test cubes in the set of test cubes are merged according to a sequence based on the ranking scores in a test pattern generation process.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: November 10, 2020
    Assignee: Mentor Graphics Corporation
    Inventors: Janusz Rajski, Yu Huang
  • Patent number: 10831593
    Abstract: Hardware accelerator memory address translation fault resolution is provided. A hardware accelerator and a switchboard are in communication with a processing core. The hardware accelerator determines at least one memory address translation related to an operation having a fault. The operation and the fault memory address translation are flushed from the hardware accelerator including augmenting the operation with an entity identifier. The switchboard forwards the operation with the fault memory address translation and the entity identifier from the hardware accelerator to a second buffer. The operating system repairs the fault memory address translation. The operating system sends the operation to the processing core utilizing an effective address based on the entity identifier. The switchboard, supported by the processing core, forwards the operation with the repaired memory address translation to a first buffer and the hardware accelerator executes the operation with the repaired address.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Lakshminarayana B. Arimilli, Richard L. Arndt, Bartholomew Blaner
  • Patent number: 10831597
    Abstract: Provided are a computer program product, system, and method for receiving, at a secondary storage controller, information on modified data from a primary storage controller to use to calculate parity data. The secondary storage controller receives from the primary storage controller difference data calculated from modified data and a pre-modified version of the modified data for a primary group of tracks at the primary storage and one of the modified data and new primary parity data calculated at the primary storage controller from the modified data and the difference data. The secondary storage controller uses the difference data and one of the modified data and the new primary parity data to write new secondary parity data and the modified data to a secondary group of tracks at the secondary storage.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lokesh M. Gupta, Matthew G. Borlick, Kevin J. Ash, John C. Elliott
  • Patent number: 10824503
    Abstract: A semiconductor device may include a memory bank and a plurality of mode registers that communicatively couple to each of the plurality of memory banks. The plurality of mode registers may include a pattern of data stored therein. The semiconductor device may also include a bank control that receives a write pattern command that causes the bank control to write the pattern of data into the memory bank, send a signal to a multiplexer to couple the plurality of mode registers to the memory bank, and write the pattern of data to the memory bank via the plurality of mode registers.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: November 3, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Gary L. Howe
  • Patent number: 10812112
    Abstract: The invention relates to a soft input decoding method and a decoder for generalized concatenated (GC) codes. The GC codes are constructed from inner nested block codes, such as binary Bose-Chaudhuri-Hocquenghem, BCH, codes and outer codes, such as Reed-Solomon, RS, codes. In order to enable soft input decoding for the inner block codes, a sequential stack decoding algorithm is used. Ordinary stack decoding of binary block codes requires the complete trellis of the code. In one aspect, the present invention applies instead a representation of the block codes based on the trellises of supercodes in order to reduce the memory requirements for the representation of the inner codes. This enables an efficient hardware implementation. In another aspect, the present invention provides a soft input decoding method and device employing a sequential stack decoding algorithm in combination with list-of-two decoding which is particularly well suited for applications that require very low residual error rates.
    Type: Grant
    Filed: January 19, 2019
    Date of Patent: October 20, 2020
    Assignee: HYPERSTONE GMBH
    Inventors: Juergen Freudenberger, Jens Spinner, Christoph Baumhof
  • Patent number: 10810120
    Abstract: An encoder of a flash memory controller is provided, which includes a barrel shifter module, an inverse matrix calculating circuit and a calculating circuit. The barrel shifter module processes multiple data blocks to generate multiple partial parity blocks including a first portion, a second portion and a third portion. The inverse matrix calculating circuit performs inverse matrix calculating operations on the first portion to generate a first portion of parity blocks. The calculating circuit performs inverse matrix calculating operations on the second portion and the third portion according to the first portion of the parity blocks, to generate a second portion of the parity blocks and a third portion of the parity blocks. The first portion of the parity blocks, the second portion of the parity blocks, and the third portion of the parity blocks serve as multiple parity blocks generated in response to encoding the data blocks.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: October 20, 2020
    Assignee: Silicon Motion, Inc.
    Inventor: Shiuan-Hao Kuo
  • Patent number: 10804929
    Abstract: A wireless device generates a High Efficiency Signal B (HE-SIG-B) field by Block Convolution Code (BCC) encoding and rate-matching a BCC block of the HE-SIG-B field, generates a Physical Layer Protocol Data Unit (PPDU) including the HE-SIG-B field, and transmits the PPDU. A total number N is a total number of bits of the HE-SIG-B field that precede the BCC block, and is greater than 0. The BCC block has a puncturing pattern depending on the total number N. A wireless device receives a PPDU. The PPDU includes an HE-SIG-B field that includes an encoded BCC block. The wireless device de-rate-matches the encoded BCC block having a puncturing pattern depending on a total number N. The total number N is a total number of decoded bits of the HE-SIG-B field that preceded the BCC block, and the total number N is greater than 0.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: October 13, 2020
    Assignee: NEWRACOM, INC.
    Inventors: Dae Won Lee, Yujin Noh, Sungho Moon, Young Hoon Kwon
  • Patent number: 10802913
    Abstract: A solid state storage device using a prediction function is provided. The solid state storage device includes a control circuit and a non-volatile memory. The control circuit generates collection read operation commands. The collection read operation commands are temporarily stored in a command queue, and transmitted to the non-volatile memory. According to each of the collection read operation commands, the non-volatile memory generates a corresponding encoded read data to the control circuit. After the error correction circuit performs a decoding operation on the encoded read data, a decoded content is generated and a first count of the decoded content is transmitted to a first register of the register set. After the encoded read data is decoded, a value stored in the first register is a first parameter and the first parameter is inputted into a prediction function of the function storage circuit.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: October 13, 2020
    Assignee: SOLID STATE STORAGE TECHNOLOGY CORPORATION
    Inventors: Shih-Jia Zeng, Tsu-Han Lu, Hsiao-Chang Yen
  • Patent number: 10789012
    Abstract: A write method and a write apparatus for a storage device, where the write method includes: acquiring n numerical values that need to be written; determining n bits corresponding to the n numerical values, and information about a stuck-at fault included in the n bits; grouping the n bits into B groups of bits, so that the B groups of bits meet a grouping condition; and correspondingly writing the n numerical values according to information about a stuck-at fault included in each group of bits in the B groups of bits and a numerical value that needs to be written and that is corresponding to the information about the stuck-at fault included in each group of bits in the B groups of bits.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: September 29, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Jiwu Shu, Jie Fan, Guanyu Zhu
  • Patent number: 10790855
    Abstract: Field error correction coding is particularly suitable for applications in non-volatile flash memories. We describe a method for error correction encoding of data to be stored in a memory device, a corresponding method for decoding a codeword matrix resulting from the encoding method, a coding device, and a computer program for performing the methods on the coding device, using a new construction for high-rate generalized concatenated (GC) codes. The codes, which are well suited for error correction in flash memories for high reliability data storage, are constructed from inner nested binary Bose-Chaudhuri-Hocquenghem (BCH) codes and outer codes, preferably Reed-Solomon (RS) codes. For the inner codes extended BCH codes are used, where only single parity-check codes are applied in the first level of the GC code. This enables high-rate codes.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: September 29, 2020
    Assignee: HYPERSTONE GMBH
    Inventors: Juergen Freudenberger, Jens Spinner, Christoph Baumhof
  • Patent number: 10784988
    Abstract: Techniques are described for performing conditional forward error correction (FEC) of network data. The techniques and solutions can be applied to suppress the transmission of redundant forward error correction information for data (e.g., frames of audio and/or video data) that can be effectively recovered at the receiving device (e.g., at the decoder). For example, a first computing device that is encoding and transmitting data (e.g., encoded audio data) to a second computing device can determine whether portions of data can be predicted (e.g., to a certain quality measure) at the second computing device. If the portions of data can be predicted, then the first computing device can skip sending redundant copies of the portions of data (e.g., can skip sending forward error correction information) in current network packets.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: September 22, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Sriram Srinivasan, Soren Skak Jensen, Koen Bernard Vos
  • Patent number: 10769011
    Abstract: A memory device includes a semiconductor memory unit, a controller circuit configured to communicate with a host through a serial interface, store write data to be written into a page of the semiconductor memory unit in a data buffer, and an error-correcting code (ECC) circuit configured to generate an error correction code from the write data if the ECC circuit is enabled. The controller circuit writes the error correction code with the write data into the page if the ECC circuit is enabled. A maximum column address of the page which is accessible from the host changes depending on whether or not the ECC circuit is enabled.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: September 8, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shunsuke Kodera, Toshihiko Kitazume, Kenichirou Kada, Nobuhiro Tsuji, Shinya Takeda, Tetsuya Iwata, Yoshio Furuyama, Hirosuke Narai
  • Patent number: 10768231
    Abstract: “Shoot-through” timing failures in a scan chain of a defective semiconductor integrated circuit corrupt test pattern data used to perform failure analysis. Methods and procedures are provided to detect “shoot-through” conditions, determine the number of shoot-through scan cells, and to determine the location of the shoot-through cells within a scan chain. Reset test pattern results can be analyzed to identify candidate locations of shoot-through cells and when combined with candidate cell locations from analysis of physical clock distribution trees and potential clock-skew issues, the exact location of all shoot-through cells can be determined. Methods are also provided to use shoot-through cell locations to identify the defective clock net containing the physical defect causing the clock skew conditions needed to produce shoot-through timing failures.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: September 8, 2020
    Assignee: TESEDA CORPORATION
    Inventor: Theodore Clifton Bernard
  • Patent number: 10746792
    Abstract: An error-handling processing circuit and system are provided. The system can receive an error signal, such as an interrupt, and decouple (e.g., by a gate signal) a functional clock from a processing block, in some instances effectively halting the processing block's operation. This can prevent a cascade of interdependent errors, thereby avoiding producing redundant or confusing error information. The system can include the processing block, a debug clock not coupled to the processing block, and a data block (e.g., a register file) coupled to the debug clock and to an external input/output interface. The data block can be configured to continue receiving a clock signal via a multiplexer from the debug clock without disruption after the functional clock is decoupled, enabling the data block to remain operational for debugging.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: August 18, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Ron Diamant, Gil Stoler, Nafea Bshara
  • Patent number: 10746796
    Abstract: Configuration values for Lookup tables (LUTs) and programmable routing switches in an FPGA are provided by means of a number of flip flops arranges in a shift register. This shift register may receive test values in a factory test mode, and operational configuration values (implementing whatever functionality the client requires of the FPGA) in an operational mode. The bitstreams are provided at one end of the shift register, and clocked through until the last flip flop receives its value. Values may also be clocked out at the other end of the shift register to be compared to the initial bitstream in order to identify corruption of stored values e.g. due to radiation exposure. A clock gating architecture is proposed for loading data to or reading data from specific selected shift registers.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: August 18, 2020
    Assignee: MENTA
    Inventors: Laurent Rouge, Julien Eydoux, Marcello Giuffre
  • Patent number: 10749628
    Abstract: A terminal apparatus (1) is provided with a coding unit (7), a decoding unit (2), and a control unit (5) for controlling the coding unit and the decoding unit individually. Under control of the control unit, the coding unit codes a payload, a first number of error corrections (3), and identification information (6) that are to be transmitted, on the basis of a method indicated by the already-transmitted identification information to thereby generate first coded data. The decoding unit decodes newly-received second coded data on the basis of a method indicated by the identification information included in a decoding result of the already-received second coded data.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: August 18, 2020
    Assignee: NEC CORPORATION
    Inventor: Tatsuhiro Nakada