Abstract: Systems and methods are disclosed for providing H-ARQ transmissions in respect of a set of horizontal code blocks are combined in a code. Retransmissions contain vertical parity check blocks which are determined from verticals from the set of horizontal code blocks. Once all the vertical parity check blocks have been transmitted, a new set may be determined after performing interleaving upon either the content of the horizontal code blocks, in the case of non-systematic horizontal code blocks, or over the content of encoder input bits in the place of systematic horizontal code blocks. The interleaving may be bitwise or bit subset-wise. The retransmissions do not contain any of the original bits. In the decoder, soft decisions are produced, and nothing needs to be discarded; decoding will typically improve with each retransmission.

Abstract: Method for testing an integrated circuit device, by defect modelling of the integrated circuit device, fault modelling of the integrated circuit device based on the information obtained from the defect modelling, test development based on information obtained from the fault modelling, and executing the test on the integrated circuit device. Defect modelling of the integrated circuit device including executing a physical defect analysis of the integrated circuit device to provide a set of effective technology parameters modified from a set of defect-free technology parameters associated with the integrated circuit device, and executing an electrical modelling of the integrated circuit device using the set of effective technology parameters to provide a defect-parametrized electrical model based on a defect-free electrical model of the integrated circuit device. The present methods allow parts-per-billion testing capabilities.

Abstract: Embodiments of this application disclose a polar coding method, apparatus, and device, so as to reduce storage overheads of a system. A sequence for polar coding is obtained based on a length M of a target polar code, wherein the sequence comprises L sequence numbers, ordering of the L sequence numbers in the sequence is the same as ordering of the L sequence numbers in a maximum mother code sequence, wherein the maximum mother code sequence is obtained by sorting N sequence numbers of N polarized channels in ascending order or descending order of reliability metrics, wherein L and N are integer power of 2, M is smaller than or equal to L, L is smaller than or equal to N.

Abstract: A method of communication on a shared media having a plurality of devices coupled thereto, the method including: forming a first portion including information on a property of a data signal and complying with a communication protocol; forming a second portion comprising data that differs from the information on the property provided in the first portion, where the second portion is non-compliant with the communication protocol; forming a third portion comprising an error check character to verify that the data signal is error free, where the error check character is purposefully set to be an incorrect value and otherwise complying with the communication protocol; and transmitting the data signal including the first, second, and third portions on the shared media, whereby a first of the plurality of devices that complies with the communication protocol is configured to reject the data signal due to the purposefully incorrect error check character.

Abstract: Test packets may be received at a design under test (DUT) from an automated test equipment (ATE) over a serializer/deserializer (SERDES) connection between the ATE and the DUT. The test packets may include test pattern data to test the DUT. The test pattern data may be applied to the DUT using a set of scan chains and test response data corresponding to the test pattern data may be obtained. The test response data may be received by a circuit in the DUT at irregular time intervals. Response packets may be sent to the ATE by the circuit in the DUT at regular time intervals, where the response packets may include a portion of the test response data (which may be encoded using an encoding technique), and where the response packets may be sent to ATE over the SERDES connection.

Abstract: Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a multi-chip module (MCM) is disclosed. The MCM includes a first integrated circuit (IC) chip including a first interface defining a first number of interface contacts. Conversion circuitry receives a first full set of signals associated with the first interface and to omit a subset of the full set of signals to generate a reduced set of signals. Serialization circuitry serializes the reduced set of signals to generate a serialized set of signals. A second interface transmits the serialized set of signals with a second number of interface contacts that is less than the first number of interface contacts. A logic IC chip includes a third interface coupled to the second interface via a set of links and configured to match the second interface. Deserialization circuitry deserializes the serialized set of signals.

Abstract: A Bluetooth receiver is provided. The Bluetooth receiver comprises interface circuitry configured to receive a receive packet. Further, the Bluetooth receiver comprises physical layer processing circuitry configured to demodulate the receive packet into a bit stream representing a sequence of data symbols. Further, the physical layer configured to determine a number of bits in the bit stream having a highest likelihood of being erroneous as weak-bits and determine locations of the identified weak-bits in the bit stream. The Bluetooth receiver further comprises medium access control layer processing circuitry configured to receive the bit stream and information about the determined locations of the identified weak-bits from the physical layer processing circuitry.

Abstract: A programmable crossbar matrix or an array of steering multiplexors (MUXs) coalesces (i.e., routes) the data values from multiple known “bad” bit positions within multiple symbols of a codeword, to bit positions within a single codeword symbol. The single codeword symbol receiving the known “bad” bit positions may correspond to a check symbol (vs. a data symbol). Configuration of the routing logic may occur at boot or initialization time. The configuration of the routing logic may be based upon error mapping information retrieved from system non-volatile memory (e.g., memory module serial presence detect information), or from memory tests performed during initialization. The configuration of the routing logic may be changed on a per-rank basis.

Abstract: The application relates to the adaptation of the length of the cyclic redundancy check (CRC) code in the context of 3GPP NR. In 3GPP NR, the length of the uplink and downlink control information (UCI, DCI) significantly varies. Therefore, it is necessary to select a CRC code of appropriate size or length. Accordingly, a method (200) for use in a wireless transmitter comprises: determining an amount of data to transmit (212); determining a cyclic redundancy check (CRC) polynomial length based on the amount of data to transmit (214); encoding the data using a CRC of the determined polynomial length (216); and transmitting the encoded data (216). The data to transmit may not only comprise control channel data but also user data and may be encoded with a Polar code or a low-density parity check (LDPC) code.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may receive, from a base station, a physical downlink shared channel (PDSCH) transmission in one or more of a half-duplexing mode or a full-duplexing mode. The UE may attempt to decode the PDSCH transmission using a low-density parity-check (LDPC) decoder. The UE may transmit, to the base station, feedback that indicates a difference between a half-duplex channel quality and a full-duplex channel quality based at least in part on one or more decoding parameters associated with the LDPC decoder. Numerous other aspects are described.

Abstract: An apparatuses for radio access network configuration for video approximate semantic communications includes a transceiver that receives from a transmitter a bitstream corresponding to a video coded data transmission wherein the received bitstream includes bitwise transmission errors and a processor that performs FEC decoding and correcting at least one bitwise transmission error of the video coded data transmission whereas at least one bitwise transmission error is left in a bit-inexact reception of the video coded data transmissions post FEC decoding, applies, by a smart video decoder in a video approximate semantic communications mode, semantic error correction to decoded video coded data transmissions to correct and conceal one or more video artifacts in response to the bit-inexact reception of the video coded data transmissions post FEC decoding, and reconstructs a video uncoded representation of concealed approximate semantic content relative to the received bitstream corresponding to the video coded da

Abstract: A plurality of codewords are programmed to one or more memory pages of a memory sub-system. Each memory page of the memory sub-system is associated with a logical unit of a plurality of logical units of the memory sub-system and at least one of a plane of a plurality of planes of the memory sub-system or a block of a plurality of blocks of the memory sub-system. Each codeword of the plurality of codewords comprises host data and base parity bits. A plurality of additional parity bits are programmed to the one or more memory pages of the memory sub-system, wherein each additional parity bit of the plurality of additional parity bits is associated with a codeword of the plurality of standard codewords. A first set of redundancy metadata is generated corresponding to each of the additional parity bits. The first set of redundancy metadata is programmed to a memory page separate from any memory page storing the additional parity bits.

Abstract: It provides a method (300) for polar decoding a received signal into a number, N, of bits with Successive Cancellation List, SCL. The method (300) includes: at the i-th level of a binary tree for decoding the i-th bit of the N bits, where 1?i?N: when the i-th bit is an information bit, calculating (310) a path metric for each of 2*Li-1 candidate paths at the i-th level, where Li-1 is an SCL size at the (i?1)-th level and L0=1; setting (320) an SCL size at the i-th level, Li, based on Li-1 and a statistical distribution of the path metrics calculated for the 2*Li-1 candidate paths; and selecting (330) Li surviving paths from the 2*Li-1 candidate paths based on their respective path metrics.

Abstract: With rapid increase in wired/wireless communication traffic and data storage requirements, the performance of error correction codes and data security solutions is become crucial. Random-like codes can be used in symmetric data encryption, cryptographic hash functions, random number/sequence generators, error correction and detection codes, and other data security applications. The present disclosure provides systems and methods that implement a dynamic permutation based coding approach of input based permutation/remapping/repositioning sequence generation. As the encoding process is defined using input bits, the output of the proposed codes depends on the statistic of input bits rather than any fixed predefined encoding structure. This dynamic encoding method can facilitate to implement strong confusion-diffusion logic and randomness in symmetric cryptography, hash functions, error correction codes, and other data security and authentication areas.

Abstract: Aspects of the disclosure relate to wireless communication systems configured to provide techniques for multiplexing dedicated control information for a plurality of users in a single information block and polar coding the information block to produce a polar code block of dedicated control information for transmission over a wireless air interface. The information block may further include group cyclic redundancy check (CRC) information for the information block and individual CRC information for each dedicated control information.

Abstract: A decoding system, a decoding controller, and a decoding control method are provided. In the decoding system, a decoding controller is disposed between two adjacent decoders. The decoding controller determines whether to perform turn-off based on a non-turn-off indication received by a previous-stage decoder, a turn-off indication output by the previous-stage decoder, and historical turn-off probability statistics. This is equivalent to adding a buffer zone between the two adjacent decoders.

Abstract: An information processing apparatus includes: a decoding module, configured to receive M first codewords from at least one peer device, where each first codeword includes first service data with a K-unit length and an error correction code with an R-unit length, where the decoding module is further configured to decode the M first codewords to obtain M second codewords, where a length of each second codeword is a sum of the K-unit length and the R-unit length, each second codeword includes second service data with the K-unit length and error correction information, the second service data is error-corrected first service data; and a classification and statistics collection module, configured to determine a bit error rate of the first service data based on the error correction information.

Abstract: A network node device of a communication network comprises physical (PHY) layer circuity configured to transmit and receive data packets via a communication network; and processing circuitry connected to the PRY layer circuitry. The processing circuitry is configured to encode a data packet for sending according to a first communication protocol for sending to a second network node during a specified communication time slot, initiate resending of the data packet when the second network node does not respond during a specified acknowledge time slot, and encode the data packet according to a second communication protocol for sending to the second network node for a last retry attempt of a finite number of retry attempts, wherein the time to send the data packet formatted in the second communication protocol extends into the specified acknowledge time slot.

Abstract: A first pool of blocks of a memory device is determined, wherein blocks of the first pool are associated with storing system data at a single bit per memory cell. A second pool of blocks of the memory device is determined, wherein blocks of the second pool are associated with storing user data at a plurality of bits per memory cell. In response to detecting a failure associated with a particular block of the second pool of blocks, the particular block is added to the first pool of blocks.

Abstract: Embodiments herein relate to, e.g., a method performed by a communication node for controlling one or more communication parameters of a channel between a first communication device and a second communication device in a wireless communication network. The communication node, upon obtaining an indication of a channel quality of the channel to the second communication device, uses a correction value and the indication when determining the one or more communication parameters. The correction value is based on a decoding success of one or more previous transmissions, which one or more previous transmissions are based on an obtained previous indication of a previous channel quality from the second communication device, and wherein a change of the correction value relative a previous correction value is limited.